RICOH RV5C386A_03

I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
WITH VOLTAGE MONITORING FUNCTION
NO.EA-079-0208
RV5C386A
OUTLINE
The RV5C386A is a CMOS real-time clock IC connected to the CPU by two signal lines, SCL and SDA, and
configured to perform serial transmission of time and calendar data to the CPU. The periodic interrupt circuit is
configured to generate interrupt signals with six selectable interrupts ranging from 0.5 seconds to 1 month. The 2
alarm circuits generate interrupt signals at preset times. The oscillation circuit is driven under constant voltage so
that fluctuations in oscillation frequency due to voltage are small and supply current is also small (TYP. 0.35µA at 3
volts). The oscillation halt sensing circuit can be used to judge the validity of internal data in such events as poweron. The supply voltage monitoring circuit is configured to record a drop in supply voltage below two selectable
supply voltage monitoring threshold settings. The 32-kHz clock output function (CMOS push-pull) is intended to
output sub-clock pulses for the external microcomputer. The 32-kHz clock circuit can be disabled by certain input
pin. The oscillation adjustment circuit is intended to adjust time counts with high precision by correcting deviations
in the oscillation frequency of the crystal oscillator. This model comes in an ultra-compact 10-pin SSOP-G (with a
height of 1.20mm and a pin pitch of 0.5mm).
FEATURES
• Timekeeping supply voltage ranging from 1.45 to 5.5 volts
• Low supply current: TYP. 0.35µA (MAX. 0.8µA) at 3 volts
• Only two signal lines (SCL, SDA) required for connection to the CPU.
(I2C bus compatible, 400kHz at VDD≥2.5V, address 7bits)
• Time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months, days,
and weeks) (in BCD format)
• 1900/2000 identification bit for Year 2000 compliance
• Interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1 month)
to the CPU and provided with an interrupt flag and an interrupt halt circuit
• 2 alarm circuits (Alarm_W for week, hour, and minute alarm settings and Alarm_D for hour and minute
alarm settings)
• 32-kHz clock circuit (CMOS output, equipped with a control pin)
• Oscillation halt sensing circuit which can be used to judge the validity of internal data
• Supply voltage monitoring circuit with two supply voltage monitoring threshold settings
• Automatic identification of leap years up to the year 2099
• Selectable 12-hour and 24-hour mode settings
• Built-in oscillation stabilization capacitors (CG and CD)
• High precision oscillation adjustment circuit
• CMOS process
• Ultra-compact 10-pin SSOP-G(with a height of 1.20mm and size 4.0mm×2.9mm)
1
RV5C386A
Note
2
· I C bus is a trademark of PHILIPS ELECTRONICS N.V.
· Purchase of I2C components of Ricoh Company, Ltd. conveys a license under the Philips I2C Patent Rights to
use these components in an I 2 C system, provided that the system comforms to the I 2 C Standard
Specification as defined by Philips.
BLOCK DIAGRAM
32KOUT
CLKC
32kHz
OUTPUT
CONTROL
OSCIN
OSC
OSCOUT
COMPARATOR_W
ALARM_W REGISTER
(MIN,HOUR,WEEK)
COMPARATOR_D
ALARM_D REGISTER
(MIN,HOUR)
VDD
DIVIDER
CORREC
-TION
VSS
TIME COUNTER
(SEC,MIN,HOUR,WEEK,DAY,MONTH,YEAR)
DIV
OSC
DETECT
SCL
ADDRESS
REGISTER
ADDRESS
DECODER
I/O
CONTROL
INTRA
INTRB
VOLTAGE
DETECT
INTERRUPT CONTROL
SHIFT REGISTER
APPLICATIONS
• Communication devices (multi function phone, portable phone, PHS or pager)
• OA devices (fax, portable fax)
• Computer (desk-top and mobile PC, portable word-processor, PDA, electric note or video game)
• AV components (portable audio unit, video camera,camera, digital camera or remote controller)
• Home appliances (rice cooker, electric oven)
• Other (car navigation system, multi-function watch)
PIN CONFIGURATION
• 10-pin SSOP-G
2
32KOUT
1
10
SCL
2
9
OSCIN
SDA
3
8
OSCOUT
INTRB
4
7
CLKC
VSS
5
6
INTRA
VDD
SDA
RV5C386A
PIN DESCRIPTIONS
Pin No. Symbol
Item
Description
This pin is used to input shift clock pulses to synchronize data input/output to and
2
SCL
Serial clock line
from the SDA pin with this clock. Allows a maximum input voltage of 5.5 volts
regardless of supply voltage.
This pin inputs and outputs written or read data in synchronization with shift clock
3
SDA
Serial data line
pulses from the SCL pin. Allows a maximum input voltage of 5.5 volts regardless
of supply voltage.
6
INTRA
Interrupt output A
4
INTRB
Interrupt output B
1
32KOUT 32-kHz Clock Output
This pin outputs periodic interrupt pulses and alarm interrupt (Alarm_D) to the
CPU. This pin is off when power is activated from 0V. Nch. open drain output.
This pin is used to output alarm interrupt signals(Alarm_W) to the CPU. This pin
is off when power is activated from 0V. Nch. open drain output.
The 32KOUT pin is used to output 32.768kHz clock pulses. CMOS push-pull
output. The output is disabled if the CLKC pin is set to “L” or open.
The CLKC pin is used to control output of the 32KOUT pin. The clock output is
7
CLKC
Clock Control Input disabled and held low when the pin is set to “L”or open. Incorporates a pull down
resistor.
9
OSCIN
Oscillatory Circuit
The OSCIN and OSCOUT pins are used to connect the 32.768-kHz crystal
8
OSCOUT
Input/Output
oscillator (with all other oscillation circuit components built into the RV5C386A).
10
VDD
Positive Power Supply Input
5
VSS
Negative Power Supply Input
The VDD pin is connected to the power supply. The VSS pin is grounded.
3
RV5C386A
ABSOLUTE MAXIMUM RATINGS
(Vss=0V)
Symbol
Item
Ratings
Unit
–0.3 to +6.5
V
SCL, SDA, CLKC
–0.3 to +6.5
V
Output Voltage 1
SDA, INTRA, INTRB
–0.3 to +6.5
Output Voltage 2
32KOUT
–0.3 to VDD+0.3
Power Dissipation
Topt=25˚C
300
mW
VDD
Supply Voltage
VI
Input Voltage 2
Conditions
VO
PD
V
Topt
Operating Temperature
–40 to +85
˚C
Tstg
Storage Temperature
–55 to +125
˚C
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum ratings are threshold limit values that must not be exceeded even for an instant under
any conditions. Moreover, such values for any two items must not be reached simultaneously. Operation
above these absolute maximum ratings may cause degradation or permanent damage to the device. These
are stress ratings only and do not necessarily imply functional operation below these limits.
RECOMMENDED OPERATING CONDITIONS
(Vss=0V,Topt=–40 to +85˚C)
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VDD
Supply Voltage
2.0
5.5
V
VCLK
Timekeeping Voltage
1.45
5.5
V
fXT
Oscillation Frequency
VPUP
4
Item
Pull-up Voltage
32.768
SCL, SDA, INTRA, INTRB
kHz
5.5
V
RV5C386A
DC ELECTRICAL CHARACTERISTICS
Unless otherwise specified : Vss=0V,VDD=3V,Topt=–40 to +85˚C
Symbol
VIH
Item
Pin name
“H” Input Voltage
SCL,SDA, CLKC
VIL
“L” Input Voltage
IOH
“H” Output Current
“L” Output Current
IOL3
IIL
ICLKC
IOZ
32KOUT
INTRA, INTRB
Pull Dwon Resistancs
Input Current
Output Off-state
Current
CLKC
SDA, INTRA, INTRB
TYP.
MAX.
0.8VDD
5.5
–0.3
0.2VDD
VOH=VDD–0.5V
–0.5
Unit
V
mA
0.5
VOL=0.4V
SDA
Input Leakage Current SCL
MIN.
VDD=2.5 to 5.5V
32KOUT
IOL1
IOL2
Conditions
1.0
mA
4.0
VI=5.5V or Vss
VDD=5.5V
–1
VI=5.5V
Vo=5.5V or Vss
VDD=5.5V
1
µA
1.0
µA
1
µA
0.35
0.8
µA
0.35
–1
VDD=3V,
SCL=SDA=3V,
IDD
Timekeeping Current
VDD
Output=OPEN*1
CLKC=“L”
VDETH
VDETL
Supply Voltage Monitoring
Voltage (“H”)
Supply Voltage Monitoring
Voltage (“L”)
VDD
Topt=–30 to +70˚C
1.90
2.10
2.30
V
VDD
Topt=–30 to +70˚C
1.45
1.60
1.80
V
CG
Internal Oscillation Capacitance 1 OSCIN
12
CD
Internal Oscillation Capacitance 2 OSCOUT
12
pF
*1)
For standby current for outputting 32.768-kHz clock pulses from the 32KOUT pin, see “USAGES, 7. Typical Characteristics”.
5
RV5C386A
AC ELECTRICAL CHARACTERISTICS
Unless otherwise specified : VSS=0V, Topt=–40 to +85˚C
I/O conditions: VIH=0.8×VDD, VIL=0.2×VDD, VOL=0.2×VDD, CL=50pF
Symbol
Item
Conditions
VDD≥2.0V
MIN.
TYP.
VDD≥2.5V
MAX.
MIN.
TYP.
MAX.
fSLC
SCL clock frequency
tLOW
SCL clock “L” time
4.7
1.3
µs
tHIGH
SCL clock “H” time
4.0
0.6
µs
tHD ; STA
Start condition hold time
4.0
0.6
µs
tSU ; STO
Stop condition setup time
4.0
0.6
µs
tSU ; STA
Start condition setup time
4.7
0.6
µs
tSU ; DAT
Data setup time
250
200
ns
tHD ; DAT
Data hold time
0
0
ns
tPL ; DAT
SDA “L” stable time after falling of SCL
2.0
0.9
µs
tPZ ; DAT
SDA off stable time after falling of SCL
2.0
0.9
µs
tR
Rising time of SCL and SDA (input)
1000
300
ns
tF
Falling time of SCL and SDA (input)
300
300
ns
50
50
ns
tSP
100
Spike width that can be removed
with input filter
S
400
Sr
P
SCL
tLOW
tHD;STA
tHIGH
tSP
SDA(IN)
tHD;STA
tSU;DAT
tHD;DAT
SDA(OUT)
tPL;DAT
S Start condition
tPZ;DAT
P Stop condition
Sr Repeated start condition
*)
6
Unit
For read/write timing, see “USAGES, 1.5 Considerations in Reading and Writing Time Data”.
tSU;STA
tSU;STO
kHz
RV5C386A
GENERAL DESCRIPTION
1. Interface with CPU
The RV5C386A is connected to the CPU by two signal lines SCL and SDA, through which it reads and writes data
from and to the CPU. Since the output of the I/O pin of SDA is open drain, data interfacing with a CPU different
supply voltage is possible by applying pull-up resistors on the circuit board. The maximum clock frequency of
400kHz (at VDD≥2.5V) of SCL enables data transfer in I2C bus fast mode.
2. Clock and Calendar Function
The RV5C386A reads and writes time data from and to the CPU in units ranging from seconds to the last two digits
of the calendar year. The calendar year will automatically be identified as a leap year when its last two digits are a
multiple of 4. Also available is the 1900/2000 identification bit for Year 2000 compliance. Consequently, leap years
up to the year 2099 can automatically be identified as such.
*)
The year 2000 is a leap year while the year 2100 is not a leap year.
3. Alarm Function
The RV5C386A incorporates an alarm circuit configured to generate interrupt signals to the CPU for output at
preset times. The alarm circuit allows two types of alarm settings specified by the Alarm_W registers and the
Alarm_D registers. The Alarm_W registers allow week, hour, and minute alarm settings including combinations of
multiple day-of-week settings such as “Monday, Wednesday, and Friday” and “Saturday and Sunday”. The Alarm_D
registers allow hour and minute alarm settings. The Alarm_W signal outputs from INTRB pin, and the Alarm_D
signal outputs from INTRA pin. The current INTRA or INTRB pin conditions specified by the flag bits for each
alarm function can be checked from the CPU by using a polling function.
4. High-precision Oscillation Adjustment Function
The RV5C386A has built-in oscillation stabilization capacitors (CG and CD), which can be connected to an external
crystal oscillator to configure an oscillation circuit. To correct deviations in the oscillation frequency of the crystal
oscillator, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss (up to
±1.5ppm at 25˚C) from the CPU within a maximum range of approximately ±189ppm in increments of approximately
3ppm. Such oscillation frequency adjustment in each system has the following advantages:
· Allows timekeeping with much higher precision than conventional real-time clocks while using a crysta
l oscillator with a wide range of precision variations.
· Corrects seasonal frequency deviations through seasonal oscillation adjustment.
· Allows timekeeping with higher precision particularly in systems with a temperature sensing function
through oscillation adjustment in tune with temperature fluctuations.
7
RV5C386A
5. Oscillation Halt Sensing Function and Supply Voltage Monitoring Function
The RV5C386A incorporates an oscillation halt sensing circuit equipped with internal registers configured to record
any past oscillation halt, thereby identifying whether they are powered on from 0 volts or battery backed-up. As
such, the oscillation halt sensing circuit is useful for judging the validity of time data.
The RV5C386A also incorporates a supply voltage monitoring circuit equipped with internal registers configured to
record any drop in supply voltage below a certain threshold value. Supply voltage monitoring threshold settings can
be selected between 2.1 and 1.6 volts through internal register settings.
The oscillation halt sensing circuit is configured to confirm the established invalidation of time data in contrast to
the supply voltage monitoring circuit intended to confirm the potential invalidation of time data. Further, the supply
voltage monitoring circuit can be applied to battery supply voltage monitoring.
6. Periodic Interrupt Function
The RV5C386A incorporates a periodic interrupt circuit configured to generate periodic interrupt signals aside from
interrupt signals generated by the alarm circuit for output from the INTRA pin. Periodic interrupt signals have five
selectable frequency settings of 2Hz (once per 0.5 seconds), 1Hz (once per 1 second), 1/60Hz (once per 1 minute),
1/3600Hz (once per 1 hour), and monthly (the first day of every month). Further, periodic interrupt signals also
have two selectable waveforms of a normal pulse form (with a frequency of 2Hz or 1Hz) and special form adapted to
interruption from the CPU in the level mode (with second, minute, hour, and month interrupts). The register
records of periodic interrupt signals can be monitored by using a polling function.
7. 32-kHz Clock Output Function
The RV5C386A incorporates a 32-kHz clock circuit configured to generate clock pulses with the oscillation
frequency of a 32.768kHz crystal oscillator for output from the 32KOUT pin (CMOS push-pull output). The 32-kHz
clock output is enabled and disabled when the CLKC pin is held “H”, and “L” or open, respectively.
8
RV5C386A
FUNCTIONAL DESCRIPTIONS
1. Address Mapping
D7
D6
D5
Data*1
D4
D3
Second Counter
–*2
S40
S20
S10
S8
S4
S2
S1
1
Minute Counter
–
M40
M20
M10
M8
M4
M2
M1
1
0
Hour Counter
–
–
H10
H8
H4
H2
H1
0
1
1
Day-of-week Counter
–
–
–
–
–
W4
W2
W1
0
1
0
0
Day-of-month Counter
–
–
D20
D10
D8
D4
D2
D1
5
0
1
0
1
Month Counter and Century Bit 19/20
–
–
MO10
MO8
MO4
MO2
MO1
6
0
1
1
0
Year Counter
Y80
Y40
Y20
Y10
Y8
Y4
Y2
Y1
7
0
1
1
1
Oscillation Adjustment Register*3
–
F6
F5
F4
F3
F2
F1
F0
8
1
0
0
0
Alarm_W (minute register)
–
WM4
WM2
WM1
9
1
0
0
1
Alarm_W (hour register)
–
–
A
1
0
1
0
Alarm_W (Day-of-week register)
–
WW6
B
1
0
1
1
Alarm_D (minute register)
–
C
1
1
0
0
Alarm_D (hour register)
–
–
D
1
1
0
1
–
–
E
1
1
1
0
Control Register 1*3
WALE DALE 12/24 SCRATCH3 TEST
F
1
1
1
1
Control Register 2*3
VDSL VDET SCRATCH1 XSTP SCRATCH2 CTFG WAFG DAFG
Address
A3
A2
A1
A0
0
0
0
0
0
1
0
0
0
2
0
0
3
0
4
Register
H20
P/A
WM40 WM20 WM10 WM8
WH20
D2
D1
D0
WH10
WH8
WH4
WH2
WH1
WW5
WW4
WW3
WW2
WW1
WW0
DM40 DM20
DM10
DM8
DM4
DM2
DM1
DH10
DH8
DH4
DH2
DH1
–
–
–
–
–
CT2
CT1
CT0
WP/A
DH20
DP/A
–
*1) All the data listed above accept both reading and writing.
*2) The data marked with “–” is invalid for writing and reset to 0 for reading.
*3) When the XSTP bit is set to 1 in control register 2, all the bits are reset to 0 in oscillation adjustment register 1, control register 1 and control register 2
excluding the XSTP bit.
9
RV5C386A
2. Register Settings
2.1 Control Register 1 (at Address Eh)
D7
D6
D5
D4
D3
D2
D1
D0
WALE
DALE
12/24
SCRATCH3
TEST
CT2
CT1
CT0
(For writing)
WALE
DALE
12/24
SCRATCH3
TEST
CT2
CT1
CT0
(For reading)
0
0
0
0
0
0
0
0
*)
Default settings*1
Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop.
2.1-1 WALE and DALE
Alarm_W Enable Bit and Alarm_D Enable Bit
WALE, DALE
Description
Disabling the alarm interrupt circuit (under the control of the settings of the
Alarm_W registers and the Alarm_D registers).
0
(Default setting)
Enabling the alarm interrupt circuit (under the control of the settings of the
1
Alarm_W registers and the Alarm_D registers)
2.1-2 12/24
12-/24-hour Mode Selection Bit
12/24
Description
0
Selecting the 12-hour mode with a.m. and p.m. indications.
1
Selecting the 24-hour mode
(Default setting)
Setting the 12/24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively.
Table of Time Digit Indications
*)
10
24-hour mode
12-hour mode
24-hour mode
12-hour mode
00
01
02
03
04
05
06
07
08
09
10
11
12 (AM12)
01 (AM 1)
02 (AM 2)
03 (AM 3)
04 (AM 4)
05 (AM 5)
06 (AM 6)
07 (AM 7)
08 (AM 8)
09 (AM 9)
10 (AM10)
11 (AM11)
12
13
14
15
16
17
18
19
20
21
22
23
32 (PM12)
21 (PM 1)
22 (PM 2)
23 (PM 3)
24 (PM 4)
25 (PM 5)
26 (PM 6)
27 (PM 7)
28 (PM 8)
29 (PM 9)
30 (PM10)
31 (PM11)
Setting the 12/24 bit should precede writing time data.
RV5C386A
2.1-3 SCRATCH3
Scratch Bit 3
SCRATCH3
Description
(Default setting)
0
1
The SCRATCH3 bit is intended for scratching and accepts the reading and writing of 0 and 1. The SCRATCH3 bit
will be set to 0 when the XSTP bit is set to 1 in the control register 2.
2.1-4 TEST
Test Bit
TEST
Description
0
Normal operation mode
1
Test mode
(Default setting)
The TEST bit is used only for testing in the factory and should normally be set to 0.
11
RV5C386A
2.1-5 CT2, CT1, and CT0
Periodic Interrupt Selection Bits
Description
CT2
CT1
CT0
Waveform Mode
Interrupt Cycle and Fall Timing
0
0
0
—
Off (“H”)
0
0
1
—
Fixed at low (“L”)
0
1
0
Pulse Mode
2Hz (Duty cycle of 50%)
0
1
1
Pulse Mode
1Hz (Duty cycle of 50%)
1
0
0
Level Mode
Once per 1 second (Synchronized with second counter increment)
1
0
1
Level Mode
Once per minute (at 00 seconds of every minute)
1
1
0
Level Mode
Once per hour (at 00 minutes and 00 seconds of every hour)
1
1
1
Level Mode
Once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month)
(Default setting)
1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second counter
as illustrated in the timing chart on the next page.
2) Level Mode: periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute,
1 hour, and 1 month. The increment of the second counter is synchronized with the falling edge of
periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting
of 1 second are output in synchronization with the increment of the second counter as illustrated
in the timing chart on the next page.
3) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20 seconds as follows:
Pulse Mode: the “L” period of output pulses will increment or decrement by a maximum of ±3.784ms.
For example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%.
Level Mode: a periodic interrupt cycle of 1 second will increment or decrement by a maximum of ±3.784ms.
12
RV5C386A
Relation Between the Mode Waveform and the CTFG Bit
• Pulse mode
CTFG bit
INTRA pin
Approx. 92µs
(Increment of second counter)
*)
Rewriting of the second counter
In the pulse mode, the increment of the second counter is delayed by approximately 92µs from the falling edge of clock pulses. Consequently, time
readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second.
Rewriting the second counter will reset the other time counters of less than 1 second, driving the INTRA pin low.
• Level mode
CTFG bit
INTRA pin
Setting CTFG bit to 0
(Increment of
second counter)
(Increment of
second counter)
Setting CTFG bit to 0
(Increment of
second counter)
13
RV5C386A
2.2 Control Register 2 (at Address Fh)
D7
D6
D5
D4
D3
D2
D1
D0
VDSL
VDET
SCRATCH1
XSTP
SCRATCH2
CTFG
WAFG
DAFG
(For write operation)
VDSL
VDET
SCRATCH1
XSTP
SCRATCH2
CTFG
WAFG
DAFG
(For read operation)
0
0
0
1
0
0
0
0
*)
Default setting*1
Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop.
2.2-1 VDSL
Supply Voltage Monitoring Threshold Selection Bit
VDSL
Description
0
Selecting the supply voltage monitoring threshold setting of 2.1 volts.
1
Selecting the supply voltage monitoring threshold setting of 1.6 volts.
(Default setting)
The VDSL bit is intended to select the supply voltage monitoring threshold settings.
2.2-2 VDET
Supply Voltage Monitoring Result Indication Bit
VDET
Description
0
Indicating supply voltage above the supply voltage monitoring threshold settings.
1
Indicating supply voltage below the supply voltage monitoring threshold settings.
(Default setting)
Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will hold the
setting of 1. The VDET bit accepts only the writing of 0, which restarts the supply voltage monitoring circuit.
Conversely, setting the VDET bit to 1 causes no event.
2.2-3 SCRATCH1
Scratch Bit 1
SCRATCH1
Description
0
(Default settings)
1
The SCRATCH1 bit is intended for scratching and accepts the reading and writing of 0 and 1. The SCRATCH1 bit
will be set to 0 when the XSTP bit is set to 1 in the control register 2.
14
RV5C386A
2.2-4 XSTP
Oscillation Halt Sensing Bit
XSTP
Description
0
Sensing a normal condition of oscillation
1
Sensing a halt of oscillation
(Default setting)
The XSTP bit is for sensing a halt in the oscillation of the crystal oscillator.
· The XSTP bit will be set to 1 once a halt in the oscillation of the crystal oscillator is caused by such events as
power-on from 0 volts and a drop in supply voltage. The XSTP bit will hold the setting of 1 even after the restart of
oscillation. As such, the XSTP bit can be applied to judge the validity of clock and calendar data after power-on or
a drop in supply voltage.
· When the XSTP bit is set to 1, all bits will be reset to 0 in the oscillation adjustment register, control register 1,
and control register 2, stopping the output from the INTRA and INTRB pins.
· The XSTP bit accepts only the writing of 0, which restarts the oscillation halt sensing circuit. Conversely, setting
the XSTP bit to 1 causes no event.
2.2-5 SCRATCH2
Scratch Bit 2
SCRATCH2
Description
0
(Default setting)
1
The SCRATCH2 bit is intended for scratching and accepts the reading and writing of 0 and 1. The SCRATCH2 bit
will be set to 0 when the XSTP bit is set to 1 in the control register 2.
15
RV5C386A
2.2-6 CTFG
Periodic Interrupt Flag Bit
CTFG
Description
0
Periodic interrupt output “H” (OFF)
1
Periodic interrupt output “L” (ON)
(Default setting)
The CTFG bit is set to 1 when the periodic interrupt signals are output from the INTRA pin (“L”). The CTFG bit
accepts only the writing of 0 in the level mode, which disables (“H”) the INTRA pin until it is enabled (“L”) again in
the next interrupt cycle. Conversely, setting the CTFG bit to 1 causes no event.
2.2-7 WAFG and DAFG
Alarm_W Flag Bit and Alarm_D Flag Bit
WAFG, DAFG
Description
0
Indicating a mismatch between current time and preset alarm time
1
Indicating a match between current time and preset alarm time
(Default setting)
The WAFG and DAFG bits are valid only when the WALE and DALE bits have the setting of 1, which is caused
approximately 61µs after any match between current time and preset alarm time specified by the Alarm_W registers
and the Alarm_D registers. The WAFG and DAFG bits accept only the writing of 0, which disables (“H”) the INTRA
or INTRB pin until it is enabled (“L”) again at the next preset alarm time. Conversely, setting the WAFG and DAFG
bits to 1 causes no event. The WAFG and DAFG bits will have the reading of 0 when the alarm interrupt circuit is
disabled with the WALE and DALE bits set to 0. The settings of the WAFG and DAFG bits are synchronized with
the output of the INTRA and INTRB pins as shown in the timing chart below.
Output Relationships Between the WAFG or DAFG Bit and INTRA or INTRB
Approx.61µs
Approx.61µs
Settings of WAFG (DAFG) bit
Output of INTRB (INTRA) pin
Writing of 0 to WAFG
(DAFG) bit
Writing of 0 to WAFG
(DAFG) bit
(Match between current time (Match between current time (Match between current time
and preset alarm time)
and preset alarm time)
and preset alarm time)
16
RV5C386A
2.3 Time Counters (at Addresses 0h to 2h)
· Time digit display (BCD format) as follows:
The second digits range from 00 to 59 and are carried to the minute digit in transition from 59 to 00.
The minute digits range from 00 to 59 and are carried to the hour digits in transition from 59 to 00.
The hour digits range as shown in “2.1-2 12/24: 12-/ 24-hour Mode Selection Bit” and are carried to the
day-of-month and day-of-week digits in transition from PM11 to AM12 or from 23 to 00.
· Any writing to the second counter resets divider units of less than 1 second.
· Any carry from lower digits with the writing of non-existent time may cause the time counters to malfunction.
Therefore, such incorrect writing should be replaced with the writing of existent time data.
2.3-1 Second Counter (at Address 0h)
D7
D6
D5
D4
D3
D2
D1
D0
—
S40
S20
S10
S8
S4
S2
S1
(For writing)
0
S40
S20
S10
S8
S4
S2
S1
(For reading)
0
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Default settings*
2.3-2 Minute Counter (at Address 1h)
D7
D6
D5
D4
D3
D2
D1
D0
—
M40
M20
M10
M8
M4
M2
M1
(For writing)
0
M40
M20
M10
M8
M4
M2
M1
(For reading)
0
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Default settings*
2.3-3 Hour Counter (at Address 2h)
*)
D7
D6
D5
D4
D3
D2
D1
D0
—
—
P/A or H20
H10
H8
H4
H2
H1
(For writing)
0
0
P/A or H20
H10
H8
H4
H2
H1
(For reading)
0
0
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Default settings*
Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop.
17
RV5C386A
2.4 Day-of-week Counter (at Address 3h)
*)
D7
D6
D5
D4
D3
D2
D1
D0
—
—
—
—
—
W4
W2
W1
(For writing)
0
0
0
0
0
W4
W2
W1
(For reading)
0
0
0
0
0
Indefinite
Indefinite
Indefinite
Default settings*
Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop.
· The day-of-week counter is incremented by 1 when the day-of-week digits are carried to the day-of-month digits.
· Day-of-week display (incremented in septimal notation):
(W4, W2, W1) = (0, 0, 0) → (0, 0, 1) → ... → (1, 1, 0) → (0, 0, 0)
· Correspondences between days of the week and the day-of-week digits are user-definable (e.g. Sunday = 0, 0, 0)
· The writing of (1, 1, 1) to (W4, W2, W1) is prohibited except when days of the week are unused.
2.5 Calendar Counters (at Addresses 4h to 6h)
· The calendar counters are configured to display the calendar digits in BCD format by using the automatic
calendar function as follows:
The day-of-month digits (D20 to D1) range from 1 to 31 for January, March, May, July, August, October, and
December; from 1 to 30 for April, June, September, and November; from 1 to 29 for February in leap years;
from 1 to 28 for February in ordinary years.
The day-of-month digits are carried to the month digits in reversion from the last day of the month to 1. The
month digits (MO10 to MO1) range from 1 to 12 and are carried to the year digits in reversion from 12 to 1.
The year digits (Y80 to Y1) range from 00 to 99 (00, 04, 08, ... , 92, and 96 in leap years) and are carried to the
19/20 digits in reversion from 99 to 00.
The 19/20 digits cycle between 0 and 1 in reversion from 99 to 00 in the year digits.
· Any carry from lower digits with the writing of non-existent calendar data may cause the calendar counters to
malfunction. Therefore, such incorrect writing should be replaced with the writing of existent calendar data.
2.5-1 Day-of-month Counter (at Address 4h)
D7
D6
D5
D4
D3
D2
D1
D0
—
—
D20
D10
D8
D4
D2
D1
(For writing)
0
0
D20
D10
D8
D4
D2
D1
(For reading)
0
0
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Default settings*
2.5-2 Month Counter + Century Bit (at Address 5h)
18
D7
D6
D5
D4
D3
D2
D1
D0
19/20
—
—
MO10
MO8
MO4
MO2
MO1
(For writing)
19/20
0
0
MO10
MO8
MO4
MO2
MO1
(For reading)
Indefinite
0
0
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Default settings*
RV5C386A
2.5-3 Year Counter (at Address 6h)
D7
D6
D5
D4
D3
D2
D1
D0
Y80
Y40
Y20
Y10
Y8
Y4
Y2
Y1
(For writing)
Y80
Y40
Y20
Y10
Y8
Y4
Y2
Y1
(For reading)
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
*)
Default settings*
Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop.
2.6 Oscillation Adjustment Register (at Address 7h)
*)
D7
D6
D5
D4
D3
D2
D1
D0
—
F6
F5
F4
F3
F2
F1
F0
(For writing)
0
F6
F5
F4
F3
F2
F1
F0
(For reading)
0
0
0
0
0
0
0
0
Default settings*
Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop.
2.6-1 F6 to F0
The oscillation adjustment circuit is configured to change time counts of 1 second on the basis of the settings of the
oscillation adjustment register when the second digits read 00, 20, or 40 seconds. Normally, the second counter is
incremented once per 32768 32.768-kHz clock pulses generated by the crystal oscillator. Writing to the F6 to F0 bits
activates the oscillation adjustment circuit.
· The oscillation adjustment circuit will not operate with the same timing (00, 20, or 40 seconds) as the timing of
writing to the oscillation adjustment register.
· The F6 bit setting of 0 causes an increment of time counts by ((F5, F4, F3, F2, F1, F0) –1) × 2.
The F6 bit setting of 1 causes a decrement of time counts by (( F5, F4, F3, F2, F1, F0) +1) × 2.
The settings of “*, 0, 0, 0, 0, 0, *” ( “*” representing either “0” or “1” ) in the F6, F5, F4, F3, F2, F1, and F0 bits
cause neither an increment nor decrement of time counts.
Example:
When the second digits read 00, 20, or 40, the settings of “0, 0, 0, 0, 1, 1, 1” in the F6, F5, F4, F3, F2, F1, and F0 bits
cause an increment of the current time counts of 32768 by (7–1) × 2 to 32780 (a current time count loss). When the
second digits read 00, 20, or 40, the settings of “0, 0, 0, 0, 0, 0, 1” in the F6, F5, F4, F3, F2, F1, and F0 bits cause neither
an increment nor a decrement of the current time counts of 32768.
When the second digits read 00, 20, or 40, the settings of “1, 1, 1, 1, 1, 1, 0” in the F6, F5, F4, F3, F2, F1, and F0 bits
cause a decrement of the current time counts of 32768 by (–2) × 2 to 32764 (a current time count gain).
19
RV5C386A
An increase of two clock pulses once per 20 seconds causes a time count loss of approximately 3ppm (2 / (32768 ×
20=3.051ppm). Conversely, a decrease of two clock pulses once per 20 seconds causes a time count gain of 3ppm.
Consequently, deviations in time counts can be corrected with a precision of ±1.5ppm. Note that the oscillation
adjustment circuit is configured to correct deviations in time counts and not the oscillation frequency of the 32.768kHz clock pulses. For further details, see “USAGE, 2.4 Oscillation Adjustment Circuit”.
2.7 Alarm_W Registers (at Addresses 8h to Ah)
2.7-1 Alarm_W Minute Register (at Address 8h)
D7
D6
D5
D4
D3
D2
D1
D0
—
WM40
WM20
WM10
WM8
WM4
WM2
WM1
(For writing)
0
WM40
WM20
WM10
WM8
WM4
WM2
WM1
(For reading)
0
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Default settings*
2.7-2 Alarm_W Hour Register (at Address 9h)
D7
D6
D5
D4
D3
D2
D1
D0
—
—
WH20,WP/A
WH10
WH8
WH4
WH2
WH1
(For writing)
0
0
WH20,WP/A
WH10
WH8
WH4
WH2
WH1
(For reading)
0
0
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Default settings*
2.7-3 Alarm_W Day-of-week Register (at Address Ah)
D7
D6
D5
D4
D3
D2
D1
D0
—
WW6
WW5
WW4
WW3
WW2
WW1
WW0
(For writing)
0
WW6
WW5
WW4
WW3
WW2
WW1
WW0
(For reading)
0
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
*)
Default settings*
Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop.
· The D5 bit of the Alarm_W hour register represents WP/A when the 12-hour mode is selected (0 for a.m. and 1
for p.m.). and WH20 when the 24-hour mode is selected (tens in the hour digits).
· The Alarm_W registers should not have any non-existent alarm time settings. (Note that any mismatch between
current time and preset alarm time specified by the Alarm_W registers may disable the alarm circuit.)
· When the 12-hour mode is selected, the hour digits read 12 and 32 for 0 a.m. and 0 p.m., respectively (see “2.1-2
12/24: 12-/24-hour Mode Selection Bit”).
· WW0 to WW6 correspond to W4, W2, and W1 of the day-of-week counter with settings ranging from (0, 0, 0) to (1,
1, 0).
· WW0 to WW6 with respective settings of 0 disable the outputs of the Alarm_W registers.
20
RV5C386A
Example of Alarm Time Setting
Day-of-week
12-hour mode
Sun. Mon. Tue. Wed. Thu.
Preset alarm time
Fri.
Sat.
WW0 WW1 WW2 WW3 WW4 WW5 WW6
24-hour mode
10-hour 1-hour 10-min 1-min 10-hour 1-hour 10-min 1-min
00:00 a.m. on all days
1
1
1
1
1
1
1
1
2
0
0
0
0
0
0
01:30 a.m. on all days
1
1
1
1
1
1
1
0
1
3
0
0
1
3
0
11:59 a.m. on all days
1
1
1
1
1
1
1
1
1
5
9
1
1
5
9
0
1
1
1
1
1
0
3
2
0
0
1
2
0
0
1
0
0
0
0
0
0
2
1
3
0
1
3
3
0
0
1
0
1
0
1
0
3
1
5
9
2
3
5
9
00:00 p.m. on
Mondays to Fridays
01:30 p.m. on Sundays
11:59 p.m. on Mondays,
Wednesdays, and Fridays
Note that the correspondence between WW0 to WW6 and the days of the week shown in the above table is only an
example and not mandatory.
2.8 Alarm_D Registers (at Addresses Bh to Ch)
2.8-1 Alarm_D Minute Register (at Address Bh)
D7
D6
D5
D4
D3
D2
D1
D0
—
DM40
DM20
DM10
DM8
DM4
DM2
DM1
(For writing)
0
DM40
DM20
DM10
DM8
DM4
DM2
DM1
(For reading)
0
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Default settings*
2.8-2 Alarm_D Hour Register (at Address Ch)
D7
D6
D5
D4
D3
D2
D1
D0
—
—
DH20,DP/A
DH10
DH8
DH4
DH2
DH1
(For writing)
0
0
DH20,DP/A
DH10
DH8
DH4
DH2
DH1
(For reading)
0
0
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
*)
Default settings*
Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop.
· The D5 bit represents DP/A when the 12-hour mode is selected (0 for a.m. and 1 for p.m.). and DH20 when the 24hour mode is selected (tens in the hour digits).
· The Alarm_D registers should not have any non-existent alarm time settings. (Note that any mismatch between
current time and preset alarm time specified by the Alarm_D registers may disable the alarm circuit.)
· When the 12-hour mode is selected, the hour digits read 12 and 32 for 0 a.m. and 0 p.m., respectively (see “2.1-2
12/24: 12-/24-hour Mode Selection Bit”).
21
RV5C386A
USAGES
1. Interfacing with the CPU
The RV5C386A employs the I2C bus system to be connected to the CPU via 2-wires. Connection and transfer
system of I2C bus are described in the following sections.
Note
I2C bus is a trademark of PHILIPS ELECTRONICS N.V.
1.1 Connection of I2C bus
2-wires, SCL and SDA which are connected to I2C bus are used for transmit clock pulses and data respectively.
All ICs that are connected to these lines are designed that will be not be clamped when a voltage beyond supply
voltage is applied to input or output pins. Open drain pins are used for output. This construction allows
communication of signals between ICs with different supply voltages by adding a pull-up resistor to each signal line
as shown in the figure below. Each IC is designed not to affect SCL and SDA signal lines when power to each of
these is turned off separately.
VDD1
*1) For data interface, the following conditions must be met:
VDD4≥VDD1
VDD4≥VDD2
VDD4≥VDD3
*2) When the master is one, the micro controller is ready for
driving SCL to “H” and RP of SCL may not be required.
VDD2
VDD3
VDD4
RP
RP
SCL
SDA
Microcontroller
22
RV5C386A
Other
Peripheral
Device
RV5C386A
Cautions on Determining RP Resistance
(1) Voltage drop at RP due to sum of input current or output current at off conditions on each IC pin
connected to the I2C bus shall be adequately small.
(2) Rising time of each signal shall be kept short even when all capacity of the bus is driven.
(3) Current consumed in I2C bus is small compared to the consumption current permitted for the entire
system.
When all ICs connected to I2C bus are CMOS type, condition (1) may usually be ignored since input current
and off state output current is extremely small for the many CMOS type ICs.
Thus the maximum resistance of RP may be determined based on (2) while the minimum on (3) in most
cases.
In actual cases a resistor may be place between the bus and input/output pins of each IC to improve noise
margins in which case the RP minimum value may be determined by the resistance.
Consumption current in the bus to review (3) above may be expressed by the formula below:
Bus consumption current .=
(Sum of input current and off state output current of all devices in stand-by mode) × Bus stand-by duration
Bus stand-by duration + bus operation duration
.
+
Supply voltage × bus operation duration × 2
RP resistance × 2 × (bus stand-by duration + bus operation duration)
+
supply voltage × bus capacity × charging/discharging times per unit time
Operation of “× 2” in the second member denominator in the above formula is derived from assumption that
“L” duration of SDA and SCL pins are the half of bus operation duration. “× 2” in the numerator of the same
member is because there are two pins of SDA and SCL. The third member, (charging/discharging times per
unit time) means number of transition from “H” to “L” of the signal line.
Calculation example is shown below:
Pull-up resistor (RP)=10kΩ, Bus capacity=50pF (both for SCL and SDA), VDD=3V
In as system with sum of input current and off state output current of each pin=0.1µA, I2C bus is used for
10ms every second while the rest of 990ms is in the stand-by mode. In this mode number of transitions of the
SCL pin from “H” to “L” state is 100 while SDA 50, every second.
Bus consumption current .=
0.1µA × 990ms
990ms + 10ms
.
+
3V × 10ms × 2
10kΩ × 2 × (990ms + 10ms)
+
3V × 50pF × (100 + 50)
=
0.099µA + 3.0µA + 0.0225µA = 3.12µA
Generally, the second member of the above formula is larger enough than the first and the third members,
bus consumption current may be determined by the second member in many cases.
23
RV5C386A
1.2 Transmission System of I2C bus
1.2-1 Start and stop conditions
In I 2C bus, SDA must be kept at a certain state while SCL is at the “H” state as shown below during data
transmission.
SCL
SDA
tSU;DAT
tHDL;DAT or tHDH;DAT
The SCL and SDA pins are at the “H” level when no data transmission is made. Changing the SDA from “H” to “L”
when the SCL is “H” activates the start condition and access is started. Changing the SDA from “L” to “H” when the
SCL is “H” activates stop condition and accessing stopped. Generation of start and stop conditions are always made
by the master (see the figure below).
Start condition
Stop condition
SCL
SDA
tHD;STA
tSU;STO
1.2-2 Data transmission and its acknowledge
After start condition is entered, data is transmitted by 1byte (8bits). Any bytes of data may be serially transmitted.
The receiving side will send an acknowledge signal to the transmission side each time 8bit data is transmitted.
The acknowledge signal is sent immediately after falling to “L” of SCL8bit clock pulses of data transmission, by
releasing the SDA by the transmission side that has asserted the bus at that time and by turning the SDA to “L” by
the receiving side. When transmission of 1byte data next to preceding 1byte of data is received the receiving side
releases the SDA pin at falling edge of the SCL9bit of clock pulses or when the receiving side switches to the
transmission side it starts data transmission. When the master is the receiving side, it generates no acknowledge
signal after the last 1byte of data from the slave to tell the transmitter that data transmission has completed when
the slave side (transmission side) continues to release the SDA pin so that the master will be able to generate stop
condition.
SCL from the master
1
SDA from
the transmission side
2
8
9
SDA from
the receiving side
Start condition
24
Acknowledge signal
RV5C386A
1.2-3 Data transmission format in I2C bus
I2C bus generates no CE signals. In place of it each device has a 7bit slave address allocated. The first 1byte is
allocated to this 7bit of slave address and to the command (R/W) for which data transmission direction is
designated by the data transmission thereafter. 7bit address is sequentially transmitted from the MSB and 2 and
after bytes are read, when 8bit is “H” and write when “L”.
The slave address of the RV5C386A is specified at (0110010).
At the end of data transmission/receiving stop condition is generated to complete transmission. However, if start
condition is generated without generating stop condition, repeated start condition is met and transmission/receiving
data may be continued by setting the slave address again. Use this procedures when the transmission direction
needs to be changed during one transmission.
Data is written into
the slave from the master
When data is read from
the slave immediately
after 7bit addressing
from the master
S
Slave address
(0110010)
S
S
Slave address
A
Data
A
Data
A P
1 A
Data
A
Data
A P
Inform read has been completed by
not generating an acknowledge signal,
to the slave side.
R/W=1 (Read)
Slave address
(0110010)
Data
R/W=0 (Write)
(0110010)
When the transmission
direction is to be changed
during transmission.
0 A
0 A
A Sr
Data
(0110010)
R/W=0 (Write)
A
1
Slave address
R/W=1 (Read)
A P
Data
Inform read has been completed by
not generating an acknowledge signal, to the slave side.
Master to slave
S Start condition
Slave to master
P Stop condition
A
A
A Acknowledge signal
Sr Repeated start condition
25
RV5C386A
1.2-4 Data transmission write format in the RV5C386A
Although the I 2C bus standard defines a transmission format for the slave address allocated for each IC,
transmission method of address information in IC is not defined. The RV5C386A transmits data the internal address
pointer (4bit) and the transmission format register (4bit) at the 1byte next to one which transmitted a slave address
and a write command. For write operation only one transmission format is available and (0000) is set to the
transmission format register. The 3byte transmits data to the address specified by the internal address pointer
written to the 2byte. Internal address pointer settings are automatically incremented for 4byte and after. Note that
when the internal address pointer is Fh, it will change to 0h on transmitting the next byte.
Example of data writing (When writing to internal address Eh to Fh)
R/W=0 (Write)
S 0 1 1 0 0 1 0 0 A 1 1 1 0 0 0 0 0 A
Transmission of
slave address
(0110010)
Setting of
Eh to the
internal
address
pointer
Setting of
0h to the
transmission
format
register
Master to slave
S Start condition
A
26
A
A Acknowledge signal
Data
Writing of data to the
internal address Eh.
Slave to master
P Stop condition
A
Data
Writing of data to the
internal address Fh.
A P
RV5C386A
1.2-5 Data transmission read format of the RV5C386A
The RV5C386A allows the following three readout methods of data from an internal register.
1) The first method to reading data from the internal register is to specify an internal address by setting the internal
address pointer and the transmission format register described 1.2-4, generate the repeated start condition (see
section 1.2-3) to change the data transmission direction to perform reading. The internal address pointer is set to
Fh when the stop condition is met. Therefore, this method of reading allows no insertion of the stop condition
before the repeated start condition. Set 0h to the transmission format register.
Example 1 of data read (when data is read from 2h to 4h)
R/W=0 (Write)
Repeated start condition
R/W=1 (Read)
S 0 1 1 0 0 1 0 0 A 0 0 1 0 0 0 0 0 A Sr 0 1 1 0 0 1 0 1 A
Transmission of
slave address
(0110010)
Setting of
2h to the
internal
address
pointer
Data
A
Reading of data from
the internal address 2h.
Master to slave
S Start condition
A
A
Transmission of
slave address
(0110010)
Setting of
0h to the
transmission
format
register
Data
A
Reading of data from
the internal address 3h.
Data
A P
Reading of data from
the internal address 4h.
Slave to master
Sr Repeated start condition
P Stop condition
A Acknowledge signal
27
RV5C386A
2) The second method to reading data from the internal register is to start reading immediately after writing to the
internal address pointer and the transmission format register. Although this method is not based on the I2C bus
standard in a strict sense it still effective to shorten read time to ease load to the master. Set 4h to the
transmission format register when this method is used.
Example 2 of data read (when data is read from internal addresses Eh to 1h).
R/W=0 (Write)
S 0 1 1 0 0 1 0 0 A 1 1 1 0 0 1 0 0 A
Transmission of
slave address
(0110010)
Setting of
Eh to the
internal
address
pointer
Data
A
Reading of data from
the internal address Fh.
Master to slave
S Start condition
A
28
A
A Acknowledge signal
Setting of
4h to the
transmission
format
register
A
Data
Reading of data from
the internal address Eh
Data
A
Reading of data from
the internal address 0h.
Slave to master
P Stop condition
Data
Reading of data from
the internal address 1h.
A P
RV5C386A
3) The third method to reading data from the internal register is to start reading immediately after writing to the
slave address and the R/W bit. Since the internal address pointer is set to Fh by default as described in 1), this
method is only effective when reading is started from the internal address Fh.
Example 3 of data read (when data is read from internal addresses Fh to 3h).
R/W=1 (Read)
S 0 1 1 0 0 1 0 1 A
Transmission of
slave address
(0110010)
Reading of data from
the internal address Fh.
Data
A
Reading of data from
the internal address 1h.
Master to slave
S Start condition
A
A
A
Data
A
Data
Reading of data from
the internal address 0h.
Data
A
Reading of data from
the internal address 2h.
Data
A P
Reading of data from
the internal address 3h.
Slave to master
P Stop condition
A Acknowledge signal
29
RV5C386A
1.2-6 Data transmission under special condition
The RV5C386A holds the clock tentatively for duration from start condition to stop condition to avoid invalid read or
write clock on carrying clock. When clock is carried during this period, which will be adjusted within approx. 61µs
from stop condition. To prevent invalid read or write clock shall be made during one transmission operation (from
start condition to stop condition). When 0.5 to 1.0 second elapses after start condition any access to the RV5C386A
is automatically released to release tentative hold of the clock, set Fh to the address pointer, and access from the
CPU is forced to be terminated (the same action as made stop condition is received: automatic resume function from
the I2C bus interface). Therefore, one access must be completed within 0.5 seconds. The automatic resume
function prevents delay in clock even if the SCL is stopped from sudden failure of the system during clock read
operation.
Also a second start condition after the first condition and before the stop condition is regarded as the “repeated start
condition.” Therefore, when 0.5 to 1.0 seconds passed after the first start condition, access to the RV5C386A is
automatically released.
If access is tried after automatic resume function is activated, no acknowledge signal will be output for writing while
FFh will be output for reading.
Access to the Real-time Clock
1) No stop condition shall be generated until clock read/write is started and completed.
2) One cycle read/write operation shall be completed within 0.5 seconds.
3) Do not make Start Condition within 61µs from Stop Condition. When clock is carried during the access,
which will be adjusted within approx. 61µs from Stop Condition.
The user shall always be able to access the real-time clock as long as these three conditions are met.
Bad example of reading from seconds to hours (invalid read)
(Start condition) → (Read of seconds) → (Read of minutes) → (Stop condition) → (Start condition) → (Read
of hour) → (Stop condition)
Assuming read was started at 05:59:59 P.M. and while reading seconds and minutes the time advanced to
06:00:00 P.M. At this time second digit is hold so the read as 05:59:59. Then the RV5C386A confirms (Stop
condition) and carries second digit being hold and the time changes to 06:00:00 P.M. Then, when the hour
digit is read, it changes to 6. The wrong results of 06:59:59 will be read.
30
RV5C386A
2. Configuration of Oscillation Circuit and Correction of Time Count Deviations
2.1 Configuration of Oscillating Circuit
Typical externally-equipped element
RV5C386A
VDD
9
(R1=30kΩ TYP.)
(CL=6pF to 8pF)
OSCIN
CG
RF
X'tal: 32.768kHz
VDD
10
32kHz
Standard values of internal elements
RF=15MΩ TYP.
8
RD
CD
RD=120kΩ TYP.
OSCOUT
CG, CD=12pF TYP.
A
The oscillation circuit is driven at a constant voltage of approximately 1.2 volts relative to the level of the VSS pin
input. As such, it is configured to generate an oscillating waveform with a peak-to-peak voltage on the order of 1.2
volts on the positive side of the VSS pin input.
Considerations in Handling Crystal Oscillators
Generally, crystal oscillators have basic characteristics including an equivalent series resistance (R 1)
indicating the ease of their oscillation and a load capacitance (CL) indicating the degree of their center
frequency. Particularly, crystal oscillators intended for use with the RV5C386A are recommended to have a
typical R1 value of 30kΩ and a typical CL value of 6 to 8pF. To confirm these recommended values, contact
the manufacturers of crystal oscillators intended for use with these particular models.
Considerations in Installing Components around the Oscillation Circuit
1) Install the crystal oscillator in the closest possible vicinity to the real-time clock ICs.
2) Avoid laying any signal lines or power lines in the vicinity of the oscillation circuit (particularly in the area
marked “←A→” in the above figure).
3) Apply the highest possible insulation resistance between the OSCIN and OSCOUT pins and the printed
circuit board.
4) Avoid using any long parallel lines to wire the OSCIN and OSCOUT pins.
5) Take extreme care not to cause condensation, which leads to various problems such as oscillation halt.
Other Relevant Considerations
1) For external input of 32.768-kHz clock pulses to the OSCIN pin:
DC coupling: Prohibited due to an input level mismatch.
AC coupling: Permissible except that the oscillation halt sensing circuit does not guarantee perfect
operation because it may cause sensing errors due to such factors as noise.
2) To maintain stable characteristics of the crystal oscillator, avoid driving any other IC through 32.768-kHz
clock pulses output from the OSCOUT pin.
31
RV5C386A
2.2 Measurement of Oscillation Frequency
RV5C386A
VDD
OSCIN
OSCOUT
32.768kHz
CLKC
Frequency
counter
32KOUT
VSS
*1) The RV5C386A is configured to generate 32-kHz clock pulses for output from the 32KOUT pin.
*2) A frequency counter with 6 (more preferably 7) or more digits on the order of 1ppm is recommended for use in the measurement of the oscillation
frequency of the oscillation circuit.
*3) The CLKC pin should be connected to the VDD pin with a pull-up resistor.
2.3 Adjustment of Oscillation Frequency
The oscillation frequency of the oscillation circuit can be adjusted by varying procedures depending on the usage of
the RV5C386A in the system into which they are to be built and on the allowable degree of time count errors. The
flow chart below serves as a guide to selecting an optimum oscillation frequency adjustment procedure for the
relevant system.
Start
Use 32-kHz
clock circuit?
NO
Allowable time count precision is on order of oscillation
frequency variations of crystal oscillator *1 plus
frequency variations of real-time clock? *2 *3
YES
YES
YES
To Course (A)
NO
To Course (B)
Use 32-kHz clock circuit without regard
to its frequency precision?
To Course (C)
NO
Allowable time count precision is on order of oscillation
frequency variations of crystal oscillator *1 plus
frequency variations of real-time clock? *2 *3
YES
NO
To Course (D)
*1) Generally, crystal oscillators for commercial use are classified in terms of their center frequency depending on their load capacitance (CL) and further
divided into ranks on the order of ±10, ±20, and ±50ppm depending on the degree of their oscillation frequency variations.
2) Basically, the RV5C386A is configured to cause frequency variations on the order of ±5 to ±10ppm at normal temperature.
*
*3) Time count precision as referred to in the above flow chart is applicable to normal temperature and actually affected by the temperature characteristics
and other properties of crystal oscillators.
32
RV5C386A
Course (A)
When the time count precision of each real-time clock is not to be adjusted, the crystal oscillator intended for use
with that real-time clock may have any CL value requiring no presetting. The crystal oscillator may be subject to
frequency variations which are selectable within the allowable range of time count precision. Several crystal
oscillators and real-time clocks should be used to find the center frequency of the crystal oscillators by the method
described in “2.2 Measurement of Oscillation Frequency” and then calculate an appropriate oscillation adjustment
value by the method described in “2.4 Oscillation Adjustment Circuit” for writing this value to the RV5C386A.
Course (B)
When the time count precision of each real-time clock is to be adjusted within the oscillation frequency variations of
the crystal oscillator plus the frequency variations of the real-time clock ICs, it becomes necessary to correct
deviations in the time count of each real-time clock by the method described in “2.4 Oscillation Adjustment Circuit”.
Such oscillation adjustment provides crystal oscillators with a wider range of allowable settings of their oscillation
frequency variations and their CL values. The real-time clock IC and the crystal oscillator intended for use with that
real-time clock IC should be used to find the center frequency of the crystal oscillator by the method described in
“2.2 Measurement of Oscillation Frequency” and then confirm the center frequency thus found to fall within the
range adjustable by the oscillation adjustment circuit before adjusting the oscillation frequency of the oscillation
circuit. At normal temperature, the oscillation frequency of the oscillator circuit can be adjusted by up to
approximately ±1.5ppm.
Course (C)
Course (C) together with Course (D) requires adjusting the time count precision of each real-time clock as well as
the frequency of 32.768-kHz clock pulses output from the 32KOUT pin. Normally, the oscillation frequency of the
crystal oscillator intended for use with the real-time clocks should be adjusted by adjusting the oscillation stabilizing
capacitors CG and CD connected to both ends of the crystal oscillator. The RV5C386A, which incorporates the CG
and the CD, requires adjusting the oscillation frequency of the crystal oscillator through its CL value.
Generally, the relationship between the CL value and the CG and CD values can be represented by the following
equation:
CL =
CG × CD
+ CS
CG + CD
where “CS” represents the floating capacity of the printed circuit board
The crystal oscillator intended for use with the RV5C386A is recommended to have the CL value on the order of 6 to
8pF. Its oscillation frequency should be measured by the method described in “2.2 Measurement of Oscillation
Frequency”. Any crystal oscillator found to have an excessively high or low oscillation frequency (causing a time
count gain or loss, respectively) should be replaced with another one having a smaller and greater CL value,
respectively until another one having an optimum CL value is selected. In this case, the bit settings disabling the
oscillation adjustment circuit (see “2.4 Oscillation Adjustment Circuit”) should be written to the oscillation
adjustment register.
33
RV5C386A
Another advisable way to select a crystal oscillator having an optimum CL value is to contact the manufacturer of the
crystal oscillator intended for use with the RV5C386A.
Incidentally, the high oscillation frequency of the crystal oscillator can also be adjusted by adding an external
oscillation stabilization capacitor CGOUT as illustrated in the diagram below.
*1) The CGOUT should have a capacitance ranging from 0 to 15pF.
RV5C386A
VDD
VDD
10
9
CG
RF
32kHz
8
RD
OSCIN
CGOUT *1
OSCOUT
CD
Course (D)
It is necessary to select the crystal oscillator in the same manner as in Course (C) as well as correct errors in the
time count of each real-time clock in the same manner as in Course (B) by the method described in “2.4 Oscillation
Adjustment Circuit”.
2.4 Oscillation Adjustment Circuit
The oscillation adjustment circuit can be used to correct a time count gain or loss with high precision by varying the
number of 1-second clock pulses once per 20 seconds. When such oscillation adjustment is not to be made, the
oscillation adjustment circuit can be disabled by writing the settings of “*, 0, 0, 0, 0, 0, *” (“*” representing “0” or
“1”) to the F6, F5, F4, F3, F2, F1, and F0 bits in the oscillation adjustment circuit. Conversely, when such oscillation
adjustment is to be made, an appropriate oscillation adjustment value can be calculated by the equation below for
writing to the oscillation adjustment circuit.
2.4-1 When Oscillation Frequency *1 is Higher than Target Frequency *2 (There is a Time Count Gain)
Oscillation adjustment value*3 =
(Oscillation frequency – Target frequency + 0.1)
Oscillation frequency × 3.051 × 10–6
.= (Oscillation frequency – Target frequency) × 10 + 1
.
*1)
Frequency of clock pulses output from the 32KOUT pin at normal temperature in the manner described in “2.2
Measurement of Oscillation Frequency”.
2) Target frequency:
Desired frequency to be set. Generally, a 32.768-kHz crystal oscillator has such temperature characteristics as to have
*
the highest oscillation frequency at normal temperature. Consequently, the crystal oscillator is recommended to have
target frequency settings on the order of 32.768 to 32.76810kHz (+3.05ppm relative to 32.768kHz). Note that the target
frequency differs depending on the environment or location where the equipment incorporating the real-time clocks is
expected to be operated.
*3) Oscillation adjustment value: Value that is to be finally written to the F0 to F6 bits in the oscillation adjustment register and is represented in 7-bit coded
decimal notation.
34
Oscillation frequency:
RV5C386A
2.4-2 When Oscillation Frequency is Equal to Target Frequency (There is Neither a Time Count Gain
nor a Time Count Loss)
Writing the oscillation adjustment value setting of “0”, “+1”, “–64”, or “–63” to the oscillation adjustment register
disables the oscillation adjustment circuit.
2.4-3 When Oscillation Frequency is Lower than Target Frequency (There is a Time Count Loss)
Oscillation adjustment value*3 =
(Oscillation frequency – Target frequency)
Oscillation frequency × 3.051 × 10–6
.= (Oscillation frequency – Target frequency) × 10
.
Oscillation adjustment value calculations are exemplified below.
(1) For an oscillation frequency of 32768.85Hz and a target frequency of 32768.05Hz:
Oscillation adjustment value = (32768.85 – 32768.05 + 0.1) / (32768.85 × 3.051 × 10–6) .= (32768.85 – 32768.05) × 10 + 1
.
= 9.001 =. 9
.
In this instance, write the settings of “0, 0, 0, 1, 0, 0, 1” to the F6, F5, F4, F3, F2, F1, and F0 bits in the oscillation
adjustment register. Thus, an appropriate oscillation adjustment value in the presence of any time count gain
represents a distance from 01h.
(2) For an oscillation frequency of 32763.95Hz and a target frequency of 32768.05Hz:
Oscillation adjustment value = (32763.95 – 32768.05) / (32763.95 × 3.051 × 10–6) = (32763.95 – 32768.05) × 10
= –41.015 .= –41
.
To represent an oscillation adjustment value of –41 in 7-bit coded decimal notation, subtract 41(29h) from
128(80h) to obtain 57h. In this instance, write the settings of “1, 0, 1, 0, 1, 1, 1” in the F6, F5, F4, F3, F2, F1, and F0
bits in the oscillation adjustment register. Thus, an appropriate oscillation adjustment value in the presence of
any time count loss represents a distance from 80h.
Oscillation adjustment involves an adjustment differential of approximately ±1.5ppm from the target frequency
at normal temperature.
Notes
1) Oscillation adjustment does not affect the frequency of 32.768-kHz clock pulses output from the 32KOUT
pin.
2) Oscillation adjustment value range: When the oscillation frequency is higher than the target frequency
(causing a time count gain), an appropriate time count gain ranges from –3.05ppm to –189.2ppm with the
settings of “0, 0, 0, 0, 0, 1, 0” to “0, 1, 1, 1, 1, 1, 1” written to the F6, F5, F4, F3, F2, F1, and F0 bits in the
oscillation adjustment register, thus allowing correction of a time count gain of up to +189.2ppm.
Conversely, when the oscillation frequency is lower than the target frequency (causing a time count loss),
an appropriate time count gain ranges from +3.05ppm to +189.2ppm with the settings of “1, 1, 1, 1, 1, 1, 1”
to “1, 0, 0, 0, 0, 1, 0” written to the F6, F5, F4, F3, F2, F1, and F0 bits in the oscillation adjustment register,
thus allowing correction of a time count loss of up to –189.2ppm.
35
RV5C386A
3. Oscillation Halt Sensing and Supply Voltage Monitoring
The oscillation halt sensing circuit is configured to record a halt in the oscillation of 32.768-kHz clock pulses. The
supply voltage monitoring circuit is configured to record a drop in supply voltage below a threshold voltage of 2.1 or
1.6 volts. For these functions, the real-time clock has two flag bits (ie. the XSTP bit for the former and the VDET bit
for the latter) in which 1 is set once and this setting is maintained until 0 is written.
When the XSTP bit is set to 1 for the oscillation halt sensing circuit, the VDET bit is reset to 0 for the supply voltage
monitoring circuit. The relationship between the XSTP and VDET bits is shown in the table below.
XSTP
VDET
Conditions of supply voltage and oscillation
0
0
No drop in supply voltage below threshold voltage and no halt in oscillation
0
1
Drop in supply voltage below threshold voltage and no halt in oscillation
1
*
Halt on oscillation
Threshold voltage (2.1 or 1.6 volts)
Supply voltage
Oscillation by 32.768-kHz clock pulses
Normal voltage detector
Supply voltage monitoring (VDET)
Oscillation halt sensing (XSTP)
Internal initialization
period
(1 to 2 seconds)
Setting XSTP and
VDET bits to 0
Setting VDET bit to 0
Setting XSTP and
VDET bits to 0
When the XSTP bit is set to 1 in the control register 2, the F6 to F0, WALE, DALE, SCRATCH3, 12/24, TEST, CT2,
CT1, CT0, VDSL, VDET, SCRATCH1, SCRATCH2, CTFG, WAFG, and DAFG bits are reset to 0 in the oscillation
adjustment register, the control register 1, and the control register 2. The XSTP bit is also set to 1 at power-on from 0
volts. Note that the XSTP bit may be locked to 0 and the internal register broken upon instantaneous power-down.
36
RV5C386A
Considerations in Using Oscillation Halt Sensing Circuit
Be sure to prevent the oscillation halt sensing circuit from malfunctioning by preventing the following:
1) Instantaneous power-down on the VDD
2) Condensation on the crystal oscillator
3) On-board noise to the crystal oscillator
4) Applying to individual pins voltage exceeding their respective maximum ratings
In particular, note that the XSTP bit may fail to be set to 1 in the presence of any applied supply voltage as
illustrated below in such events as backup battery installation. Further, give special considerations to prevent
excessive chattering to pewer supply.
VDD
< Supply Voltage Sensing Circuit >
The supply voltage monitoring circuit is configured to conduct a sampling operation during an interval of 7.8ms per
second to check for a drop in supply voltage below a threshold voltage of 2.1 or 1.6 volts for the VDSL bit setting of
0 (the default setting) or 1, respectively, in the control register 2, thus minimizing supply current requirements as
illustrated in the timing chart below. This circuit suspends a sampling operation once the VDET bit is set to 1 in the
control register 2
VDD
Threshold voltage
of 2.1 or 1.6 volts
7.8ms
XSTP
Internal initialization period
(1 or 2 seconds)
1s
Sampling operation by supply voltage
monitoring circuit
VDET
(D6 at address Fh)
Setting 0 to XSTP
and VDET bits
Setting VDET bit to 0
37
RV5C386A
4. Alarm and Periodic Interrupt
The RV5C386A incorporates the alarm circuit and the periodic interrupt circuit that are configured to generate
alarm signals and periodic interrupt signals, respectively, for output from the INTRA or INTRB pin as described below.
1) Alarm Circuit
The alarm interrupt circuit is configured to generate alarm signals for output from the INTRA or INTRB, which is
driven low (enabled) upon the occurrence of a match between current time read by the time counters (the day-ofweek, hour, and minute counters) and alarm time preset by the alarm registers (the Alarm_W registers intended
for the day-of-week, hour, and minute digit settings and the Alarm_D registers intended for the hour and minute
digit settings). The Alarm_W is output from the INTRB pin, and the Alarm_D is output from INTRA pin.
2) Periodic Interrupt Circuit
The periodic interrupt circuit is configured to generate either clock pulses in the pulse mode or interrupt signals
in the level mode for output from the INTRA pin depending on the CT2, CT1, and CT0 bit settings in the control
register 1.
The above two types of interrupt signals are monitored by the flag bits (i.e. the WAFG, DAFG, and CTFG bits in the
control register 2) and enabled or disabled by the enable bits (i.e. the WALE, DALE, CT2, CT1, and CT0 bits in the
control register 1) as listed in the table below.
Flag Bits
Enable Bits
Output Pin
Alarm signals
(under control of Alarm_W registers)
WAFG bit
(D1 at address Fh)
WALE bit
(D7 at address Eh)
INTRB
Alarm signals
(under control of Alarm_D registers)
DALE bit
(D0 at address Fh)
DALE bit
(D6 at address Eh)
INTRA
Periodic interrupt signals
CTFG bit
CT2, CT1, and CT0 bits (D2 to D0 at address Eh)
(D2 of Internal Address Fh) (these bit settings of 0 disable the periodic interrupt circuit)
INTRA
· At power-on, when the WALE, DALE, CT2, CT1, and CT0 bits are set to 0 in the control register 1, the INTRA or
INTRB pin is driven high (disabled).
· When two or more types of interrupt signals are output simultaneously from the INTRA or INTRB pin, the output
from the INTRA or INTRB pin becomes an OR waveform of their negative logic.
Example: Combined Output of Interrupt Signals Under Control of Alarm_D and Periodic Interrupt.
Alarm_D
Periodic Interrupt
INTRA
In this event, which type of interrupt signal is output from the INTRA pin can be confirmed by reading
the DAFG and CTFG bit settings in the control register 2.
38
RV5C386A
4.1 Alarm Interrupt
The alarm circuit is controlled by the enable bits (i.e. the WALE and DALE bits in the control register 1) and the
flag bits (i.e. the WAFG and DAFG bits in the control register 2). The enable bits can be used to enable this circuit
when set to 1 and to disable it when set to 0. When intended for reading, the flag bits can be used to monitor alarm
interrupt signals. When intended for writing, the flag bits will cause no event when set to 1 and will drive high
(disable) the alarm circuit when set to 0.
The enable bits will not be affected even when the flag bits are set to 0. In this event, therefore, the alarm circuit will
continue to function until it is driven low (enabled) upon the next occurrence of a match between current time and
preset alarm time.
The alarm function can be set by presetting desired alarm time in the alarm registers (the Alarm_W registers for the
day-of-week digit settings and both the Alarm_W registers and the Alarm_D registers for the hour and minute digit
settings) with the WALE and DALE bits once set to 0 and then to 1 in the control register 1. Note that the WALE
and DALE bits should be once set to 0 in order to disable the alarm circuit upon the coincidental occurrence of a
match between current time and preset alarm time in the process of setting the alarm function.
Interval (1 minute) during which
a match between current time
and preset alarm time occurs
MAX.61.1µs
INTRA or INTRB pin
Setting WALE Match between
current time and
and DALE
preset alarm time
bit to 1
Setting WALE Setting WALE
and DALE
and DALE
bit to 0
bit to 1
in the day-of-week
and hour settings
Setting WALE Match between
current time and
and DALE
preset alarm time
bit to 0
in the day-of- week
and hour settings
INTRA or INTRB pin
Setting WALE Match between
current time and
and DALE
preset alarm time
bit to 1
in the day-of-week
and hour settings
Setting WAFG
and DAFG
bit to 0
Match between
current time and
preset alarm time
in the day-of- week
and hour settings
39
RV5C386A
4.2 Periodic Interrupt
Setting of the periodic selection bits (CT2 to CT0) enables periodic interrupt to the CPU. There are two waveform
modes: pulse mode and level mode. In the pulse mode, the output has a waveform duty cycle of around 50%. In the
level mode, the output is cyclically driven low and, when the CTFG bit is set to 0, the output is set to high (OFF).
Waveform Mode, Cycle and Falling Timing
Description
CT2
CT1
CT0
Waveform Mode
Interrupt Cycle and Fall Timing
0
0
0
—
Off (“H”)
0
0
1
—
Fixed at low (“L”)
0
1
0
Pulse Mode*1 2Hz (Duty cycle of 50%)
0
1
1
Pulse Mode*1 1Hz (Duty cycle of 50%)
1
0
0
Level Mode*2 Once per 1 second (Synchronized with second counter increment)
1
0
1
Level Mode*2 Once per minute (at 00 seconds of every minute)
1
1
0
Level Mode*2 Once per hour (at 00 minutes and 00 seconds of every hour)
1
1
1
Level Mode*2 Once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month)
(Default setting)
1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second counter
as illustrated in the timing chart on the next page.
2) Level Mode: periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1
hour, and 1 month. The increment of the second counter is synchronized with the falling edge of
periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of
1 second are output in synchronization with the increment of the second counter as illustrated in
the timing chart on the next page.
3) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20 seconds as follows:
Pulse Mode: the “L” period of output pulses will increment or decrement by a maximum of ± 3.784ms.
For example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%
Level Mode: a periodic interrupt cycle of 1 second will increment or decrement by a maximum of ±3.784ms.
40
RV5C386A
Relation Between the Mode Waveform and the CTFG Bit
• Pulse Mode
CTFG bit
INTRA pin
Approx. 92µs
(Increment of second counter)
*)
Rewriting of the second counter
In the pulse mode, the increment of the second counter is delayed by approximately 92 µs from the falling edge of clock pulses. Consequently, time
readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second.
Rewriting the second counter will reset the other time counters of less than 1 second, driving the INTRA pin low.
• Level Mode
CTFG bit
INTRA pin
Setting CTFG bit to 0
(Increment of
second counter)
(Increment of
second counter)
Setting CTFG bit to 0
(Increment of
second counter)
5. 32-kHz Clock Output
For the RV5C386A, 32.768kHz clock pulses are output from the 32KOUT pin when the CLKC pin is set to high.
If CLKC is set to “L” or open, the 32KOUT pin is driven low, as illustrated in the timing chart below.
CLKC pin
32KOUT pin
MAX. 76.3µs
41
RV5C386A
6. Typical Applications
6.1 Typical Power Circuit Configurations
Sample circuit configuration 1
RV5C386A
*1) Install bypass capacitors for high-frequency and lowfrequency applications in parallel in close vicinity to the
RV5C386A .
OSCIN
System power supply
OSCOUT
32.768kHz
VDD
*1
VSS
Sample circuit configuration 2
RV5C386A
*1) When using an OR diode as a power supply for the
OSCIN
System power supply
OSCOUT
32.768kHz
VDD
*1
VSS
42
RV5C386A , ensure that voltage exceeding the absolute
maximum rating of V DD + 0.3 volts is not applied the
32KOUT pin.
RV5C386A
6.2 Connection of INTRA or INTRB Pin
The INTRA or INTRB pin follows the N-channel open drain output logic and contains no protective diode on the
power supply side. As such, it can be connected to a pull-up resistor of up to 5.5 volts regardless of supply voltage.
System power supply
RV5C386A
*1) Depending on whether the INTRA or INTRB pin is to be used
A
INTRA or INTRB
B
*
during battery backup, it should be connected to a pull-up
resistor at the following different positions:
1) Position A in the left diagram when it is not to be used during
battery backup.
2) Position B in the left diagram when it is to be used during
battery backup.
1
OSCIN
Backup power supply
32.768kHz
OSCOUT
VDD
VSS
6.3 Connection of 32KOUT Pin
As the 32KOUT pin is CMOS output, the power supply voltage of the RV5C386A and any devices to be connected to
the 32KOUT should be same. When the devices is powered down, the 32KOUT output should be disabled. When
the CLKC pin is connected to the system power supply through the pull-up resistor, the pull-up resistor should be
0Ω to 10kΩ, and the 32KOUT pin should be connect to the host through the resistor (approx. 10kΩ).
I = 0.5 × (VDD or VCC) / Rp
System power supply
RV5C386A
RV5C386A
System power supply
0 to 10kΩ
Voltage detector IC 1
*
CLKC
CLKC
32KOUT
32KOUT
OSCIN
OSCIN
OSCOUT
*1)
Host
Backup power supply
Backup power supply
32.768kHz
Approx. 10kΩ
OSCOUT
VDD
VDD
VSS
VSS
32.768kHz
RN5VL××C by RICOH.
43
RV5C386A
7. Typical Characteristics
• Test Circuit
RV5C386A
X'tal : 32.768kHz
(R1=30kΩ TYP.)
VDD
(CL=6pF to 8pF)
OSCIN
32.768kHz
Topt : 25˚C
Output Pins: open
OSCOUT
Frequency
counter
32KOUT
VSS
7.1 Timekeeping Current vs. Supply Voltage
(with no 32-kHz clock output)
(Output=Open, Topt=25˚C)
0.8
0.6
0.4
0.2
0
1
2
3
4
5
2.5
2
1.5
1
0.5
0
6
Supply Voltage VDD(V)
2
3
4
5
6
7.4 Timekeeping Current vs. Operating Temperature
(with no 32-kHz clock output)
(Output=Open)
2
TimeKeeping Current IDD(µA)
CPU Access Current IDD(µA)
1
(Output=Open, Topt=25˚C)
20
15
10
VDD=5V
VDD=3V
5
0
100
200
300
400
SCL Clock Frequency (kHz)
44
0
Supply Voltage VDD(V)
7.3 CPU Access Current vs. SCLK Clock Frequency
0
(Output=Open, Topt=25˚C)
3
TimeKeeping Current IDD(µA)
TimeKeeping Current IDD(µA)
1
0
7.2 Timekeeping Current vs. Supply Voltage
(with 32-kHz clock output)
500
1.5
1
0.5
0
–60 –40 –20
0
20
40
60
80 100
Operating Temperature Topt(˚C)
RV5C386A
(VDD=3V, Topt=25˚C,
External CG=0pF as standard)
10
5
0
–5
–10
–15
–20
–25
–30
–35
–40
0
5
10
15
20
7.6 Oscillation Frequency Deviation vs. Supply Voltage
Oscillation Frequency Deviation(ppm)
Oscillation Frequency Deviation(ppm)
7.5 Oscillation Frequency Deviation vs. External CG
(Topt=25˚C, VDD=3V as standard)
5
4
3
2
1
0
–1
–2
–3
–4
–5
0
1
External CG(pF)
–20
–40
–60
–80
–100
–120
20
40
60
300
200
100
0
80 100
0
1
2
3
4
5
6
Supply Voltage VDD(V)
7.9 VOL vs. IOL
(SDA, INTRA, INTRB Pin)
7.10 Input Current to CLKC pin vs. Supply Voltage
(Topt=25˚C)
30
(Topt=25˚C)
1.0
25
0.8
20
15
VDD=5V
VDD=3V
10
ICLKC (µA)
IOL (mA)
6
400
Temperature Topt(˚C)
0.6
0.4
0.2
5
0
5
(Topt=25˚C)
500
Oscillation Start Time(ms)
Oscillation Frequency Deviation(ppm)
0
0
4
7.8 Oscillation Start Time vs. Supply Voltage
(Topt=25˚C, VDD=3V as standard)
–140
–60 –40 –20
3
Supply Voltage VDD(V)
7.7 Oscillation Frequency Deviation vs.
Operating Temperature
20
2
0
0.2
0.4
0.6
VOL (V)
0.8
1.0
0
0
1
2
3
4
5
6
Supply Voltage VDD(V)
45
RV5C386A
8. Typical Software-based Operations
8.1 Initialization at Power-on
Start
*1
Power-on
*2
XSTP=1?
YES
*4
Set Oscillation Adjustment Register
and Control Registers 1 and 2, etc.
NO
*3
VDET=0?
NO
YES
Warning of Backup Battery
Run-down
*1) After power-on from 0 volts, the start of oscillation and the process of internal initialization require a time span on the order of 1 to 2 seconds, so that
access should be done after the lapse of this time span or more.
2) The XSTP bit setting of 0 in the control register 1 indicates power-on from backup battery and not from 0 volt. The XSTP bit may fail to be set to 1 in the
*
presence of any excessive chattering in power supply in such events as installing backup battery. Should there be any possibility of this failure occurring,
it is recommended to initialize the RV5C386A regardless of the current XSTP bit setting. For further details, see “3. Oscillation Halt Sensing and Supply
Voltage Monitoring”.
3) This step is not required when the supply voltage monitoring circuit is not used.
*
4) This step involves ordinary initialization including the oscillation adjustment register and interrupt cycle settings.
*
8.2 Writing of Time and Calendar Data
*1) When writing to clock and calendar counters, do not insert stop condition
46
Start condition
*
Write to clock and
calendar counters
*2
Stop condition
*3
1
until all times from second to year have been written to prevent error in
writing time. (Detailed in “1.2-6 Data transmission under special
condition”.
2) Any writing to the second counter will reset divider units lower than the
*
second digits.
3) Take care so that process from start condition to stop condition will be
*
complete within 0.5sec. (Detailed in “1.2-6 Data transmission under
special condition”.
The RV5C386A may also be initialized not at power-on but in the process
of writing time and calendar data.
RV5C386A
8.3 Reading Time and Calendar Data
8.3-1 Ordinary Process of Reading Time and Calendar Data
*1) When reading from clock and calendar counters, do not insert stop
Start condition
*
condition until all times from second to year have been read to prevent
error in reading time. (Detailed in “1.2-6 Data transmission under special
condition”.
2) Take care so that process from start condition to stop condition will be
*
complete within 0.5sec. (Detailed in “1.2-6 Data transmission under
special condition”.
1
Read from clock and
calendar counters
Stop condition
*2
8.3-2 Basic Process of Reading Time and Calendar Data Synchronized with Periodic Interrupt
Set Periodic Interrupt
Cycle Selection Bits
*1) This step is intended to select the level mode as a waveform mode for the
*1
periodic interrupt function.
*2) This step must be completed within 0.5 second.
*3) This step is intended to set the CTFG bit to 0 in the Control Register 2 to
cancel an interrupt to the CPU.
Generate Interrupt in CPU
CTFG=1?
YES
NO
Read from Time Counter
and Calendar Counter
*2
Write “×,1,×,1,×,0,1,1”
to Control Register 2
*3
Other Interrupt
Processes
47
RV5C386A
8.3-3 Applied Process of Reading Time and Calendar Data Synchronized with Periodic Interrupt
Time data need not be read from all the time counters when used for such ordinary purposes as time count
indication. This applied process can be used to read time and calendar data with substantial reductions in the load
involved in such reading.
For Time Indication in “Day-of-month, Day-of-week, Hour,
Minute, and Second” Format:
Write “×,×,×,×,0,1,0,0”
to Control Register 1
Write “×,1,×,1,×,0,1,1”
to Control Register 2
*1
Generate Interrupt to CPU
NO
CTFG=1?
YES
Second Digit = 00?
*2
NO
YES
*3
Use Previous Minute,
Hour, Day-of-week,
and Day-of-month Data
Read Minute, Hour, Day-of-week,
and Day-of-month Counters
Write “×,1,×,1,×,0,1,1”
to Control Register 2
Other Interrupt
Processes
*4
*1) This step is intended to select the level mode as a waveform mode for the periodic interrupt function.
*2) This step must be completed within 0.5 sec.
*3) This step is intended to read time data from all the time counters only in the first session of reading time data after writing time data.
*4) This step is intended to set the CTFG bit to 0 in the control register 2 to cancel an interrupt to the CPU.
48
RV5C386A
8.4 Interrupt Process
8.4-1 Periodic Interrupt
Set Periodic Interrupt
Cycle Selection Bits
*1) This step is intended to select the level mode as a waveform mode for the
*1
periodic interrupt function.
2) This step is intended to set the CTFG bit to 0 in the control register 2 to
*
cancel an interrupt to the CPU.
Generate Interrupt to CPU
CTFG=1?
NO
YES
Periodic Interrupt Process
Write “×,1,×,1,×,0,1,1”
to Control Register 2
Other Interrupt
Processes
*2
8.4-2 Alarm Interrupt
WALE or DALE=0
*1) This step is intended to once disable the alarm interrupt circuit by setting
*1
the WALE and DALE bits to 0 in anticipation of the coincidental occurrence
of a match between current time and preset alarm time in the process of
setting the alarm interrupt function.
2) This step is intended to enable the alarm interrupt function after completion
*
of all alarm interrupt settings.
*3) This step is intended to once cancel the alarm interrupt function by writing
the settings of “×,1,×,1,×,1,0,1” and “×,1,×,1,×,1,1,0” to the Alarm_W
registers and the Alarm_D registers, respectively.
Set Alarm Minute, Hour,
and Day-of-week Registers
WALE or DALE=1
*2
Generate Interrupt to CPU
WAFG or DAFG=1?
NO
YES
Conduct Alarm Interrupt
Write “×,1,×,1,×,1,0,1”
to Control Register 2
Other Interrupt
Processes
*3
49