¡ Semiconductor MSM62X42B ¡ Semiconductor MSM62X42B REAL TIME CLOCK IC WITH BUILT-IN CRYSTAL DESCRIPTION The MSM62X42B is a bus-connection Microcomputer peripheral IC of a Real Time Clock with built-in crystal in the perpetual calendar which can be read and written from a second unit. The interface between this IC and a microcomputer uses 4 data buses, 4 address buses, 3 control buses and 2 chip selects and carries out setting up, amending and reading time. ALE input is available for 8048 system, 8051 system or 8085 system and is used for other microcomputers if this input is fixed at "H". The clock function provides seconds, minutes, hours, day of week, date, month, year, 12/24 hour selectable, automatic leap year in the Christian Era and 30-second compensation controlled by software. The periodical interrupt function (or periodical waveform output) and the STOP/START function of the clock are also provided. The device is a silicon gate CMOS and the current consumption is low. The built-in crystal oscillator is 32.768 kHz and battery backup operation is considered. FEATURES • 32.768kHz built-in crystal oscillator (2 ranks of ±10PPM and ±50PPM --DIP) (2 ranks of ±20PPM and ±50PPM --SOP) • Real time clock of second, minute, date, month, year and day of week • Interface corresponding to microcomputer bus • 30-second compensation controlled by software • Periodical interrupt function (or periodical waveform output) for alarm • STOP/START function for clock • 12/24 hour selectable • AEL input for 8048 system, 8051 system or 8085 system (when a microcomputer does not provide the ALE output, fix the AEL input at "H".) • Low current consumption for CMOS device • Low STANDBY voltage and small STANDBY current • 18-pin plastic DIP(DIP18-P-300) • 24-pin plastic SOP PIN CONFIGURATION MSM62X42BRS (TOP View) 18 Lead Plastic DIP STD.P 1 18 VDD MSM62X42BGS-1K (TOP View) 24 Lead Plastic SOP STD.P 1 24 VDD CS0 2 23 (VDD) (VDD) CS0 2 17 (VDD) NC 3 22 ALE 3 16 (VDD) ALE 4 21 NC A0 4 15 CS1 A0 5 20 CS1 A1 5 14 D0 NC 6 19 D0 A1 7 18 NC A2 6 13 D1 NC 8 17 NC A3 7 12 D2 A2 9 16 D1 11 15 8 D3 A3 10 RD D2 RD 11 14 D3 GND 12 13 WR GND 9 10 WR NC : NO CONNECTION (unused pins) Note: The actual type name indicates the abbreviated one, M62X42B. 41 MSM62X42B ¡ Semiconductor RANK M62X42B M62X42B xxxxS JAPAN xxxxA Lot no. Stability S or B S: ± 20PPM B: ± 50PPM Stability A or B A: ± 10PPM B: ± 50PPM Lot no. EXTERNAL DIMENSION (UNIT : mm) 16.3 MAX 1.27 0.35 0.2 13 8.0MAX 12.2MAX 1.0 24 0.3MAX 1 42 12 0 2.58 ~1 MAX 0 ¡ Semiconductor MSM62X42B FUNCTION BLOCK DIAGRAM X'tal & OSC COUNTER 32.768kHz 1Hz HOLD bit RESET STOP 30 sec ADJ BUSY 30 sec ADJ bit bit bit bit bit D3 D2 D1 G A T E 24/12 bit S1 S10 MI1 MI10 H1 H10 D1 D10 MO1 MO10 Y1 Y10 W D0 RD A3 A2 A1 A0 CS0 ALE VDD G TA E G A T E & L A T C H D E C O D E R 64Hz 1 sec carry 1 min carry 1 hour carry S1 ~ WR CF CD CE STD.P CF * S1 ~ W ~ Y10 are time counter register. * CD ~ CF are control register. CS1 43 MSM62X42B ¡ Semiconductor REGISTER TABLE Address Register Input A3 A2 A1 A0 Name Data D3 D2 D1 D0 Count value Description 0 0 0 0 0 S1 S8 S4 S2 S1 0 to 9 1-second digit register 1 0 0 0 1 S10 * SI40 S20 S10 0 to 5 10-second digit register 2 0 0 1 0 MI1 mi8 mi4 mi2 mi1 0 to 9 1-minute digit register 3 0 0 1 1 MI10 * mi40 mi20 mi10 0 to 5 10-minute digit register 4 0 1 0 0 Hi h8 h4 h2 h1 0 to 9 1-hour digit register 5 0 1 0 1 H10 * PM/ AM h20 h10 6 0 1 1 0 D1 d8 d4 d2 d1 0 to 9 1-day digit register 7 0 1 1 1 D10 * * d20 d10 0 to 3 10-day digit register 8 r 0 0 0 MO1 mo8 mo4 mo2 mo1 0 to 9 1-month digit register 9 1 0 0 1 MO10 * * * MO10 0 to 1 10-month digit register A 1 0 1 0 Y1 y8 y4 y2 y1 0 to 9 1-year digit register B 1 0 1 1 Y10 y80 y40 y20 y10 0 to 9 10-year digit register C 1 1 0 0 W * w4 w2 w1 0 to 6 Week register D 1 1 0 1 CD 30 sec. ADJ IRQ FLAG BUSY HOLD — r E 1 1 1 0 CE t1 t0 ITRPT MASK /STND — r F 1 1 1 1 CF TEST 24/12 STOP — r REST 0 to 2 PM/AM, or 0 to 1 10-hour digit register 0 = "L" level, 1 = "H" level REST = RESET PM/AM = 1/0 ITRPT/STND = INTERRUPT/STANDARD Notes: 44 1) The writing of bit * is at discretion, but it is handled as "0" in the internal. In addition, it is unconditionally held at "0" during a read. 2) The writings of "1" to IRQ FLAG bit, and "0" and "1" to BUSY bit are at discretion, but they are not carried out. The reading can be done. The writing of "0" to the IRQ FLAG bit is carried out. 3) The bits except bit * and the BUSY bit can fully be read and written. However, the writing to the IRQ FLAG is effective for "0" only. 4) PM/AM bit is 1 at PM and 0 at AM. ¡ Semiconductor MSM62X42B ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Conditions VDD Power supply voltage Ta = 25° Input voltage VI Output voltage Vo Rating Unit – 0.3 to 7 V -03 to VDD +0.3 V -03 to VDD +0.3 V °C Storage temperature TSTG — –55 to +85 Soldering conditions (lead) TSOL — Temp.:under 260°C Time :within 10 seconds Symbol Conditions Rating Unit Power supply voltage VDD — 4.5 to 5.5 V Time Recording Supply Voltage VCLK — 2.0 to 5.5 V Crystal Frequency f(XT) — 32.768 kHz Operating Temperature TOP — –40 to +85 °C Operating Conditions Parameter Note: Time Recording Supply Voltage: Power supply voltage to guarantee a crystal oscillator and time recording Frequency Accuracy Item Conditions Rank A Rating Unit ± 10 Ta = 25°C Frequency stability Rank S ± 20 PPM VDD = 5V Rank B ± 50 Temperature Characteristics –10 to +70°C (25°C standard) ) –40 to +85°C ( ´´ OCS starting time At 4.5V, let "t" make "0" Frequency Drift Voltage characteristics +10/ –120 +10/ –220 PPM MAX 1 Sec. Ta=25°C, VDD = 5V First year ±5 PPM/year Ta=25°C VDD = 4.5~5.5V ±5 PPM/V * Rank A : 18pin DIP only Rank S : 24pin SOP only Rank B : 18pin DIP, 24pin SOP 45 MSM62X42B ¡ Semiconductor D.C. Characteristics (VDD = 5V ± 10%, Ta = –40 to +85°C) Parameter "H" Input voltage (1) Symbol Conditions VIH1 Min. Typ. ax 2.2 — — Unit V "L" Input voltage (1) VIL1 — — 0.8 Input leak current (1) ILK1 — — 1/–1 V1 = VDD/0V µA — — 10/–10 IOL = 2.5mA — — 0.4 VOH IOH = 400µ A 2.4 — — "L" output voltage (2) VOL2 IOL = 2.5mA — — 0.4 V OFF leak current IOFFLK VI = VDD / 0V — — 10 µA Input capacitance (1) C11 — 5 — Input leak current (2) ILK2 "L" output voltage (1) VOL1 "H" output voltage Applicable Terminal All input terminals except CS1 Input terminals other than D0 ~D3 D0 ~ D3 V D0 ~ D3 STD. P Input capacitance (2) C12 Current consumption (1) IDD1 Current consumption (2) IDD2 "H" input voltage (2) V1H2 "L" input voltage (2) V1L2 46 Input frequency 1MHz f(xt) = 32.768 kHz CS1 ~~ 0V VDD = 5V VDD = 2V VDD=2~5.5V PF — 5 — — — 30 — — 1.8 4/5VDD — — — — 1/5VDD Input terminals other than D0 to D3 D0 ~D3 µA VDD V CS1 ¡ Semiconductor MSM62X42B Switching Characteristics WRITE mode (ALE = VDD) (VDD = 5V ± 10%, Ta = –40 to +85°C) Parameter Symbol Conditions Min. Max. CS1 Set up Time tC1S — 1000 — CS1 Hold Time tC1H — 1000 — Address Stable Before WRITE tAW — 20 — Address Stable After WRITE tWA — 10 — WRITE Pulse Width tWW — 120 — Data Set up Time tDS — 100 — Data Hold Time tDH — 10 — RD/WR Recovery Time tRCV — 60 — Unit ns CS1 VIH2 VIH2 t C1S A0~A3 CS0 t C1H VIH1 VIL1 VIH1 VIL1 t Aw WR t ww VIH1 VIL1 t wA VIL1 t DS D0~D3 (INPUT) VIH1 t DH t RCV VIH1 VIH1 VIH1 VIL1 VIL1 VIH1 = 2.2V VIL1 = 0.8V VIH2 = 4/5 VDD VIL2 = 1/5 VDD 47 MSM62X42B ¡ Semiconductor WRITE mode (with use of ALE) (VDD = 5V ± 10%, Ta = –40 to +80°C) Parameter Symbol Conditions Min. Max. CS1 Set up Time tC1S — 1000 — Address Set up Time tAS — 25 — Address Hold Time tAH — 25 — ALE Pulse Width tAW — 40 — ALE Before WRITE tALW — 10 — WRITE Pulse Width tWW — 120 — ALE After WRITE tWAL — 20 — Data Set up Time tDS — 100 — Data Hold Time tDH — 10 — CS1 Hold Time tC1H — 1000 — RD/WR Recovery Time tRCV — 60 — CS1 VIH2 t C1S t AS VIH1 VIL1 A0~A3 CS0 Unit ns VIH2 t C1H t AH VIH1 VIL1 t AW ALE VIH1 VIH1 VIL1 t ALW WR t WW t DS D0~D3 (Input) VIH1 VIL1 VIH1 = 2.2V VIL1 = 0.8V 48 t WAL VIH1 VIL1 VIH1 VIL1 t RCV t DH VIH1 VIL1 VIH2 = 4/5 VDD VIL2 = 1/5 VDD VIH1 ¡ Semiconductor MSM62X42B READ mode (ALE = VDD) (VDD = 5V ± 10%, Ta = –40 to +85°C) Parameter Symbol Conditions Min. Max. CS1 Set up Time tC1S — 1000 — CS1 Hold Time tC1H — 1000 — Address Stable Before READ tAR — 20 — Address Stable After READ tRA — 0 RD to Data tRD CL = 150 pF — 120 Data Hold tDR — 0 — RD/WR Recovery Time tRCV — 60 — CS1 VIH2 t C1S t C1H t AR A0~A3 CS0 Unit ns VIH2 t RA VIH1 VIL1 RD VIH1 D0~D3 (Output) VIH1 VIL1 t RD VIL1 VIH1 t DR VOH VOH VOL VOL VIH1 = 2.2V VIL1 = 0.8V t RCV VIH2 = 4/5 VDD VIL2 = 1/5 VDD "Z" VOH = 2.2V VOL = 0.8V 49 MSM62X42B ¡ Semiconductor READ mode (with use of ALE) (VDD = 5V ± 10%, Ta = –40 to +85°C) Parameter Symbol Conditions Min. Max. CS1 Set up Time tC1S — 1000 — Address Set up Time tAS — 25 — Address Hold Time tAH — 25 — ALE Pulse Width tAW — 40 — ALE Before READ tALR — 10 — ALE After READ tRAL — 10 — RD to Data tRD CL = 150pF – 120 DATA Hold tDR — 0 — CS1 Hold Time tC1H — 1000 — RD/WR Recovery Time tRCV — 60 — Unit ns CS1 VIH2 t C1S t AS t AH VIH1 VIL1 A0~A3 CS0 VIH2 t C1H VIH1 VIL1 t AW ALE VIH1 VIH1 VIL1 VIL1 t RAL t ALR RD VIH1 VIL1 t DR VIH1 = 2.2V VIL1 = 0.8V VIH2 = 4/5 VDD VIL2 = 1/5 VDD VIH1 t RCV VIL1 t DR VOH VOL D0~D3 (Output) 50 VIH1 VOH = 2.2V VOL = 0.8V "Z" ¡ Semiconductor MSM62X42B PIN DESCRIPTION D0 to D3 (Data buses 0 to 3) Data input/output pins to be directly connected to a microcomputer data bus for reading and writing of the register controlled by the microcomputer. The interface serves as positive logic and CS0=L, 1=H, RD=L, and as output mode when WR=H. It becomes high impedance except these cases. A0 to A3 (Address buses 0 to 3) These are input pins to be directly connected to a microcomputer address bus for register assignment which is read and written by a microcomputer. These address data are used in combination with ALE for addressing registers. ALE (Address Latch Enable) This is an input pin to read address data and CS0. The address bus andCS0 are read into a IC when ALE="H". The address data in the case of ALE=L in the IC is held. CS1 functions to ALE independently. When the microcomputer of MSC-48, 51 or 80 system having an ALE output is used, this pin is connected to the ALE output of the microcomputer. When 4 Bits of A0 to A3 in a 4 Bit microcomputer are commonly used with an another peripheral IC. When the microcomputer does not have the ALE output, the ALE input of this IC is fixed to "H". WR (WRITE) This is a input pin for which the data is written into this IC by a microcomputer. When CS1=H, D0 ~ D3 data are written into the designated registers by A0 to A3 and ALE at the rising edge of WR. RD (READ) This is an input pin to read this IC data by a microcomputer. When CS1=H, RD outputs the register data designated by A0 to A3 and ALE during "L". If both WR and RD are set at "L", this should be inhibited because it becomes the cause for malfunction. CS0, CS1(Chip Select 0•1) These pins enable/disable ALE, RD and WR operation, when CS1=H at CS0=L, these pins become effective. In other combination except this, the pins become equivalent to ALE=L and WR=RD=H unconditionally in the IC internal. However, CS0 needs operation related with ALE, while CS1 works independently to ALE. CS1 must be connected to the power supply voltage detector. Refer to the item, “CS1 of APPLICATION NOTE”. STD • P (STANDRD Pulse) Output pin of N-CH OPEN DRAIN type. The output data is controlled by the D1 data content of CE register. This pin has a priority to CS0 and CS1. Refer to the item "CE REGISTER FOR FUNCTIONAL DESCRIPTION OF REGISTERS". VDD N-CH STD.P Output 51 MSM62X42B ¡ Semiconductor (VDD) Both pins are shorted to VDD. They should be left open or connected to 18 pin (DIP) or 24 pin (SOP). VDD • VSS These are a positive power supply pin VDD and a ground pin VSS. FUNCTIONAL DESCRIPTION OF REGISTERS Register names: S1, S10, MI1, MI10, H1, H10, D1, D10, MO1, MO10, Y1 Y10, W a) These are abbreviations for Second1, Second10, MI nute1, MI nute10, Day1, Day10, Month1, Month10, Year1, Year10 and week. These values are in BCD notation. b) Refer to the Register table for details. All registers are logically positive. For example, (S8, S4, S2, S1) = 1001 which means 9 seconds. In addition, the * mark in the rgister table is good for either case of "1" or "0" in the case of writing and becomes “0” automatically in the case of reading. c) If data is written which is out of the clock register data limits, it can result in erroneous clock data being read back. Therefore, avoid to set not existing data. d) PM/AM h20, h10 In 12-hour mode, the time of AM12 ~ AM11 and PM12~ PM11 exists. In 24-hour mode, the time exists from 0 hour to 23 hour. In the mode setting of 24-hour mode, PM/AM bit is ignored, while in the mode setting of 12hour mode, h20 is to be set. Otherwise it causes discrepancy. In reading out the PM/AM bit in the 24-hour mode, it is continuously read out as 0. In reading out h20 bit in the 12-hour mode, 0 is written into this bit first, then it is continuously read out as 0 unless 1 is being written into this bit. e) Registers Y1, Y10 and Leap Year This IC is designed exclusively for the Christian Era and is capable of identifying a leap year automatically. 80, 84 88 ------- leap years When a non-existant day of the month less than 31 day is set, for example, if the data February 29, or November 31, 1983 was written, it would be changed automatically to March 1 or December 1, 1983 at the exact time at which a carry pulse occurs for the day's digit. 52 ¡ Semiconductor MSM62X42B f) Regarding W The Register W data limits are up-counted from 0 to 6. The following Table 1 shows a possible data definition. TABLE 1 W4 W2 W1 Day of Week 0 0 0 Sunday 0 0 1 Monday 0 1 0 Tuesday 0 1 1 Wednesday 1 0 0 Thursday 1 0 1 Friday 1 1 0 Saturday CD REGISTER (Control D Register) a) HOLD (D0) • This Register is one means used for reading out registers S1 to W (addresses 0 to C) and a bit used for writing. "1" bit to this bit is written and when BUSY bit shows "0", the clock more than 1 second digit stops and the reading and writing become possible (Refer to the item APPLICATION NOTE for reading which does not use HOLD bit). When BUSY was "1" and after reading have finished, "0" is written to HOLD bit. If the writing of "0" is omitted, then this results in the cause for erroneous data. Setting this bit to "1" inhibits a carry to 1 second counter in the IC internal, but a carry to a second counter caused during the duration of "1" is automatically compensated (+1 second) by only one time at the time when "0" is written to this bit. However, the carry after the second is disregarded and is not compensated (loss second). • If CS1 makes "L", the HOLD bit becomes equivalent to the writing to "0" and becomes "0". b) BUSY (D1) • The status bit in the IC internal which shows the interface condition with a microcomputer. When the registers S1 to W (addresses 0 to C) is written, when HOLD bit is always "1" and when BUSY bit is surely "0", in case the HOLD bit is used for reading, this is performed when the BUSY bit is "0". "0" of the BUSY bit continues while the HOLD bit is "1". When the HOLD bit makes "0", the BUSY bit becomes "1". • The operation for the registers CD, CE and CF is irrespectively performed for the HOLD bit and BUSY bit. • The BUSY bit is "1" uncondiotinally when the HOLD bit=0 and when "1" written into the HOLD bit, BUSY or not BUSY can be confirmed and when BUSY="1", "0" is once written into the HOLD bit, and then "1" is again written. BUSY is checked. The routine procedure like this [HOLD ¨ "0", HOLD ¨ "1", BUSY check] is repeated, or after "0" is written into the HOLD bit, "1" is again written into the HOLD bit after 190µs and BUSY=0 is confirmed. • The time when this IC is BUSY is 190µs per one second • The writing into the BUSY bit cannot be performed. 53 MSM62X42B ¡ Semiconductor c) IRQ FLAG (D2) (Interrupt Request FLAG) This status bit corresponds to "L" or "OPEN" of the STD.P output pin. When STD.P="L", then this bit=1 and when STD.P=OPEN, then this bit=0. This bit indicates that an interrupt has occurred to a microcomputer mainly. When D0 of register CE(MASK)=0, then the STD.P output changes from OPEN to "L" and this bit changes from "0" to "1" according to the timing set by D3(t1) and D2(t0) of the register CE. When D1(ITRPT/STND) of the register CE is 1 (interrupt mode), the "1" of this bit (the "L" of the STD.P output) remains until "0" is written into this bit. When this bit is "1" and timing for a new interrupt occurs, the new interrupt is ignored. When D1(ITRPT/STND)=0 (fixed cycle output waveform mode), the "1" of this bit (the "L" of the STD.P output) keeps "1" until either "0" is written to this bit, or this bit automatically returns after 7.8125ms. The using examples for the alarm are shown in the item "Set STD.P at alarm mode of APPLICATION NOTE". d) 30 sec. ADJ bit (30 sec. ADJUST) This is a bit for 30-second adjustment. When "1" is written into this bit, the compensation for 30 seconds is performed. The duration for 125µs from the time written into this bit should not be read from or written into registeres S1 ~ W (addresses 0 ~ C). This bit for 125µs from the time written into this bit is kept in "1" and then it will automatically return to "0". After "1" is written into this bit, the registeres S0 ~ W (addresses 0 ~ C) are operationed with confirmation of automatical return to "0" of this bit. CE REGISTER (Control E Register) a) MASK (D0) This bit controls the STD.P output. When this bit=1, then the STD.P output becomes open. When this bit=0, then the STD.P output=output mode. The relationship between the MASK bit and STD.P output is shown as follows. • In the case of interrupt mode (ITRPT/STND bit="1") • In the case of fixed cycle output waveform mode (ITRPT/STND bit="0") "1" MASK BIT "0" STD.P OUTPUT "0" "1" "INTERRUPT" DOES NOT OCCUR BECAUSE MASK BIT IS "1" OPEN LOW LEVEL "INTERRUPT" TIMING WRITE “0” INTO IRQ FLAG BIT IN TRT/STND BIT = "1" 54 ¡ Semiconductor MSM62X42B "1" MASK BIT "0" "0" "1" OUTPUT DOES NOT OCCUR AT LOW LEVEL BECAUSE MASK BIT IS "1" STD.P OUTPUT OPEN LOW LEVEL OUTPUT TIMING AUTOMATIC RETURN (When “0” is written to IRQ FLAG bit, at that time, STD.P output becomes open without awaiting automatic return.) IN TRT/STND BIT = "0" b) ITRPT/STND (D1) (INTERRUPT/STANDARD PULSE) This is a bit which gives the meaning for STD.P output. When this bit="1", the request for interrupt is outputted at the STD.P output and when this bit="0", a fixed cycle waveform with a low-level pulse width of 7.8125ms is present at the STD.P output. However, at this time, the MASK bit must equal 0, while the period in either modes is determined by t0 (D2) and t1(D3) of register CE. c) t0 (D2), t1 (D2) (time 0, 1) • When ITRPT/STND bit="1", this bit determines the interrupt period. When ITRPT/ STND bit="0", this bit determines the period of fixed timing waveform. The periods are shown in the table below. Duty CYCLE of "L" level when INRPT/STND bit is "0". t1 t0 Period 0 0 1/64 second 1/2 0 1 1 second 1/128 1 0 1 minute 1/7680 1 1 1 hour 1/460800 • The timing of the STD.P output designated by t1 and t2 occurs at the moment that a carry occurs to a clock digit. (EXAMPLE) WHEN t1 = 1, t0 = 1 and MASK = 0 PM12:00 PM1:00 WHEN ITRPT/STND BIT is "1" STD.P OUTPUT WHEN ITRPT/STND BIT is "0" OPEN LOW LEVEL OPEN LOW LEVEL The special counter is not included for t1 and t0. 55 MSM62X42B ¡ Semiconductor • The low-level pulse width of the fixed cycle waveform is 7.8125ms independent of t0/t1 inputs. • The fixed cycle output waveform mode is available for the confirmation of the crystal oscilltor frequency. • During ±30 second adjustment a carry can occur that will cause the STD.P output to go "L" when t0/t1=1,0 or 1,1. However, when ITRPT/STND bit=0, the "L" is kept from clearing under the second of 30-second ADJ to resuming a carry to 1/64-second digit. • No STD.P output change occurs as a result of writing data to registers S1 ~ H1. CF REGISTER (control F Register) a) REST (D0) (RESET) This bit is used to reset the clock's internal counter of less than a second. When RTEST=1, the counter is Reset for the duration of REST. In order to release this counter from Reset, a "0" must be written to the REST bit. If CS1=0, then REST=0 automatically. b) STOP (D1) (STOP) This bit is used for the integrating clock. When "1" is written, the timing after 8,192Hz stops and swhen "0" is written, the timing starts again. "1" STOP BIT "0" "1" "0" "1" "0" "0" TIMING OF "CARRY" TO 8192Hz "CARRY" EXECUTED "CARRY" NOT EXECUTED c) 24/12 (D2) (24 Hour/12 Hour) • This bit is for selection of 24/12 hour time modes, if D2=1, 24 hour mode is selected and the PM/AM bit is invalid. If D2=0,12 hour mode is selected and the PM/AM bit is valid. • The writing into the 24/12 hour bit is performed only when RESET bit=1. [24/12 hour bit=*1 and RESET bit="1"] must be written and then [24/12 hour bit=*2 and RESET bit="0"] must be written continuously. However, in the case of *1=*2 and *1≠*2, the 24/ 12 hour bit becomes indefinite. • When 24/12 hour bit is rewritten, the data of more than H1 may be destroyed. Therefore, the data of more than H1 must be newly rewritten. • When REST bit=0, the 24/12 hour bit cannot be written. d) TEST (D3) • This is a bit for the test. This bit is used in the state of TEST bit=0. • When TEST bit is "1", because of the test function based on our company's convenience, the user's function is not guaranteed. 56 ¡ Semiconductor MSM62X42B APPLICATION NOTE Power Supply Start Power On TEST bit REST bit 24/12 bit STOP bit ¨ 0 ¨ 1 ¨ *1 ¨ 1 VDD= 0 to VDD= 5V All registers and STD,P output=undefined *1=*2(=1 or 0) REST bit ¨ 0 24/12 bit ¨ *2 Set the current Time HOLD bit ¨ 0 STOP bit ¨ 0 Start Operation Pattern Layout The oscillation circuit of 32.768kHz consists of high impedance in the oscillation stage to realize the minimum current consumption. In addition, it is a feature that the time when the oscillation waveform passes the threshold vicinity is long. For this reason, the power supply anti-noise by the same method as an analog IC must be considered. As an actual example, set a tantalum capacitor (4.7µF) and a ceramic capacitor (0.01µF) near this IC. In case that an another IC, for instance, RAM for backup, exists in battery backup circuit, set a bypass capacitor close to it. Maximum value of allowable power supply noise should be 300mV. 57 MSM62X42B ¡ Semiconductor Reading and Writing of Registers S1 ~ W and Writing of 30-Second ADJ Bit Registers S1 ~ W (Addresses 0 ~ C) Reading and writing in the case of using HOLD bit HOLD bit ¨ 1 READ BUSY bit * BUSY bit = 0 ? YES Write data into or Read data from registers S1~W NO HOLD bit ¨ 0 Idling time HOLD bit ¨ 0 * In the inside of LSI, the CLEAR of BUSY bit is performed when HOLD bit = 0, but, if the period of HOLD bit =0 is extermely narrow as compared with the period of HOLD bit = 1, there is some case that the CLEAR of BUSY bit delays so that the BUSY bit can be cleared by sampling HOLD bit = 0 at approximate 16KHz. It is recommended to allow an idling time of 62ms or more. 58 ¡ Semiconductor MSM62X42B Reading method 1 in the case of not using HOLD bit Reading from Registers S1~W First Data of DATA1 ¨ Registers S1~ W Reading from Registers S1~W Second Data of DATA2 ¨ Registers S1~ W NO DATA1=DATA2 * The reason why the registers are read twice is to avoid the case during the variation of information because a carry has occurred accidentlly. YES END Reading method 2 in the case of not using HOLD bit t1 t0 ← ← *1 *2 ITRPT/STND ← MASK ← Initial setting only at power On • *1 and *2 represent the minimum required time unit. 1 0 For example t1=0 and t0=1 when required to a unit of second t1=1 and t0=0 when required to a unit of minute t1=1 and t0=1 when required to a unit of hour IRQ FLAG ← 0 t : 12 hour mode 35µs 24 hour mode 3µs WAIT t Note TIME DATA READ See Note below ~ Retried the reading since a carry occurred during the operation. REGISTER CD READ IRQ FLAG=0 YES Normal read NO (Note) Do this process within the following time requirements by combination between t1 and t0. t1=0, t0=1 t1=1, t0=0 t1=1, t0=1 within 1 second within 1 minute within 1 hour 59 MSM62X42B ¡ Semiconductor Reading mehtod 3 in the cass of not using HOLD bit t1 ¨ t0 ¨ *1 • Initial setting only in power On *2 • *1 and *2 represent the minimum required time unit. 1 ITRPT/STND ¨ MASK For example 0 ¨ t1 =0 and t0 =1 when required to a unit of second t1 =1 and t0 = 0 when required to a unit of minute t1 =1 and t0 =1 when required to a unit of hour CPU senses the interruption. REGISTER CD READ IRQ FLAG=1 NO The other IC causes the interruption. YES WAIT t The interruption is caused by this IC due to the occurrence of a carry TIME DATA READ t : 12 hour mode 35µs 24 hour mode 3µs IRQ FLAG ¨ 0 The IRQ FLAG is cleared to read the next time data. END Writing 30-Second ADJ bit (Two Ways A, B) START 30-SECOND ADJ BIT ¨ 1 READ 30-SECOND ADJ BIT 30-SECOND ADJ BIT=0? NO YES END (A) START 30-SECOND ADJ BIT ¨ 1 120µs PASS ? YES END (B) 60 NO • The reading from or writing into all bits of registers CD and CP can carry out without any relation to HOLD bit. ¡ Semiconductor MSM62X42B CS1 (Chip Select) VIH and VIL of CS1 have 3 functions: 1. To accomplish the interface with a microcomputer in 5V operation. 2. To inhibit the control bus, data bus and address bus and to reduce input gate pass current in the stand-by mode. 3. To protect internal data when the mode is moved to and from stand-by mode. To realize the above functions: 1. More than 4/5 VDD should be applied to this IC for the interface with a microcomputer in 5V operation. 2. In moving to the stand-by mode, 1/5 VDD should be applied so that all data buses should be disabled. In the stand-by mode, approx. 0V should be applied. 3. To and from the stand-by mode, obey the following Timing chart. ] The stand-by mode means the power supply voltages from 4V to 2V up to the minimum value (2V) of the operating power supply voltage and the interface with the IC external is not guaranteed while the clock time works. To Standby Mode From Standby Mode 4~6V VDD 4V 4V 2~4V CS1 2 V 5 DD 2µs (MIN) 2µs (MIN) The CS0 of this IC does not generate "H" or WR during this duration. 4 5 Less than 15 VDD VDD The interface with this IC is available after this. As a matter of fact, regard this matter as the data holding in the stand-by of STATIC RAM. 61 MSM62X42B ¡ Semiconductor Set STD.P at alarm mode Set alarm at 9:00 MASK BIT ITRPT/STND BIT t1 , t0 ¨ 0 ¨ 1 ¨ 1, 1 Start interruption CPU Activation Read Register RD D2 =1 ? NO YES Read H10 and H1 Content AM 9:00? Repeat NO YES CPU HALT or CPU STAND BY 62 ¡ Semiconductor MSM62X42B TYPICAL APPLICATION - POWER SUPPLY CIRCUIT (A capacitor for bypass should be attached near the IC.) [When supplied from +5V power supply system.] +5.1V A495 100W 51K 10K C372 10K 22µ + + 0.01µ + Ceramic capacitor RL M C RL VDD MSM62X42B GND When the power is changed from ON to OFF, the reverse-current flows temporally from collector to emitter of a transistor. Therefore, use a capacitor of large capacitance here. 1.2V ¥ 3 = 3.6V Ni–Cd batteries +5V 4.7µF Tantalum capacitor VCE (sat) = 0.1v 100W B + 1.5¥2=3V + – Dry cells Tantalum capacitor 4.7µF 0.01 µF VDD Ceramic capacitor MSM62X42B GND [When supplied from higher power supply system than +5V.] + V (Higher power supply over about 1.5V than +5V) R1 D1 +5V (Power supply of peripheral circuit) R2 +5.7V D2 100 W + 3.6V (Ni–Cd batteries) – 4.7µ + 0.01µ VDD Tantalum Ceramic capacitor capacitor MSM62X42B GND (Note) In order to reduce the level difference to VDD between +5V and MSM62 x 42B, use the same diodes for D1 and D2. 63 MSM62X42B ¡ Semiconductor IS1588 VF = 0.69V +5.7V 100 W or + C372 – 4.7µF + 0.01µ VDD Tantalum Ceramic capacitor capacitor MSM62X42BRS GND VF = 0.69V 1.2 ¥ 3 = 3.6V Ni–Cd batteries TYPICAL APPLICATION INTERFACE WITH MSM62X42B AND MICROCOMPUTER (8085) MSM62X42B 8085 MSM62X42B D3 D2 D1 D0 A3 A2 A1 A0 CS0 AD0~AD3 D3 D2 D1 D0 A3 A2 A1 A0 CS0 A4~A15 S1 S2 IO/M ALE RD WR DECODER AD3 AD2 AD1 AD0 R1 R2 ALE RD WR A0~A11 or A12~A15 S1 S0 IO/M RD WR DECODER 8085 R1 R2 ALE RD WR Note 1) If the address of program memory and the address of MSM62X42B do not overlap, the S1 and S0 of the Decoder are not required. Note 2) If the address of IO/MSM62X42B for the decoder does not overlap with other addresses, this is not required. Note 3) If 8085 does not enter into the state of HALT or HOLD during CS1 = "H" of MSM62X42B, R1 and R2 are not required. 64 ¡ Semiconductor MSM62X42B (Z80) MSM62X42B Z80 D3 D2 D1 D0 D3 D2 D1 D0 A3 A2 A1 A0 A3 A2 A1 A0 A0~A15 IORQ or MREQ RD WR DECODER Note) It depends upon the switching characteristics decided by a X’tal used for a Z80 that either of IORQ and MREQ is used. CS0 VDD G1 G2 ALE RD WR (MCS48) MCS48 MSM62X42B BUS3 BUS2 BUS1 BUS0 D3 D2 D1 D0 DECODER A3 A2 A1 A0 BUS4~7 CS0 ALE RD WR ALE RD WR 65 MSM62X42B ¡ Semiconductor REFERENCE DATA (1) Frequency vs. Temperature Frequency temperature characteristics can be estimated as follows: Dfx (PPM) = f0T + a(qT – qx)2 Dfx (PPM) : frequency shift at arbitrary : temperature f0T (PPM) : frequency shift at qT a(PPM) : temperature coefficient : (–0.035 ppm/°C2 ± 0.005 : (ppm/°C2) qT (°C) : turning point temperature : (25°C ± 5°C) qx (°C) : arbitrary temperature 11.574 ppm equals to the error of a second/ day. Temp. (°C) –20 –10 0 0 10 20 30 40 50 60 70 Frequency Df/f (ppm) –10 –20 –30 –40 –50 –60 –70 Typical qT = 25°C a = –0.035ppm/°C2 (2) Current Consumption vs. Supply Voltage IDD [µA] 30 CS1 = 0V at 25°C 25 20 15 10 5 Voltage 2.0 3.0 4.0 5.0 [V] 3.0 4.0 5.0 (3) Frequency vs. Supply Voltage D fx [PPM] 4 2 0 –2 –4 –6 –8 –10 66 at 25°C 2.0 [V] Voltage ¡ Semiconductor MSM62X42B SUPPLEMENTARY DESCRIPTION 1. When "0" is written to the IRQ FLAG bit, the IRQ FLAG bit is cleared. However, if "0" is assigned to the IRQ FLAG bit when written to the other bits, the 30-sec. ADJ bit and the HOLD bit, the IRQ FLAG = 1 generated before the writing will be cleared. To avoid this, always set "1" to the IRQ FLAG unless "0" is written to it intentionally. By writing "1" to it, the IRQ FLAG bit does not become "1". 2. Since the IRQ FLAG bit becomes "1" in some cases when rewriting either of the t1, t0 or ITRPT/ STND bit of register CE, be sure to write "0" to the IRQ FLAG bit after writing to make valid the IRQ FLAG = 1 to be generated after it. 3. The relationship between SDT.P OUT and IRQ FLAG bit is shown below: open STD.P OUT IRQ FLAG Bit "L" 1 0 Approx. 1.95ms SUGGESTIONS FOR P.C.B ASSEMBLY 1. This IC can bear shock of fall from a height of 75 cm. However, the shock power of IC inserters might destroy resonators. It depends on the machines and conditions at your Company. We recommended to adjust the machine conditions before mass production. 2. The notice for soldering differs in DIP product and SOP product. • DIP Product Since the eutectic solder (melting point 183°C) is used for soldering the crystal resonator, destruction of crystal resonator or degradation of characteristics of resonators can be induced by high temperature (more than 150°C) inside the package. Soldering with solder dip bath or manual soldering is recommendable. Please refrain from soldering by hot air, reflow, infrared rays, etc. Soldering heat resistance test conditions : 260°C x 10 seconds. (Soldering for the lead must leave 1 mm from its base.) • SOP Product Soldering by hand or soldering by infrared ray reflow based on the temperature profile of our Company’s recommendation is desirable. (Refer to "Package information.) 3. The ultrasonic washing may damage the crystal resonator due to the use conditions. Therefore, we can not guarantee your use for the ultrasonic washing because of unknown factors about a kind of washing machine, electric power, hour, place to be set in a bath, etc. Be sure to confirm the use conditions before your use as well as with condition change when you have to use the ultrasonic washing machine unavoidably. (The ultrasonic washing machine of frequency 40 kHz can not be used for built-in the tuning - fork resonator of 32.768 kHz, but the one of frequency 28 kHz has the range available due to the conditions. However, be sure to confirm the setting conditions sufficiently for the abovementioned reasons.) 4. Please keep parts free from dew. 67