Ordering number : ENA0651 Bi-CMOS LSI LV4900HR Class-D Audio Power Amplifier BTL 10W×2ch Overview The LV4900HR is a 10W per channel stereo digital power amplifier that takes analog inputs. The LV4900H uses unique SANYO-developed feedback technology to achieve excellent audio quality despite being a class D amplifier and can be used to implement high quality flat display panel (FDP) based systems. Features • Supports circuit designs that do not require output LC filters • BTL output, class D amplifier system • Unique SANYO-developed feedback technology achieves superb audio quality • High-efficiency class D amplifier • Soft muting function reduces impulse noise at power on/off • Full complement of built-in protection circuits : overcurrent protection, thermal protection, and low power supply voltage protection circuits • Built-in bootstrap diodes • Internal oscillator frequencies : channel 1 = 325kHz, channel 2 = 300kHz Functions • 10W output (At VD = 12V, RL = 8Ω, THD + N = 10%) • 15W output (At VD = 12V, RL = 4Ω, THD + N = 10%) • Efficiency : 88% (VD = 12V, RL = 8Ω, fin = 1kHz, PO = 10W) • Low THD + N : 0.15% (VD = 12V, RL = 8Ω, fin = 1kHz, PO = 1W, Filter : AES17) • Noise : 100µVrms (Filter : A-weight) Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 51507 MS PC 20061208-S00003 No.A0651-1/14 LV4900HR Specifications Maximum Ratings at Ta = 25°C Parameter Symbol Maximum supply voltage VD Maximum output current IO peak Allowable power dissipation Pd max Conditions Ratings Externally applied voltage Unit 15 Independent package V 3.75 A/ch 886 mW Operating temperature Topr -25 to +75 °C Storage temperature Tstg -50 to +150 °C Operating Conditions at Ta = 25°C Parameter Symbol Ratings Conditions min Recommended supply voltage range VD Externally applied voltage Recommended load resistance RL Speaker load typ Unit max 10 12 4 8 14 V Ω Electrical Characteristics at Ta = 25°C, VD = 12V, RL = 8Ω, L = 22µH, C = 0.33µF Parameter Symbol Ratings Conditions min typ Unit max Ist STBY = L, MUTE = L 13 25 µA Muting current Imute STBY = H, MUTE = L 13.5 20 mA Quiescent current ICCO STBY = H, MUTE = H 60 70 mA VG fin = 1kHz, VO = 0dBm 29 31 dB 150 mV Standby current Voltage gain Output offset voltage Voffset Rg = 0 Total harmonic distortion THD@1W PO = 1W, fin = 1kHz, AES17 Maximum output PO1@10% THD+N = 10%, AES17 Channel separation CH sep. Ripple rejection ratio SVRR -150 0.15 0.5 % 8 10 W Rg = 0, VO = 0dBm, DIN AUDIO 55 70 dB fr = 100Hz, Vr = 0dBm, Rg = 0, A-weight 50 Noise VNO Rg = 0, A-weight High-level output voltage VIH STBY pin and MUTE pin Low-level output voltage VIL STBY pin and MUTE pin Power supply voltage drop protection 27 65 100 dB 300 3 µVrms V 1 V UV_UPPER VD pin voltage monitor 8.0 V UV_LOWER VD pin voltage monitor 7.0 V circuit upper limit value Power supply voltage drop protection circuit lower limit value Note : The values of these characteristics were measured in the SANYO test environment. The actual values in an end system will vary depending on the printed circuit board pattern, the external components actually used, and other factors. Package Dimensions unit : mm (typ) 3251 17.8 (6.2) 19 1 2.0 18 0.3 0.25 2.45max (2.25) 0.8 2.7 0.1 (0.5) 0.65 (4.9) 7.9 10.5 36 SANYO : HSOP36R(375mil) No.A0651-2/14 LV4900HR Block Diagram and Application Circuit Example 1 (RL = 8Ω) 1µF 1 2 OUT1+ 22µH STBY PVD1 PVD1 35 VIN1+ Output stage 3 0.1µF 0.33µF BOOT1+ 5 1µF BOOT1- 0.33µF 22µH VIN1- 4 1µF RL 36 VDD1 Control delay 0-5V NC 1µF IN_CH1+ 34 1µF 33 IN_CH1- Receiver 32 NC VCC 31 6 0.1µF OUT1- Output stage 7 8 9 30 NC BIASCAP PGND1 29 VBIAS PGND1 28 1000µF VD Thermal 10 11 22µH OUT2- Supply Sequence 1µF PGND2 GND PGND2 MUTECAP 12 MUTE Output stage 1µF 1µF 27 1µF 26 25 0-5V 0.1µF 0.33µF RL BOOT2- 13 1µF 1uF 14 BOOT2+ 0.33µF 22µH VDD2 Control delay VIN2- 16 17 18 NC 23 NC 1µF 15 0.1µF OUT2+ Receiver 24 Output stage PVD2 PVD2 VIN2+ 22 IN_CH2IN_CH2+ 21 1µF 20 NC 19 NC 1µF No.A0651-3/14 LV4900HR Application Circuit Example 2 (RL = 4Ω) 1µF 1 VD 2 OUT1+ 22µH STBY PVD1 PVD1 35 VIN1+ Output stage 3 0.1µF 0.33µF BOOT1+ 5 1µF VD BOOT1- 0.33µF 22µH VIN1- 4 1µF RL 36 VDD1 Control delay 0-5V NC 1µF IN_CH1+ 34 1µF 33 IN_CH1- Receiver 32 NC VCC 31 6 0.1µF OUT1- Output stage 7 8 9 30 NC BIASCAP PGND1 29 VBIAS PGND1 28 1000µF VD Thermal 10 VD 11 22µH OUT2- Supply Sequence 1µF PGND2 GND PGND2 MUTECAP 12 MUTE Output stage 1µF 1µF 27 1µF 26 25 0-5V 0.1µF 0.33µF RL BOOT2- 13 1µF 1uF 14 VD BOOT2+ 0.33µF 22µH VDD2 Control delay VIN2- 16 17 18 NC 23 NC 1µF 15 0.1µF OUT2+ Receiver 24 Output stage PVD2 PVD2 VIN2+ 22 IN_CH2IN_CH2+ 21 1µF 20 NC 19 NC 1µF No.A0651-4/14 LV4900HR Pin Equivalent Circuit Pin No. Pin I/O Description 1 PVD1 Channel 1 power system power supply 2 PVD1 Channel 1 power system power supply 3 OUT1+ O Equivalent Circuit Channel 1 high side output VD 3 GND 4 BOOT1+ I/O Bootstrap I/O pin, channel 1 power supply high side 5 VDD1 O Internal power supply decoupling capacitor VD connection 2kΩ 5 GND 6 BOOT1- Bootstrap I/O pin, channel 1 power supply low side 7 OUT1- O Channel 1 low side output VD 7 GND 8 PGND1 Channel 1 power system ground 9 PGND1 Channel 1 power system ground 10 PGND2 Channel 2 power system ground 11 PGND2 12 OUT2- Channel 2 power system ground O Channel 2 low side output VD 12 GND 13 BOOT2- I/O Bootstrap I/O pin, channel 2 power supply low side Continued on next page. No.A0651-5/14 LV4900HR Continued from preceding page Pin No. 14 Pin VDD2 I/O O Description Equivalent Circuit Internal power supply decoupling capacitor VD connection 2kΩ 14 GND 15 BOOT2+ I/O Bootstrap I/O pin, channel 2 power supply low side 16 OUT2+ O Channel 2 high side output VD 16 GND 17 PVD2 Channel 2 power system power supply 18 PVD2 Channel 2 power system power supply 19 NC No connection 20 NC 21 VIN2+ No connection I Channel 2 noninverting inputt VD 300Ω 30kΩ 21 VBIAS GND 22 VIN2- I Channel 2 inverting input VD 300Ω 30kΩ 22 VBIAS GND NC 25 MUTE No connection No connection I Muting control VD 100kΩ NC 24 25 1kΩ 500kΩ 23 GND Continued on next page. No.A0651-6/14 LV4900HR Continued from preceding page. Pin No. Pin I/O 26 MUTECAP O Description Muting system capacitor connection Equivalent Circuit VCC VDD VD 1kΩ 1kΩ 27 GND 28 VBIAS 100kΩ GND 26 Analog system ground O Internal power supply decoupling capacitor VD 100Ω 100Ω connection 28 GND 29 BIASCAP O Internal power supply decoupling capacitor VD 100kΩ connection 1kΩ 100kΩ 29 GND 30 NC 31 VCC No connection O Internal power supply decoupling capacitor VD connection 2kΩ 31 GND NC 33 VIN1- No connection I Channel 1 inverting input VD 300Ω 33 30kΩ 32 VBIAS GND Continued on next page. No.A0651-7/14 LV4900HR Continued from preceding page. Pin No. 34 Pin VIN1+ I/O I Description Equivalent Circuit Channel 1 noninverting input VD 300Ω 30kΩ 34 VBIAS GND NC 36 STBY No connection I Standby mode control VD 100kΩ 35 1kΩ 500kΩ 36 GND Note: Smoothing capacitors must be connected to each power supply pin. No.A0651-8/14 LV4900HR Functional Descriptions System Standby The bias levels are turned on and off under control of the high/low state of the STBY pin. When the STBY pin is low, the bias levels will be turned off, and when that pin is high, the bias levels will be applied. Mute Function The mute function is provided mainly to mute the output so that impulse noise will not appear in the output when the power supply is being turned on. (1) Output Muting The output PWM signal can be turned on or off by setting the MUTE pin high or low. When the MUTE pin is low, the internal oscillator is stopped. This oscillator operates at all times that the MUTE pin is high. (2) Power On Sequence Applications should provide a power-on muting period of at least 500ms to minimize impulse noise. 5V/DIV. 5 [V] 0 STBY pin Internal power supply 5 [V] 0 MUTE pin MUTE pin capacitor voltage Output pin Turn-on time Amplifier on Turn-on time: the time between the point the STBY pin is set high and the point the MUTE pin is set high. (3) Power Down Sequence Applications should provide a power down muting period of at least 100ms to minimize impulse noise. 5V/DIV. 5 [V] STBY pin 0 Internal power supply 5 [V] MUTE pin 0 MUTE pin capacitor voltage Output pin Amplifier on Power down time Turn-off time: the time between the point the MUTE pin is set low and the point the STBY pin is set low. No.A0651-9/14 LV4900HR LV4900H customer bread board rev.1.0 Pattern Silk No.A0651-10/14 LV4900HR Components * Symbol Part No. ----- SW1 Standby switch. Lower position: standby state Function ----- SW2 Mute switch. Lower position: mute state CVCC C1 Internal power supply (VCC) output coupling capacitor CBIASCAP C2 Internal power supply (VBIAS) input coupling capacitor CVBIAS C3 Internal power supply (VBIAS) output coupling capacitor CMUTE C4 CIN C5, C6, C7, C8 CVDD C9, C10 Internal power supply (VDD) output coupling capacitors VD high-frequency attenuation capacitors * CVD C11, C12 * CBOOT C13, C14, C15, C16 LO L1, L2, L3, L4 CO C17, C18, C19, C20 CVD C21 COUT C22, C23 Soft muting time constant adjustment capacitor Input capacitors Bootstrap capacitor Output low-pass filter coils: fc = 1/ (2π√LoCo) Output low-pass filter capacitors VD power supply capacitors Output for capacitors * CVDD, CVD and CBOOT, Each capacitor is arranged in the neighborhood of IC as much as possible. No.A0651-11/14 LV4900HR Ist -- VD 16 Imute -- VD 16 RL = 8Ω Rg = 0 STBY = L MUTE = L Muting current, Imute – mA Standby current, Ist – µA 20 12 8 4 0 RL = 8Ω Rg = 0 STBY = H MUTE = L 12 8 4 0 0 2 4 6 8 10 12 14 0 2 4 Externally applied voltage, VD – V ICC -- VD 60 8 10 12 14 12 14 12 14 VCC -- VD 10 RL = 8Ω Rg = 0 STBY = H MUTE = H Supply voltage, VCC – V Quiescent current, ICC – mA 80 6 Externally applied voltage, VD – V 40 20 0 RL = 8Ω Rg = 0 8 6 4 2 0 0 2 4 6 8 10 12 0 14 2 4 Externally applied voltage, VD – V VBIAS -- VD 8 6 8 10 Externally applied voltage, VD – V 6 RL = 8Ω Rg = 0 VDD -- VD RL = 8Ω Rg = 0 Supply voltage, VDD – V 5 VBIAS – V 6 4 2 4 3 2 1 0 0 2 4 6 8 10 12 0 0 14 2 4 Externally applied voltage, VD – V 10 7 5 3 2 Power -- VIN 20 VD = 12V fin = 1kHz 2ch-Drive AES17 16 1.0 7 5 3 2 RL = Power – W Power – W 100 7 5 3 2 4Ω RL = 8Ω 0.1 7 5 3 2 8 10 Power -- VD fin = 1kHz THD+N = 10% 2ch-Drive AES17 RL Ω =4 12 RL = 8Ω 8 4 0.01 10 6 Externally applied voltage, VD – V 2 3 5 7 100 2 3 Input voltage, VIN – mVp 5 7 1000 0 8 9 10 11 12 13 14 Externally applied voltage, VD – V No.A0651-12/14 LV4900HR 10 7 5 fin = 6.67kHz 1 7 5 3 2 fin = 1kHz 0.1 7 5 VD = 12V RL = 8Ω PO = 1W 2ch-Drive AES17 10 7 5 3 2 10 7 5 3 2 10 7 5 3 2 fin = 100Hz 3 2 0.01 0.001 2 3 THD+N -- Frequency 10 7 5 3 2 THD+N – % THD+N – % 3 2 THD+N -- Power VD = 12V RL = 8Ω 2ch-Drive AES17 0.001 5 70.01 2 3 5 7 0.1 2 3 5 7 1 2 3 5 7 10 10 2 3 5 7 100 Power – W 10 5 2 3 5 7 1k 2 3 5 7 10k 2 3 5 7100k 2 3 5 7100k Frequency, f – Hz Response -- Frequency Phase -- Frequency 60 VD = 12V RL = 8Ω PO = 1W 40 Phase – deg Response – dB 20 0 –5 0 – 20 – 10 – 40 – 15 VD = 12V RL = 8Ω PO = 1W – 60 – 20 – 80 10 2 3 5 7 100 2 3 5 7 1k 2 3 5 7 10k 2 3 5 7100k 10 2 3 5 7 100 Frequency, f – Hz – 10 – 20 CH Sep. -- Frequency 7 5 – 30 – 40 – 50 – 60 CH1→CH2 CH2→CH1 2 3 5 7 100 2 3 5 7 1k 2 3 VD = 12V RL = 8Ω A-weight 3 2 0.1 7 5 3 0.01 5 710k 2 3 5 7100k 1 2 3 5 7 10 2 3 5 7100 2 3 5 7 1k Rg – Ω Frequency, f – Hz – 10 – 20 SVRR -- Ripple Frequency RL = 8Ω 80 – 30 – 40 – 50 RL = 4Ω 60 40 – 60 VD = 12V fin = 1kHz 2ch-Drive AES17 20 – 70 – 80 10 2 3 5 7 100 2 3 5 710k 2 3 5 7100k Efficiency -- Power 100 VD = 12V RL = 8Ω Rg = 0 VDr = 0dBm A-weight Efficiemcy – % Ripple rejection ratio, SVRR – dB 0 5 7 10k 2 – 70 10 2 3 VNO -- Rg 10 VD = 12V RL = 8Ω Rg = 0 VO = 0dBm DIN AUDIO – 80 5 7 1k Frequency, f – Hz Noise, VNO – mVrms Channel separation, CH Sep. – dB 0 2 3 2 3 5 7 1k 2 3 5 7 10k Ripple Frequency – Hz 2 3 5 7100k 0 0 3 6 9 12 15 Power – W No.A0651-13/14 LV4900HR SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of May, 2007. Specifications and information herein are subject to change without notice. PS No.A0651-14/14