SANYO LV49157V

Ordering number : ENA1567
Bi-CMOS LSI
LV49157V
Class-D Audio Power Amplifier with built-in
Headphone Ampifier
BTL 15W × 2ch
Overview
The LV49157V is a 15W per channel stereo digital power amplifier that takes analog inputs. The LV49157V uses unique
SANYO-developed feedback technology to achieve excellent audio quality despite being a class D amplifier and can be
used to implement high quality flat display panel (FDP) based systems.
Features
• BTL output, class D amplifier system
• Unique SANYO-developed feedback technology achieves superb audio quality
• High-efficiency class D amplifier
• Soft muting function reduces impulse noise at power on/off
• Full complement of built-in protection circuits : over current protection, thermal protection, and low power supply
voltage protection circuits
• Built in Power limiter
• Built in Headphone Amplifier
Functions
• Power
: 15W × 2ch output (VD = 15V, RL = 8Ω, fin = 1kHz, AES17, THD + N = 10%)
• Efficiency : 93% (VD = 15V, RL = 8Ω, fin = 1kHz, PO = 15W)
• THD + N : 0.08% (VD = 15V, RL = 8Ω, fin = 1kHz, PO = 1W, Filter : AES17)
• Noise
: 90μVrms (Filter : A-weight)
• 60mW Stereo headphone Amplifier (VD = 15V, RL = 16Ω, THD + N = 10%)
• Package SSOP44J (275mil)
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
N0409 SY 20090918-S00001 No.A1567-1/30
LV49157V
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Maximum supply voltage
VD
Supply voltage
Allowable power dissipation
Pd max
Package thermal resistance
θjc
Maximum junction temperature
Tj max
Operating temperature
Storage temperature
Ratings
Unit
20
V
Our PCB, Soldered *
5
W
Our PCB, Soldered *
2.1
°C/W
3.6
°C/W
150
°C
Topr
-25 to +75
°C
Tstg
-50 to +150
°C
Our PCB, Not soldered *
* : Mounted on a specified board 110.0mm × 100.0mm × 1.5mm, glass epoxy (two-layer)
Recommended Operating Range at Ta = 25°C
Parameter
Symbol
Ratings
Conditions
min
typ
Unit
max
Supply voltage range
VD
Supply voltage
9
15
Load impedance range
RL
Speaker load
4
8
18
Ω
V
RL(HP)
Headphone
16
Ω
Electrical Characteristics at Ta = 25°C, VD = 15V
Parameter
Symbol
Ratings
Conditions
min
typ
Unit
max
Main Amplifier (RL = 8Ω,L = 33μH (TOKO : A7502BY-330M), C = 0.1μF,CL=0.47μF)
μA
Standby current
Ist
STBY = L, MUTE = L
Mute current
Imute
STBY = H, MUTE = L
14
20
26
mA
Quiescent current
ICCO
STBY = H, MUTE = H
35
45
55
mA
Voltage gain
VG
fin = 1kHz, VO = 0dBm
28
30
32
dB
Offset voltage
Voffset
Rg = 0
150
mV
Total harmonic distortion
THD+N
PO = 1W, fin = 1kHz, AES17
Output power
PO
THD+N = 10%, AES17
13
15
W
Channel separation
CH sep.
Rg = 0, VO = 0dBm, DIN AUDIO
55
70
dB
Ripple rejection ratio
SVRR
fr = 100Hz, Vr = 0dBm, Rg = 0, DIN AUDIO
50
60
Noise
VNO
Rg = 0, A-weight
High-level input voltage
VIH
STBY and MUTE pin
Low-level input voltage
VIL
STBY and MUTE pin
Under voltage protection UPPER
UV_UPPER
VD voltage measure
8.0
V
Under voltage protection LOWER
UV_LOWER
VD voltage measure
7.0
V
1
-150
0.08
10
0.4
%
dB
300
μVrms
3
VD
V
0
1
90
V
Headphone Amplifier(RL = 16Ω,fin=1kHz)
Quiescent current
ICCO
HP_STBY = H
Voltage gain
VG
VO = -10dBm
Total harmonic distortion
THD+N
PO = 10mW, DIN AUDIO
Output power
PO
THD+N = 10%, DIN AUDIO
48
Channel separation
CH sep.
fin=1kHz, Rg = 0, VO = -10dBm, DIN AUDIO
55
70
Ripple rejection ratio
SVRR
fr = 100Hz, Vr = 0dBm, Rg = 0, DIN AUDIO
55
Noise
VNO
Rg = 0, A-weight
High-level input voltage
VIH
HP_STBY pin
VIL
HP_STBY pin
Low-level input voltage
9.5
8
12
mA
11.5
13.5
dB
0.05
0.3
%
60
72
W
dB
70
dB
60
μVrms
3
VD
V
0
1
V
12
Note : The values of these characteristics were measured in the SANYO test environment. The actual values in an end system will vary depending on the
printed circuit board pattern, the external components actually used, and other factors.
No.A1567-2/30
LV49157V
Package Dimensions
unit : mm (typ)
3285
TOP VIEW
BOTTOM VIEW
Exposed Die-Pad
15.0
23
0.5
5.6
7.6
44
1
22
0.22
0.65
0.2
1.7max
(0.68)
(1.5)
SIDE VIEW
SANYO : SSOP44J(275mil)
Pd max - Ta
8
Allowable power dissipation, Pd max - W
Mounted on a specified board : 110 × 100 × 1.5mm3
glass epoxy (two-layer)
6
Soldered = 5.05W
4
Not Soldered = 3.35W
2
0
—25
0
25
50
75
100
125
150
Ambient temperature, Ta - C
PVD1
PVD1
OUT1+
OUT1+
BOOT1+
VDD1
BOOT1-
OUT1-
OUT1-
PGND1
PGND1
PGND2
PGND2
OUT2-
OUT2-
BOOT2-
VDD2
BOOT2+
OUT2+
OUT2+
PVD2
PVD2
Pin Assignment
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
MUTE
STBY
VIN1+
VIN1-
PLC
VIN2-
VIN2+
MUTECAP
VCC
BIASCAP
VBIAS
VREG5
GND
HP_IN1
HP_RF
HP_IN2
HP_GND1
HP_OUT1
HP_REF
HP_OUT2
HP_GND2
HP_STBY
LV49157
Top view
No.A1567-3/30
LV49157V
Block Diagram and Application Circuit
+
0-5V
1
0-5V
2
VIN1+
3
4
5
6
VIN2+
PVD1
STBY
PVD1
FB
8
9
10
11
12
13
VIN1-
+
15
PLC
41
REC. & CONT.
40
VIN2-
VDD1
37
OUTPUT
VCC
36
FB
BIASCAP
PGND1
VBIAS
PGND1
START
SEQUENCE
POWER LIMITER
VREG5
GND
PGND2
PGND2
FB
RL(HP)
17
+
18
19
+
20
21
22
REC. & CONT.
HP_OUT1
HP_OUT2
HP_GND2
HP_STBY
26
OUTPUT
25
FB
PVD2
PVD2
OUT1-
VD
OUT2OUT2BOOT2SP
28
27
HP_REF
OUT1-
32
29
Head phone
RL(HP)
SP
BOOT1-
33
30
VDD2
BOOT1+
34
31
HP_GND1
OUT1+
35
OUTPUT
HP_RF
OUT1+
39
38
MUTECAP
16
HP_IN2
43
OUTPUT
14
HP_IN1
44
42
7
+
0-5V
MUTE
BOOT2+
OUT2+
OUT2+
24
23
+
No.A1567-4/30
LV49157V
Pin Equivalent Circuit
Pin No.
1
Pin name
MUTE
I/O
I
Description
Equivalent Circuit
Mute control pin
VD
250kΩ
1
10kΩ
100kΩ
GND
2
STBY
I
Standby control pin
VD
250kΩ
2
10kΩ
100kΩ
GND
3
VIN1+
I
Input pin, CH1 plus
VD
3
300Ω
30kΩ
VBIAS
GND
4
VIN1-
I
Input pin, CH1 minus
VD
4
300Ω
30kΩ
VBIAS
GND
5
PLC
I
Power level control pin
VD
5
200Ω
GND
Continued on next page.
No.A1567-5/30
LV49157V
Continued from preceding page.
Pin No.
6
Pin name
VIN2-
I/O
I
Description
Equivalent Circuit
Input pin, CH2 minus
VD
300Ω
6
30kΩ
VBIAS
GND
7
VIN2+
I
Input pin, CH2 plus
VD
300Ω
7
30kΩ
VBIAS
GND
8
MUTECAP
O
Muteing sysytem capcitor connection
VD
VDD
20kΩ 10kΩ
8
GND
9
VCC
O
Internal power supply
VD
decupling capacitor connection
9
GND
10
BIASCAP
O
Internal regulator
VD
decupling capacitor connection
100kΩ
10
1kΩ
1kΩ
100kΩ
GND
Continued on next page.
No.A1567-6/30
LV49157V
Continued from preceding page.
Pin No.
11
Pin name
VBIAS
I/O
O
Description
Equivalent Circuit
Internal regulator
VD
decupling capacitor connection
500Ω
11
500Ω
GND
12
VREG5
O
Internal regulator
VD
decupling capacitor connection
12
500Ω
GND
13
GND
14
HP_IN1
Analog Ground
I
PREVD
VD
Headphone CH1 input
14
VREF
HP_GND
15
HP_RF
O
VD
Internal regulator
decupling capacitor connection
15
HP_GND
16
HP_IN2
I
VD
Headphone CH2 input
PREVD
16
VREF
HP_GND
Continued on next page.
No.A1567-7/30
LV49157V
Continued from preceding page.
Pin No.
Pin name
17
HP_GND1
18
HP_OUT1
I/O
Description
Equivalent Circuit
Headphone Ground
O
VD
Headphone CH1 output
18
HP_GND
19
HP_REF
O
PREVD
Internal regulator
decupling capacitor connection
19
HP_GND
20
HP_OUT2
O
VD
Headphone CH2 output
20
HP_GND
21
HP_GND2
22
HP_STBY
Headphone Ground
I
VD
Headphone Amplifier standby control pin
22
GND
23
PVD2
CH2 power supply
24
PVD2
CH2 power supply
25
OUT2+
O
Output pin, CH2 plus
VD
25
GND
Continued on next page.
No.A1567-8/30
LV49157V
Continued from preceding page.
Pin No.
26
Pin name
OUT2+
I/O
O
Description
Output pin, CH2 plus
Equivalent Circuit
VD
26
GND
27
BOOT2+
I/O
Boot strap pin, CH2 plus
28
VDD2
O
CH2 internal regulator decupling capacitor
29
BOOT2-
I/O
Boot strap pin, CH2 minus
30
OUT2-
O
Output pin, CH2 minus
connection
VD
30
GND
31
OUT2-
O
Output pin, CH2 minus
VD
31
GND
32
PGND2
CH2 Power Ground
33
PGND2
CH2 Power Ground
34
PGND1
CH1 Power Ground
35
PGND1
CH1 Power Ground
36
OUT1-
O
Output pin, CH1 minus
VD
36
GND
37
OUT1-
O
Output pin, CH1 minus
VD
37
GND
38
BOOT1-
I/O
Boot strap pin, CH1 minus
39
VDD1
O
CH1 internal regulator decupling capacitor
40
BOOT1+
I/O
Boot strap pin, CH1 plus
connection
Continued on next page.
No.A1567-9/30
LV49157V
Continued from preceding page.
Pin No.
41
Pin name
OUT1+
I/O
O
Description
Output pin, CH1 plus
Equivalent Circuit
VD
41
GND
42
OUT1+
O
Output pin, CH1 plus
VD
42
GND
43
PVD1
CH1 power supply
44
PVD1
CH1 power supply
No.A1567-10/30
LV49157V
Operation Mode Summary
STBY mode (STBY = L, MUTE = L and HP_STBY = L)
Each bias becomes off state when the regulator in IC has been turned off.
The most of circuits becomes off state.
The supply current : 1μA (typical).
MUTE mode (STBY = H and MUTE = L)
Each bias becomes on state when the regulator in IC has been turned on.
When more than half of the circuits are active, the amplifier in the output stages become off.
The supply current : 20mA (typical).
Operation mode (STBY = H, MUTE = H and HP_STBY = H)
The LV49157V operates as D-class amplifier and Headphone amplifier.
The output signal is synchronized with the input signal.
The current of the main amplifier is 45mA (typical) in our recommendation condition, and the current of the headphone
amplifier is 8mA (typical) at RG=0.
Main amplifier function image
No.A1567-11/30
LV49157V
ON TIME/OFF TIME
Secure and control ON TIME and OFF TIME about the control of the terminal STBY and the terminal MUTE for the Pop
noise decrease. The following, ON TIME, and OFF TIME are the recommendation and set time in our recommendation
constant.
ON TIME
Please secure ON TIME of 350msec or more for reducing Pop noise.
Function image
ON TIME • • • the time until the MUTE pin is set to high level after the STBY pin is set to high level
OFF TIME
Please secure OFF TIME of 1000msec or more for reducing Pop noise.
Function image
OFF TIME • • • the time until the STBY pin is set to low level after the MUTE pin is set to low level
No.A1567-12/30
LV49157V
SOFT MUTE
The soft mute circuit is able to use fade in/fade out function, and the main amplifier can set Rise time and fall time by the
time constant of the MUTECAP capacitor.
Main amplifier FADE IN
Mute rise time is Applpx.450msec in our recommended external components.
5V/DIV.
MUTE pin
MUTECAP pin
[OUT+] vs [OUT-]
Mute rise time
Main amplifier FADE IN function image
Main amplifier FADE OUT
Mute fall time is Applpx.450msec in our recommended external components.
5V/DIV.
MUTE pin
MUTECAP pin
[OUT+] vs [OUT-]
Mute fall time
Main amplifier FADE OUT function image
No.A1567-13/30
LV49157V
The headphone amplifier can set Rise time and fall time by the time constant of the HP_RF capacitor.
Headphone amplifier FADE IN
Rise time is Applpx.900msec in our recommended external components.
HP_STBY pin
HP_RF terminal
HP_OUT
rise time
Headphone amplifier FADE IN function image
Headphone amplifier FADE OUT
Fall time is Applpx.900msec in our recommended external components.
HP_STBY pin
HP_RF terminal
HP_OUT
fall time
Headphone amplifier FADE OUT function image
No.A1567-14/30
LV49157V
Power supply lowering protection circuit
Since the instable operation in the low voltage is prevented by using this circuit, after the voltage of the PVD pin is
monitored and the voltage below the Attack voltage (PVD = 8V typ.), AMP is turned off.
Also, to prevent the instable operation when the voltage of the PVD pin is decreased by any cause during operations, the
Attack voltage (PVD = 7V typ.) is set.
The voltage of Attack and Recover has hysteresis (About 1V) to prevent ON/OFF continuous action of the power supply
lowering protection circuit.
Function image
Also, this IC is designed to turn off AMP in the same sequence that the MUTE is on as a pop noise measures when the
plug of products are put off.
Over current protection circuit
The over current protection circuit is a protection circuit * to protect the output DMOS from the over current and
corresponds to any mode of the power supply, GND and a load short.
The protection operation is performed when the current reaches the detection current value set out in IC and the output
DMOS is compulsorily turned off for about 20μsec.
After compulsorily tuning off the output DMOS, when the Amplifier is automatically reset in usual operation and the over
current flows continuously, the protection operation is performed again.
Function image
* The over current protection circuit is a function to avoid the abnormal state like the output short-circuit temporarily.
Unfortunately, we cannot guarantee that IC is not destroyed.
No.A1567-15/30
LV49157V
Thermal protection circuit
The LV49157V includes a thermal protection circuit to prevent damage to or destruction of the IC should abnormal
internal heat generation occur.
This means that should the IC junction temperature (Tj) rise above about 175°C due to inadequate heat dissipation or
other reason, the thermal protection circuit will operate to stop IC operation should the temperature rise further.
If the temperature is reduced by lowering the input level or other means, the thermal protection circuit will recover
automatically (about 105°C).
Recovery
Attack
Hystsrisis
Temperature (Tj) rise
Internal
TSD DET.
Shut
down
PWM
Internal
TSD DET.
Temperature (Tj) fall
Shut down
PWM
40
50
60
70
80
90
100 110 110 130 110 150 160 170 180 190 200
Junction temperature Tj [°C]
Function image
* The thermal protection circuit is a function to avoid the abnormal state temporarily.
Unfortunately, we cannot guarantee that IC is not destroyed.
No.A1567-16/30
LV49157V
PLC
The PLC (power level control) function is able to control the maximum index modulation by setting a value of external
PLC resistance R1 voluntarily, and prevent a PWM signal from becoming the over modulation mode. In addition, this
circuit can be use as output power limit circuit because the PLC function can set the maximum index modulation
voluntarily, and variable from 2W to 15W with output power linearly in the state that made the power supply voltage and
load resistance fixation. Because the PLC function can set the suitable rated output with the same power supply
voltage/speaker regardless of screen size in flat screen televisions by this, set can plan the commonization of the board.
Furthermore, The PLC function can reduce abnormal noise in the hard clip so that output wave pattern becomes the soft
clip when it limited output power.
MAX. Power
Half Power
Min. Power
PLC
5
LV49157V
R1
GND
13
Function image
Measuring condition
VD = 15V, RL = 8Ω, L = 33μH (TOKO : A7502BY-330M), C = 0.1uF,CL = 0.47μF,Ta = 25°C
R1 -- PO@THD + N = 10%
18
R1 [kΩ]
Po@10% [W]
3.0
0.694
3.6
1.073
4.7
1.982
6.2
3.642
10
7.5
5.562
8
8.2
6.855
9.1
8.591
10
10.64
VD = 15V
RL = 8Ω
fin = 1kHz
THD + N = 10%
2ch-Drive
AES17
PO@THD + N = 10% – W
16
14
12
6
4
13
15.32
2
15
15.94
0
20
16.01
0
2
4
6
8
10
12
14
16
18
20
R1 – kΩ
Setting example of the output power limit value
* When it is used this function as output power limit, please use the high-precision resistance such as the metal film
resistor when precision of the electricity value is necessary.
* The value of external PLC resistance R1 please connects more than 3kΩ.
* When it is changed a value of external PLC resistance R1, please turn off an amplifier.
No.A1567-17/30
LV49157V
Cut-off frequency calculation method and the output LC filter setting
L
OUT+
C
CL
RL
C
L
OUT-
The cut off frequency fc of the output LC filter is calculated by the following formula.
fc =
1
2π√2LCL
Also, by setting the cut off frequency fc, the value of CL and L is calculated by using the following formula.
1
CL =
2√2 × π RLfc
L=
√2 × RL
4π fc
In general, the value from 20% to 30% of CL is set to C.
In case of fc = 30kHz
RL [Ω]
L [μH]
CL [μF]
C [μF]
Q
4
15
1
0.22
0.650
6
22
0.68
0.15
0.636
8
33
0.47
0.1
0.704
16
68
0.22
0.047
0.739
Above formula is common calculation method and is a measure of constant setting.
In fact, it is necessary to set with each set that considers the speaker characteristics.
In addition, please set the fixed number to become Q ≤ 1 in currents in the fc neighborhood increasing if Q value of the LC
filter is big.
No.A1567-18/30
LV49157V
Glaph deta (Digital Amplifier: L = 33μH (TOKO : A7502BY-330M), C = 0.1μF, CL = 0.47μF)
Ist -- VD
0.15
0.1
0.1
0.05
0.05
0
0
2
4
6
8
10
12
14
16
0
—50
18
Imute -- VD
Muting current, Imute - mA
Muting current, Imute - mA
15
10
5
0
2
4
6
8
10
12
14
16
15
10
5
0
—50
18
Quiescent current, ICC - mA
Quiescent current, ICC - mA
30
20
10
6
8
10
12
14
16
40
30
20
10
0
—50
0
4
18
VCC -- VD
100
50
VCC -- Ta
20
15
15
VCC - V
VCC - V
0
Ambient temperature, Ta - C
Externally applied voltage, VD - V
20
100
50
ICC -- Ta
50
40
2
0
Ambient temperature, Ta - C
ICC -- VD
0
100
20
Externally applied voltage, VD - V
50
50
Imute -- Ta
25
20
0
0
Ambient temperature, Ta - C
Externally applied voltage, VD - V
25
Ist -- Ta
0.15
10
5
10
5
0
0
2
4
6
8
10
12
14
Externally applied voltage, VD - V
16
18
0
—50
0
100
50
Ambient temperature, Ta - C
No.A1567-19/30
LV49157V
BIASCAP -- VD
10
10
RL = 8Ω
Rg = 0
8
BIASCAP – V
BIASCAP – V
8
6
4
2
BIASCAP -- Ta
VD = 15V
RL = 8Ω
Rg = 0
6
4
2
0
0
2
4
6
8
10
12
14
16
0
– 50
18
Externally applied voltage, VD – V
VBIAS -- VD
10
10
RL = 8Ω
Rg = 0
8
VBIAS – V
VBIAS – V
8
6
4
0
0
100
VBIAS -- Ta
VD = 15V
RL = 8Ω
Rg = 0
6
4
2
4
6
8
10
12
14
16
0
– 50
18
Externally applied voltage, VD – V
5
4
4
VREG5 – V
5
3
3
2
2
1
1
4
6
8
10
12
14
16
VD = 15V
RL = 8Ω
Rg = 0
0
– 50
0
2
18
Externally applied voltage, VD – V
6
RL = 8Ω
Rg = 0
5
4
4
VDD – V
5
3
2
1
1
0
2
4
6
8
10
12
14
Externally applied voltage, VD – V
100
50
16
18
VDD -- Ta
VD = 15V
RL = 8Ω
Rg = 0
3
2
0
0
Ambient temperature, Ta – °C
VDD -- VD
6
100
50
VREG5 -- Ta
6
RL = 8Ω
Rg = 0
0
0
Ambient temperature, Ta – °C
VREG5 -- VD
6
VREG5 – V
50
2
2
VDD – V
0
Ambient temperature, Ta – °C
0
– 50
0
100
50
Ambient temperature, Ta – °C
No.A1567-20/30
LV49157V
VG -- VD
32
32
RL = 8Ω
fin = 1kHz
VO = 0dBm
31
Gain, VG -- dB
Gain, VG -- dB
31
30
VG -- Ta
VD = 15V
RL = 8Ω
fin = 1kHz
VO = 0dBm
30
29
29
28
9
10.5
12
13.5
16.5
15
28
--50
18
Voffset -- VD
20
RL = 8Ω
Rg = 0
Offset voltage, Voffset -- mV
Offset voltage, Voffset -- mV
20
0
--20
CH2
--40
CH1
--60
10.5
12
13.5
16.5
15
Voffset -- Ta
--20
CH2
--40
--60
CH1
--80
--50
18
THD+N -- VD
CH1
0.01
7
5
3
2
0.001
9
10.5
12
13.5
15
10
7
5
3
2
Total harmonic distortion, THD+N -- %
Total harmonic distortion, THD+N -- %
CH2
0.1
7
5
3
2
16.5
18
1
7
5
3
2
THD+N -- Ta
CH2
0.1
7
5
3
2
CH1
0.01
7
5
3
2
0.001
--50
THD+N = 10%
Output power, PO -- W
Output power, PO -- W
24
18
12
THD+N = 1%
6
0
9
10.5
12
13.5
15
16.5
Externally applied voltage, VD -- V
0
100
50
Ambient temperature, Ta -- °C
PO -- VD
RL = 8Ω
fin = 1kHz
2ch-Drive
AES17
100
50
VD = 15V
RL = 8Ω
fin = 1kHz
PO = 1W
2ch-Drive
AES17
Externally applied voltage, VD -- V
24
0
Ambient temperature, Ta -- °C
RL = 8Ω
fin = 1kHz
PO = 1W
2ch-Drive
AES17
1
7
5
3
2
100
VD = 15V
RL = 8Ω
Rg = 0
Externally applied voltage, VD -- V
10
7
5
3
2
50
0
--80
9
0
Ambient temperature, Ta -- °C
Externally applied voltage, VD -- V
18
18
PO -- Ta
VD = 15V
RL = 8Ω
fin = 1kHz
2ch-Drive
AES17
THD+N = 10%
12
THD+N = 1%
6
0
--50
0
100
50
Ambient temperature, Ta -- °C
No.A1567-21/30
LV49157V
CHsep. -- VD
0
RL = 8Ω
fin = 1kHz
Rg = 0
VO = 0dBm
DIN AUDIO
--20
Channel separation, CHsep. -- dB
Channel separation, CHsep. -- dB
0
--40
--60
CH1→CH2
CH2→CH1
--80
--100
9
10.5
13.5
12
15
16.5
--20
CHsep. -- Ta
VD = 15V
RL = 8Ω
Rg = 0
VO = 0dBm
DIN AUDIO
--40
--60
CH1→CH2
CH2→CH1
--80
--100
--50
18
SVRR -- VD
0
RL = 8Ω
fin = 100Hz
Rg = 0
VDr = 0dBm
DIN AUDIO
--20
Ripple rejection ratio, SVRR -- dB
Ripple rejection ratio, SVRR -- dB
0
--40
CH1
--60
CH2
--80
9
10.5
13.5
12
15
16.5
--20
--40
CH1
--60
CH2
5
3
Noise, VNO -- mVrms
Noise, VNO -- mVrms
1
7
2
CH2
0.1
7
CH1
5
3
2
100
50
VNO -- Ta
VD = 15V
RL = 8Ω
Rg = 0
A-weight
3
2
CH2
0.1
7
CH1
5
3
2
0.01
9
10.5
13.5
12
15
16.5
0.01
--50
18
fO -- VD
430
Oscillating frequency, fO -- kHz
400
CH1
340
CH2
310
280
9
10.5
12
13.5
15
16.5
Externally applied voltage, VD -- V
100
50
fO -- Ta
430
RL = 8Ω
Rg = 0
370
0
Ambient temperature, Ta -- °C
Externally applied voltage, VD -- V
Oscillating frequency, fO -- kHz
0
Ambient temperature, Ta -- °C
VNO -- VD
5
100
SVRR -- Ta
--80
--50
18
RL = 8Ω
Rg = 0
A-weight
7
50
VD = 15V
RL = 8Ω
fin = 100Hz
Rg = 0
VDr = 0dBm
DIN AUDIO
Externally applied voltage, VD -- V
1
0
Ambient temperature, Ta -- °C
Externally applied voltage, VD -- V
18
VD = 15V
RL = 8Ω
Rg = 0
400
CH1
370
340
CH2
310
280
--50
0
100
50
Ambient temperature, Ta -- °C
No.A1567-22/30
LV49157V
DUTY -- VD
CH2
50
CH1
45
9
10.5
12
13.5
DUTY -- Ta
55
DUTY -- %
DUTY -- %
55
15
16.5
CH2
50
CH1
45
--50
18
0
CHsep. -- f
--20
--40
--60
CH1®CH2
CH2®CH1
--80
--100
10
2 3
5 7 100
2 3
5 7 1k
2 3
5 7 10k
2 3
--20
--40
CH2
--80
10
5 7100k
CH1
--60
Frequency, f -- Hz
2 3
5 7 100
2 3
5 7 1k
2 3
5 7 10k
2 3
5 7100k
Ripple frequency, fr -- Hz
VNO -- Rg
1
100
SVRR -- fr
0
Ripple rejection ratio, SVRR -- dB
Channel separation, CHsep. -- dB
0
50
Ambient temperature, Ta -- °C
Externally applied voltage, VD -- V
3.0
High & Low level -- Ta
7
3
High & Low level -- V
Noise, VNO -- mVrms
5
2
CH2
0.1
CH1
7
5
3
2.5
2.0
High
1.5
Low
2
1.0
--50
0.01
1
3
5 7 100
2
3
5 7 10k
2
3
5 71000k
0
50
100
Ambient temperature, Ta -- °C
High & Low level -- Ta
9
Upper & Lower -- Ta
2.5
Upper & Lower -- V
High & Low level -- V
3.0
2
2.0
High
1.5
1.0
--50
8
Upper
7
Low
0
Lower
50
Ambient temperature, Ta -- °C
100
6
--50
0
100
50
Ambient temperature, Ta -- °C
No.A1567-23/30
THD+N -- PO
10
7
5
VD = 15V
RL = 8Ω
2ch-Drive
AES17
3
2
1
7
5
z
kH
fin
3
2
0.1
7
5
=
7
6.6
z
kH
fin
=1
0Hz
3
2
fin = 10
0.01
0.001 2 3 5 70.01 2 3 5 7 0.1 2 3 5 7 1
10
7
5
3
2
Total harmonic distortion, THD+N -- %
Total harmonic distortion, THD+N -- %
LV49157V
1
7
5
3
2
THD+N -- f
VD = 15V
RL = 8Ω
PO = 1W
2ch-Drive
AES17
CH2
0.1
7
5
3
2
CH1
0.01
7
5
3
2
0.001
2 3 5 7 10
2 3 5 7100
10
2 3
5 7 100
THD+N -- PO
10
7
5
VD = 15V
RL = 6Ω
2ch-Drive
AES17
3
2
1
7
5
Hz
7k
=
fin
6.6
3
2
fin =
0.1
7
5
3
2
0.01
0.001 2 3 5 70.01 2 3 5 7 0.1 2 3 5 7 1
kHz
1
fin =
10
7
5
3
2
z
100H
1
7
5
3
2
2 3 5 7100
Hz
k
.67
fi
2
fin =
0.1
7
5
3
z
1kH
fin =
2
0.01
0.001 2 3 5 70.01 2 3 5 70.1 2 3 5 7 1
Hz
100
2 3
5 7 100
10
7
5
3
2
1
7
5
3
2
2 3
5 7 10k
2 3
5 7100k
THD+N -- f
CH2
CH1
0.01
7
5
3
2
2 3 5 7100
10
2 3
5 7 100
30
RL = 4Ω
60
40
20
VD = 15V
fin = 1kHz
2ch-Drive
AES17
0
12
Output power, PO -- W
2 3
5 7 1k
2 3
5 7 10k
Frequency, f -- Hz
Output power, PO -- W
Efficiency -- %
5 7 1k
VD = 15V
RL = 4Ω
PO = 1W
2ch-Drive
AES17
0.1
7
5
3
2
80
8
2 3
0.001
2 3 5 7 10
RL = 8Ω
4
5 7100k
CH1
10
Efficiency -- PO
0
2 3
CH2
Output power, PO -- W
100
5 7100k
Frequency, f -- Hz
6
n=
3
2 3
0.01
7
5
3
2
Total harmonic distortion, THD+N -- %
Total harmonic distortion, THD+N -- %
2
5 7 10k
THD+N -- f
0.1
7
5
3
2
THD+N -- PO
1
7
5
2 3
0.001
2 3 5 7 10
VD = 15V
RL = 4Ω
2ch-Drive
AES17
3
5 7 1k
VD = 15V
RL = 6Ω
PO = 1W
2ch-Drive
AES17
Output power, PO -- W
10
7
5
2 3
Frequency, f -- Hz
Total harmonic distortion, THD+N -- %
Total harmonic distortion, THD+N -- %
Output power, PO -- W
16
20
PO -- VD
fin = 1kHz
THD+N = 10%
2ch-Drive
AES17
RL
=
4Ω
Ω
RL
=6
Ω
RL
20
=8
10
0
9
10.5
12
13.5
15
16.5
18
Externally applied voltage, VD -- V
No.A1567-24/30
LV49157V
Response -- f
10
Phase -- f
40
20
0
Phase -- deg
Response -- dB
0
--10
--20
--40
--20
--60
--30
10
2 3
5 7 100
2 3
5 7 1k
2 3
Frequency, f -- Hz
5 7 10k
2 3
5 7100k
--80
10
2 3
5 7 100
2 3
5 7 1k
2 3
5 7 10k
2 3
5 7100k
Frequency, f -- Hz
No.A1567-25/30
LV49157V
Glaph deta (Digital Amplifier: L = 33μH (TOKO : A7502BY-330M), C = 0.1μF, CL = 0.47μF)
ICChp -- VD
10
10
8
8
6
6
4
4
2
2
0
0
2
4
6
8
10
12
14
16
0
--50
18
HP_RF -- VD
12
10
10
HP_RF -- V
HP_RF -- V
14
12
8
6
2
2
0
4
6
8
10
12
14
16
0
--50
18
Externally applied voltage, VD -- V
HP_REF -- VD
4
4
HP_RF -- Ta
0
50
Ambient temperature, Ta -- ∞C
100
HP_REF -- Ta
3
HP_REF -- V
HP_REF -- V
3
2
1
2
1
0
0
2
4
6
8
10
12
14
16
0
--50
18
Externally applied voltage, VD -- V
HP_OUT -- VD
4
4
3
0
50
Ambient temperature, Ta -- ∞C
100
HP_OUT -- Ta
3
HP_OUT -- V
HP_OUT -- V
100
6
4
2
50
8
4
0
0
Ambient temperature, Ta -- ∞C
Externally applied voltage, VD -- V
14
ICChp -- Ta
12
ICChp -- mA
ICChp -- mA
12
2
1
2
1
0
0
2
4
6
8
10
12
14
Externally applied voltage, VD -- V
16
18
0
--50
0
50
100
Ambient temperature, Ta -- ∞C
No.A1567-26/30
LV49157V
VG -- VD
13.5
12.5
Gain, VG -- dB
Gain, VG -- dB
12.5
CH2
11.5
CH1
10.5
CH2
11.5
CH1
10.5
9.5
9
10.5
12
13.5
16.5
15
9.5
--50
18
Voffset -- VD
0.1
CH2
0
CH1
--0.1
--0.2
9
10.5
12
13.5
16.5
15
CH2
0
Total harmonic distortion, THD+N -- %
Total harmonic distortion, THD+N -- %
2
1
7
5
3
2
CH2
CH1
2
0.01
9
10.5
12
13.5
15
16.5
10
7
5
18
1
7
5
3
2
0.1
7
5
Output power, PO -- mW
THD+N = 1%
20
0
9
10.5
12
13.5
CH2
CH1
3
2
0
15
Externally applied voltage, VD -- V
16.5
18
100
50
Ambient temperature, Ta -- °C
PO -- Ta
80
THD+N = 10%
40
THD+N -- Ta
2
0.01
--50
PO -- VD
60
100
50
3
Externally applied voltage, VD -- V
80
0
Ambient temperature, Ta -- °C
3
3
CH1
--0.1
--0.2
--50
18
THD+N -- VD
0.1
7
5
100
0.1
Externally applied voltage, VD -- V
10
7
5
50
Voffset -- Ta
0.2
Offset voltage, Voffset -- mV
Offset voltage, Voffset -- mV
0.2
0
Ambient temperature, Ta -- °C
Externally applied voltage, VD -- V
Output power, PO -- mW
VG -- Ta
13.5
THD+N = 10%
60
40
THD+N = 1%
20
0
--50
0
50
100
Ambient temperature, Ta -- °C
No.A1567-27/30
LV49157V
CHsep. -- VD
0
--20
Channel separation, CHsep. -- dB
Channel separation, CHsep. -- dB
0
--40
--60
CH1 CH2
CH2 CH1
--80
--100
9
10.5
12
13.5
15
16.5
--20
--40
--60
--80
--100
--50
18
SVRR -- VD
Ripple rejection ratio, SVRR -- dB
Ripple rejection ratio, SVRR -- dB
--40
--60
CH2
CH1
--100
10.5
9
12
13.5
15
16.5
100
SVRR -- Ta
--40
--60
CH2
--80
--100
--50
18
VNO -- VD
CH1
0
50
100
Ambient temperature, Ta -- °C
VNO -- Ta
0.1
7
7
Noise, VNO -- mVrms
Noise, VNO -- mVrms
50
--20
Externally applied voltage, VD -- V
0.1
0
0
--20
--80
CH1 CH2
CH2 CH1
Ambient temperature, Ta -- °C
Externally applied voltage, VD -- V
0
CHsep. -- Ta
5
3
2
5
3
2
CH2
CH1
CH2
CH1
0.01
9
10.5
12
13.5
15
Externally applied voltage, VD -- V
16.5
18
0.01
--50
0
50
Ambient temperature, Ta -- °C
100
No.A1567-28/30
LV49157V
CHsep. -- f
--20
--40
--60
CH1®CH2
CH2®CH1
--80
--100
10
2 3
5 7 100
2 3
5 7 1k
2 3
SVRR -- fr
0
Ripple rejection ratio, SVRR -- dB
Channel separation, CHsep. -- dB
0
5 7 10k
2 3
--20
--40
--60
CH1
--100
10
5 7100k
CH2
--80
2 3
Frequency, f -- Hz
2 3
5 7 1k
2 3
5 7 10k
2 3
5 7100k
Ripple frequency, fr -- Hz
VNO -- Rg
0.1
5 7 100
High & Low level -- Ta
3.0
5
3
2
CH2
High & Low level -- V
Noise, VNO -- mVrms
7
2.5
2.0
High
1.5
Low
CH1
5 70.01
2 3
5 70.01
2 3
5 70.01
2 3
Total harmonic distortion, THD+N -- %
Hz
3
2
1
7
5
fin
3
=1
0k
2
Hz
0.1
7
5
fin = 1kHz
3
2
2 3
5 7 0.1
2 3
5 7 1
2 3
5 7 10
2 3
5 7100
Output power, PO -- mW
4
0
100
50
Ambient temperature, Ta -- °C
THD+N -- PO
10
7
5
0.01
0.01
1.0
--50
5 710000
fin = 100
Total harmonic distortion, THD+N -- %
0.01
0.0001 2 3
THD+N -- f
10
7
5
3
2
1
7
5
3
2
CH2
0.1
7
5
CH1
3
2
0.01
10
2 3
5 7 100
2 3
5 7 1k
2 3
5 7 10k
2 3
5 7100k
Frequency, f -- Hz
Response -- f
Response -- dB
2
0
--2
--4
--6
--8
0.01 2 3 5 70.1
2 3 571
2 3 5 7 10
2 3 5 7100 2 3 5 71000
Frequency, f -- kHz
No.A1567-29/30
LV49157V
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of November, 2009. Specifications and information herein are subject
to change without notice.
PS No.A1567-30/30