Ordering number : ENA0691 Bi-CMOS LSI LV5608LP For CCD Charge pump power supply Overview The LV5608LP is charge pump power supply for CCD. Functions • The charge pump boosts the +3.3V input by multiplying with +6, then by -3 to regulate the voltage to the specified level. • The output voltage is +15V, -7.5V necessary for CCD. • Soft start function incorporated, which reduces the inrush current at start of charge pump. • Short-circuit protection function incorporated. • Four types of operating frequency selectable. Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Allowable power dissipation Symbol Conditions Ratings Unit VDD max Pd max 3.5 with specified substrate *1 V 0.8 W Operating temperature Topr -20 to +80 °C Storage temperature Tstg -40 to +125 °C *1 : Specified substrate : 40×50×0.8mm3, glass epoxy four-layer (2S2P) board Allowable Operating Ratings at Ta = 25°C, PGND = 0V Parameter Symbol Ratings Conditions min Supply voltage VDD Input CLK frequency CKIN SEL=H *2 Input High voltage VINH Input Low voltage VINL typ 3.0 Unit max 3.3 3.45 V 0.1 8 MHz EN pin 0.7VDD VDD V EN pin -0.1 0.4 V *2 : Note that the charge pump frequency should be adjusted with S0/S1 so that it becomes 2 MHz or less. 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SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. 32207 MS PC 20060728-S00004 No.A0691-1/8 LV5608LP Electrical Characteristics at Ta = 25°C, VDD = 3.3V, SGND = 0V, PGND = 0V,IH=20mA, IL=5mA, S0=H, S1=L, Unless otherwise specified Parameter Symbol Ratings Conditions min Circuit current dissipation IDD1 EN = L 15 30 μA EN = H no load 17 25 mA 20 mA IH ave VDD = 3.0V VL output load current IL ave VDD = 3.0V Reference voltage VREF VDD = 3.0 to 3.45V, design guarantee -8 V 15 15.35 -7.65 -7.5 -7.25 After capacitive discharge -50 0 50 VLoff → VHoff 4.5 5.6 7.5 ms 12 18 32 ms 20 30 mV 10 55 mV 17.5 22.5 μA Tmask ΔVH VL load regulation ΔVL Load 1mA → 20mA Load 0.5mA → 8mA Iin VH monitoring voltage V 14.55 VH load regulation Input pin current 1.37 VL Toff Protection circuit masking time V 1.239 VH VOFF VH holding time mA 1.305 Ta = -20°C to +80°C, design guarantee Output voltage at OFF max IDD2 VH output load current Output voltage accuracy Unit typ Pins EN, S0, S1, SEL and CLK 12.6 VTvlon Power efficiency Peff Inrush current Irush Oscillation frequency f clk V mV 10 CP+Regulator (VH+VL) V 70 1.5 % 2 600 mA 2.5 MHz Note : The design specification items are design guarantees and are not measured. Package Dimensions unit : mm (typ) 3322 SIDE VIEW TOP VIEW BOTTOM VIEW 13 18 12 19 3.5 (C0.116) (0.13) (0.125) 3.5 0.4 7 24 6 1 0.5 (0.5) 0.25 (0.035) 0.83 SIDE VIEW Allowable power dissipation, Pd max – W 1.0 Pd max – Ta Specified circuit board : 40×50×0.8mm3, glass epoxy four-layer (2S2P) board With specified substrate 0.8 0.6 0.4 0.2 0.15 0.36 Independent IC 0.07 0 – 20 SANYO : VCT24(3.5X3.5)X01 0 20 40 60 80 100 Ambient temperature, Ta – °C No.A0691-2/8 LV5608LP TEST VL C33 VL C32 C31A PGND1 C31B Pin Assignment 24 23 22 21 20 19 17 C12A EN 3 16 C11A SGND 4 15 PVDD SVDD 5 14 C12B CLK 6 13 PGND 8 9 10 11 12 C11B 7 NC 2 C21A S1 VH C22 18 VM C13 VH C23 1 SEL S0 Top view Pin Function Pin No. Name Mode 1 S0 Charge pump frequency changeover pin 2 S1 Charge pump frequency changeover pin 3 EN System enable pin (Hi active) 4 SGND Small signal system GND pin 5 SVDD Small signal system VDD pin 6 CLK External CLK input pin 7 SEL CLK selector pin (L: built-in CLK, H: external CLK) 8 VH C23 VH (+15V) regulator output pin 9 VH C22 Boost voltage output (+6VDD) 10 C21A 11 NC 12 C11B Boost capacitor connection pin (driver side) 13 PGND +3-fold boost power GND pin 14 C12B Boost capacitor connection pin (driver side) 15 PVDD Power system VDD pin 16 C11A Boost capacitor connection pin (load transfer side) 17 C12A Boost capacitor connection pin (load transfer side) 18 VM C13 19 C31B 20 PGND1 21 C31A 22 VL C32 Boost voltage output (-3VDD) 23 VL C33 VL (-7.5V) regulator output pin 24 TEST Boost capacitor connection pin (on the load transfer side) Boost voltage output (+3VDD) +2-fold and -1-fold boost capacitor connection pin (driver side) +2-fold and -1-fold boost power GND pin -1-fold boost capacitor connection pin (load transfer side) Test pin (OPEN or GND short-circuited) No.A0691-3/8 LV5608LP Block Diagram 10μF /VDD VDD 3.3V 15 14 SVDD 5 +3 times step up circuit 1μF /VDD 4 TSD PGND PGND1 To A bandgap voltage reference 12 16 C12B C11B 1μF /VDD 1μF /2VDD C11A 17 +3VDD 20 C12A 2.2μF /3VDD 18 VM C13 A C31B 19 0.22μF /3VDD C31A 1μF /3VDD PGND 13 PVDD VL C32 VL C33 21 22 23 1μF -1 times step up circuit -3VDD VL Reg +2 times step up circuit timing generator +6VDD sequence generator VH Reg 10 9 1μF /3VDD C21A 2.2μF /6VDD VH C22 2.2μF 8 VH C23 VH=+15V VL=-7.5V 2bitMUX 1 S0 EN 3 2 S1 2MHz oscillator divider TEST 24 MUX 6 7 SEL Lo : internal CLK Hi : external CLK CLK No.A0691-4/8 LV5608LP Short-circuit Protection VH and VL output pins incorporate the short-circuit protection function. When the output pins are short-circuited to allow the large current to flow, IC is latched OFF to interrupt output. To reset from the interrupted state, set the EN pin to L, then reset it again to H. Frequency Selection The charge pump operating frequency can be changed with S0 and S1 logics. For light load, the reactive load can be reduced by lowering the operating frequency. SEL logic also enables synchronous operation with external CLK. The charge pump is operated with the frequency equivalent to 1/2 of input CLK. (The IC internal oscillator is used for the sequence, so that it is normally ON regardless of SEL. S0 S1 CP operating frequency SEL=L For minimum 9.4ms after startup with the EN signal set to H, the IC internal clock is used to operate the charge pump with 1 MHz regardless of the input of SEL, S0, and S1 pins. After the 9.4ms(min) period, the charge pump frequency is changed over according to the state of SEL, S0, and S1 pins. The changeover frequency is set as shown in the table right. SEL=H L L 1MHz 1/2 CLK H L 500kHz 1/4 CLK L H 250kHz 1/8 CLK H H 125kHz 1/16 CLK SEL L IC internal oscillator H Synchronous operation with external CLK Internal Equivalent Circuit S0 pin S1 pin SEL pin D CLK pin clk clk/2 clk/4 clk/8 Q D B Y A 2-input multiplexer VH regulator start signal L H in 9.4 ms (min) after EN = H Charge pump clock 4-input multiplexer Q Internal 1MHz Y Q Q D Q Q D Q Q Truth Table S0 S1 L L L H L H H H Y clk clk/2 clk/4 clk/8 Truth Table SEL Y L A H B External signal input pin Internal signal No.A0691-5/8 LV5608LP External clock signal startup sequence Set EN = H by setting V DD at 3 V or more. V Stop at EN = L or over-current protection Never set V DD at 3 V or less till the sequence is over (7.5 ms after EN = L). DD EN Charge pump (C23) Regulator (C22) S0 Frequency selection Do not attempt change the signal after 9.4 ms from EN = H. Frequency selection Do not attempt change the signal after 9.4 ms from EN = H. Frequency selection S1 Frequency selection Do not attempt change the signal after 9.4 ms from EN = H. Frequency selection Do not attempt change the signal after 9.4 ms from EN = H. Frequency selection SEL External clock selected Do not attempt change the signal after 9.4 ms from EN = H. External clock selected Do not attempt change the signal after 9.4 ms from EN = H. External clock selected * Internal 1 MHz SEL=L (Internal clock) * CP clock 1MHz * CP clock 500kHz * CP clock 250kHz * CP clock 125kHz CLK SEL=H (External clock) * CP clock 1/2φ * CP clock 1/4φ * CP clock 1/8φ * CP clock 1/16φ * IC internal signal Internal clock started at 1 MHz 9.4ms(min) Steady operation Internal clock Stop started at 1 MHz sequence 9.4ms(min) 7.5ms(max) Steady operation Stop sequence 7.5ms(max) EN Pin and VDD Though the sequence operation is made at startup, startup is not effectuated if the internal circuit has not been reset. To reset the internal circuit, it is necessary to keep the EN pin at L till VDD becomes 3V or more. Note that operation with VDD and EN pin short-circuited cannot be made. Since the sequence operation is incorporated for stop of operation, the charge pump remains active till 7.5ms (max) passes after setting the EN pin to L. During this period, VDD must be kept at 3V or more to allow the internal sequence logic to operate correctly. No.A0691-6/8 LV5608LP Rise/fall Sequence EN mA MAX IDD 0 VREF +6VDD +3VDD Charge pump output -3VDD VH VTvlon REG output VL 5.5ms 2ms 2ms 3.3ms 6.1ms* Toff 18.9ms *The VL startup time at VH ≥ 10V and after elapse of 6.1ms is the reference time for CLK = 2MHz. No.A0691-7/8 LV5608LP Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. 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Specifications and information herein are subject to change without notice. PS No.A0691-8/8