SEMTECH SC1485_05

SC1485
Dual Synchronous Buck Pseudo Fixed
Frequency Power Supply Controller
POWER MANAGEMENT
Description
Features
The SC1485 is a dual output constant-on synchronous
buck PWM controller intended for use in notebook
computers and other battery operated portable devices.
Features include high efficiency and a fast dynamic
response with no minimum on time. The excellent
transient response means that SC1485 based solutions
will require less output capacitance than competing fixed
frequency converters.
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The switching frequency is constant until a step in load
or line voltage occurs at which time the pulse density
and frequency will increase or decrease to counter the
change in output or input voltage. After the transient
event, the controller frequency will return to steady state
operation. At light loads, Power-Save Mode enables the
SC1485 to skip PWM pulses for better efficiency.
Each output voltage can be independently adjusted from
0.5V to VCCA. Two frequency setting resistors set the
on-time for each buck controller. The frequency can thus
be tailored to minimize crosstalk. The integrated gate
drivers feature adaptive shoot-through protection and
soft switching. Additional features include cycle-by-cycle
current limit, digital soft-start, over-voltage and undervoltage protection, and a PGOOD output for each
controller.
VBAT
Constant on-time for fast dynamic response
Programmable VOUT range = 0.5 – VCCA
VBAT Range = 1.8V – 25V
DC current sense using low-side RDS(ON) sensing
or sense resistor
Resistor programmable frequency
Cycle-by-cycle current limit
Digital soft-start
Separate PSAVE option for each switcher
Over-voltage/Under-voltage fault protection
10µA typical shutdown current
Low quiescent power dissipation
Two Power Good indicators
1% Reference (2% system DC accuracy)
Integrated gate drivers with soft switching
Separate enables
28 Lead TSSOP
Industrial temperature range
Applications
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5VSUS
Notebook computers
CPU I/O supplies
Handheld terminals and PDAs
LCD monitors
Network power supplies
5VSUS
VBAT
D1
R1
R2
U1
22
RTON1
10R
23
VOUT1
24
EN/PSV1
TON1
SC1485
BST1
DH1
VOUT1
LX1
VCCA1
ILIM1
C1
0.1uF
7
Q1
6
C2
10uF
5
L1
R3
R4
25
VOUT1
4
C3
R5
+
26
27
PGOOD
FB1
PGD1
VDDP1
DL1
3
Q2
R6
0R
2
VSSA1
C4
R7
28
C5
C6
1nF
VSSA1
PGND1
1
1uF
1uF
VSSA1
VBAT
5VSUS
VBAT
5VSUS
D2
R8
R9
C7
8
RTON2
10R
9
VOUT2
10
EN/PSV2
TON2
BST2
DH2
VOUT2
LX2
VCCA2
ILIM2
0.1uF
21
Q3
20
C8
10uF
19
L2
R10
R11
11
VOUT2
18
C9
R12
+
12
13
PGOOD
FB2
PGD2
VDDP2
DL2
17
Q4
R13 0R
16
VSSA2
C10
R14
14
C11
C12
1nF
1uF
VSSA2
PGND2
15
1uF
VSSA2
Revision: April 26, 2005
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SC1485
POWER MANAGEMENT
Absolute Maximum Ratings(1)
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may
affect device reliability.
Parameter
Symbol
Maximum
Units
TONn to VSSAn
-0.3 to +25.0
V
DHn, BSTn to PGNDn
-0.3 to +30.0
V
LXn to PGNDn
-2.0 to +25.0
V
PGNDn to VSSAn
-0.3 to +0.3
V
BSTn to LXn
-0.3 to +6.0
V
DLn, ILIMn, VDDPn to PGNDn
-0.3 to +6.0
V
EN/PSVn, FBn, PGDn, VCCAn, VOUTn to VSSAn
-0.3 to +6.0
V
VCCAn to EN/PSVn, FBn, PGDn, VOUTn
-0.3 to +6.0
V
Thermal Resistance Junction to Ambient (2)
θJA
84
°C/W
Operating Junction Temperature Range
TJ
-40 to +125
°C
Storage Temperature Range
TSTG
-65 to +150
°C
Lead Temperature (Soldering) 10 Sec.
TLEAD
300
°C
Notes:
(1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
(2) Measured in accordance with JESD51-1, JESD51-2 and JESD51-7.
Electrical Characteristics
Test Conditions: VBAT = 15V, EN/PSV1=EN/PSV2 = 5V, VCCA1 = VDDP1 = VCCA2 = VDDP2 = 5V, VOUT1 = VOUT2 =1.25V, RTON1 = RTON2 = 1MΩ
Parameter
Conditions
25°C
Min
Typ
-40°C to 125°C
Max
Min
Max
Units
Input Supplies
V C C A 1, V C C A 2
5.0
4.5
5.5
V
V D D P 1, V D D P 2
5.0
4.5
5.5
V
VBAT Voltage
Offtime > 800ns
1.8
25
V
VDDP1, VDDP2 Operating Current FB > regulation point, ILOAD = 0A
70
150
µA
VCCA1, VCCA2 Operating Current FB > regulation point, ILOAD = 0A
700
1100
µA
TON1, TON2 Operating Current
RTON = 1M
15
Shutdown Current
EN/PSV1, EN/PSV2 = 0V
-5
-10
µA
V C C A 1, V C C A 2
5
10
µA
VDDP1, TON1, VDDP2, TON2
0
1
µA
 2005 Semtech Corp.
2
µA
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SC1485
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Test Conditions: VBAT = 15V, EN/PSV1=EN/PSV2 = 5V, VCCA1 = VDDP1 = VCCA2 = VDDP2 = 5V, VOUT1 = VOUT2 =1.25V, RTON1 = RTON2 = 1MΩ
Parameter
Conditions
25°C
Min
Typ
-40°C to 125°C
Max
Units
Min
Max
-1%
+1%
V
0.5
VC C A
V
ns
Controller
Error Comparator Threshold
(FB turn-on threshold)(1)
VCCA = 4.5V to 5.5V
0.500
Output Voltage Range
On-Time, VBAT = 2.5V
RTON = 1MΩ
1761
1497
2025
RTON = 500kΩ
936
796
1076
Minimum Off Time
400
VOUT1, VOUT2 Input Resistance
500
FB1, FB2 Input Bias Current
550
ns
kΩ
-1.0
+1.0
µA
9
11
µA
-10
10
mV
Over-Current Sensing
ILIM Source Current
DL high
Current Comparator Offset
PGND - ILIM
10
PSAVE
Zero-Crossing Threshold
(PGND - LX), EN/PSV = 5V
5
mV
(PGND - LX), RILIM = 5kΩ
50
35
65
mV
(PGND - LX), RILIM = 10kΩ
100
80
120
mV
(PGND - LX), RILIM = 20kΩ
200
170
230
mV
Current Limit (Negative)
(PGND - LX)
-140
-200
-100
mV
Output Under-Voltage Fault
With respect to internal ref.
-30
-40
-25
%
Output Over-Voltage Fault
With respect to internal ref.
+10
+8
+12
%
Over-Voltage Fault Delay
FB forced above OV Threshold
PGD Low Output Voltage
Sink 1mA
PGD Leakage Current
FB in regulation, PGD = 5V
PGD UV Threshold
With respect to internal ref.
Fault Protection
Current Limit (Positive) (2)
 2005 Semtech Corp.
3
5
-10
µs
-12
0.4
V
1
µA
-8
%
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SC1485
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Test Conditions: VBAT = 15V, EN/PSV1=EN/PSV2 = 5V, VCCA1 = VDDP1 = VCCA2 = VDDP2 = 5V, VOUT1 = VOUT2 =1.25V, RTON1 = RTON2 = 1MΩ
Parameter
Conditions
25°C
Min
Typ
-40°C to 125°C
Max
Min
Units
Max
Fault Protection (Cont.)
PGD Fault Delay
FB forced outside PGD window
5
VCCA Undervoltage Threshold
Falling (100mV Hysteresis )
4.0
Over Temperature Lockout
10°C Hysteresis
165
µs
3.7
4.3
V
°C
Inputs/Outputs
Logic Input Low Voltage
EN/PSV low
1.2
Logic Input High Voltage
EN High, PSV low (Floating)
Logic Input High Voltage
EN/PSV high
EN/PSV Input Resistance
R Pullup to VCCA
1.5
R Pulldown to VSSA
1.0
Soft-Start Ramp Time
EN/PSV high to PGD high
440
clks(3)
Under-Voltage Blank Time
EN/PSV high to UV high
440
clks(3)
ns
2.0
V
V
3.1
V
MΩ
Soft Start
Gate Drivers
Shoot-Through Delay (4)
DH or DL rising
30
DL Pull-Down Resistance
DL low
0.8
DL Sink Current
DL = 2.5V
3.1
DL Pull-Up Resistance
DL high
DL Source Current
DL = 2.5V
DH Pull-Down Resistance
DH low, BST - LX = 5V
2
4
Ω
DH Pull-Up Resistance(5)
DH high, BST - LX = 5V
2
4
Ω
DH Sink/Source Current
DH = 2.5V
2
1.6
A
4
1.3
1.3
Ω
Ω
A
A
Notes:
(1) When the inductor is in continuous and discontinuous conduction mode, the output voltage will have a DC
regulation level higher than the error-comparator threshold by 50% of the ripple voltage.
(2) Using a current sense resistor, this measurement relates to PGND minus the voltage of the source on the lowside MOSFET. These values guaranteed by the ILIM Source Current and Current Comparator Offset tests.
(3) clks = Switching cycles.
(4) Guaranteed by design. See Shoot-Through Delay Timing Diagram on Page 6.
(5) Semtech’s SmartDriverTM FET drive first pulls DH high with a pullup resistance of 10Ω (typ.) until LX = 1.5V (typ.).
At this point, an additional pullup device is activated, reducing the resistance to 2Ω (typ.). This negates the need for
an external gate or boost resistor.
 2005 Semtech Corp.
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SC1485
POWER MANAGEMENT
Pin Configuration
Ordering Information
Device
Package(1)
SC1485ITSTR
TSSOP-28
SC1485ITSTRT(2)
TSSOP-28
Notes:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
(2) Lead free product. This product is fully WEEE, RoHS
and J-STD-020B compliant.
TSSOP-28
Pin Descriptions
Pin #
Pin Name
Pin Function
1
PGND1
Power ground.
2
D L1
3
VD D P1
+5V supply voltage input for the gate drivers. Decouple this pin with a 1uF ceramic capacitor to
PGND1.
4
ILIM1
Current limit input. Connect to drain of low-side MOSFET for RDS(on) sensing or the source for
resistor sensing through a threshold sensing resistor.
5
LX 1
Phase node (junction of top and bottom MOSFETs and the output inductor) connection.
6
DH1
Gate drive output for the high side MOSFET switch.
7
BST1
Boost capacitor connection for the high side gate drive.
8
EN/PSV2
Enable/Power Save input. Pull down to VSSA2 to shut down OUT2. Pull up to enable OUT2 and
activate PSAVE mode. Float to enable OUT2 and activate continuous conduction mode (CCM). If
floated, bypass to VSSA2 with a 10nF ceramic capacitor.
9
TON2
This pin is used to sense VBAT through a pullup resistor, RTON2, and to set the top MOSFET ontime. Bypass this pin with a 1nF ceramic capacitor to VSSA2.
10
VOUT2
Output voltage sense input for output 2. Connect to the output at the load.
11
VC C A2
Supply voltage input for the analog supply. Use a 10 Ohm / 1µF RC filter from 5VSUS to VSSA2.
12
FB 2
Feedback input. Connect to a resistor divider located at the IC from VOUT2 to VSSA2 to set the
output voltage from 0.5V to VCCA2.
13
PGD2
Power Good open drain NMOS output. Goes high after a fixed clock cycle delay (440 cycles)
following power up.
14
VSSA2
Ground reference for analog circuitry. Connect to PGND2 at the bottom of the output capacitor.
 2005 Semtech Corp.
Gate drive output for the low side MOSFET switch.
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SC1485
POWER MANAGEMENT
Pin Descriptions (Cont.)
Pin#
Pin Name
Pin Function
15
PGND2
Power ground.
16
D L2
17
VD D P2
+5V supply voltage input for the gate drivers. Decouple this pin with a 1uF ceramic capacitor to
PGND2.
18
ILIM2
Current limit input. Connect to drain of low-side MOSFET for RDS(on) sensing or the source for
resistor sensing through a threshold sensing resistor.
19
LX 2
Phase node (junction of top and bottom MOSFETs and the output inductor) connection.
20
DH2
Gate drive output for the high side MOSFET switch.
21
BST2
Boost capacitor connection for the high side gate drive.
22
EN/PSV1
Enable/Power Save input. Pull down to VSSA1 to shut down OUT1. Pull up to enable OUT1 and
activate PSAVE mode. Float to enable OUT1 and activate continuous conduction mode (CCM). If
floated, bypass to VSSA1 with a 10nF ceramic capacitor.
23
TON1
This pin is used to sense VBAT through a pullup resistor, RTON1, and to set the top MOSFET ontime. Bypass this pin with a 1nF ceramic capacitor to VSSA1.
24
VOUT1
Output voltage sense input for output 1. Connect to the output at the load.
25
VC C A1
Supply voltage input for the analog supply. Use a 10 Ohm / 1µF RC filter from 5VSUS to VSSA1.
26
FB 1
Feedback input. Connect to a resistor divider located at the IC from VOUT1 to VSSA1 to set the
output voltage from 0.5V to VCCA1.
27
PGD1
Power Good open drain NMOS output. Goes high after a fixed clock cycle delay (440 cycles)
following power up.
28
VSSA1
Ground reference for analog circuitry. Connect to PGND1 at the bottom of the output capacitor.
Gate drive output for the low side MOSFET switch.
Shoot-Through Delay Timing Diagram
LX
DH
DL
DL
tplhDL
 2005 Semtech Corp.
tplhDH
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SC1485
POWER MANAGEMENT
Block Diagram
VCCA1 (25)
EN/SPV1 (22)
POR / SS
OT
BST1 (7)
TON1 (23)
ON
TON
VOUT1 (24)
OFF
PWM
CONTROL
LOGIC
HI
DH1 (6)
LX1 (5)
TOFF
OC
1.5V REF
ISENSE
ZERO I
+
FB1 (26)
ILIM1 (4)
VDDP1 (3)
X3
LO
PGD1 (27)
DL1 (2)
PGND1 (1)
OV
FAULT
MONITOR
VSSA1 (28)
UV
REF + 10%
REF - 10%
REF - 30%
VCCA2 (11)
EN/SPV2 (8)
TON2 (9)
POR / SS
OT
BST2 (21)
ON
TON
VOUT2 (10)
OFF
PWM
CONTROL
LOGIC
HI
DH2 (20)
LX2 (19)
TOFF
OC
1.5V REF
ZERO I
+
ISENSE
FB2 (12)
ILIM2 (18)
VDDP2 (17)
X3
LO
PGD2 (13)
DL2 (16)
PGND2 (15)
OV
VSSA2 (14)
FAULT
MONITOR
UV
REF + 10%
REF - 10%
REF - 30%
FIGURE 1.
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SC1485
POWER MANAGEMENT
Applications Information
+5V Bias Supplies
This input voltage-proportional current is used to charge
an internal on-time capacitor. The on-time is the time
required for the voltage on this capacitor to charge from
zero volts to VOUT, thereby making the on-time of the
high-side switch directly proportional to output voltage
and inversely proportional to input voltage. This
implementation results in a nearly constant switching
frequency without the need for a clock generator.
For VOUT < 3.3V:
The SC1485 requires an external +5V bias supply in
addition to the battery. If stand-alone capability is
required, the +5V supply can be generated with an
external linear regulator such as the Semtech LP2951.
To avoid interference between outputs, each controller
has its own ground reference, VSSA, which should be
tied by a single trace to PGND at the negative terminal of
that controller’s output capacitor (see Layout Guidelines).
All external components referenced to VSSA in the
schematic should be connected to the appropriate VSSA
trace. The supply decoupling capacitor for controller 1
should be tied between VCCA1 and VSSA1. Likewise, the
supply decoupling capacitor for controller 2 should be
tied between VCCA2 and VSSA2. A 10Ω resistor should
be used to decouple each VCCA supply from the main
VDDP supplies. PGND can then be a separate plane which
is not used for routing traces. All PGND connections are
connected directly to the ground plane with special
attention given to avoiding indirect connections which
may create ground loops. As mentioned above, VSSA1
and VSSA2 must be connected to the PGND plane at
the negative terminal of their respective output
capacitors only. The VDDP1 and VDDP2 inputs provide
power to the upper and lower gate drivers. A decoupling
capacitor for each supply is required. No series resistor
between VDDP and 5V is required. See layout guidelines
for more details.
V 
t ON = 3.3 x10 −12 • (R TON + 37 x10 3 ) •  OUT  + 50ns
 VBAT 
For 3.3V ≤ VOUT ≤ 5V:
V 
t ON = 0.85 • 3.3 x10 −12 • (R TON + 37 x10 3 ) •  OUT  + 50ns
 VBAT 
RTON is a resistor connected from the input supply (VBAT)
to the TON pin. Due to the high impedance of this
resistor, the TON pin should always be bypassed to VSSA
using a 1nF ceramic capacitor.
Enable and Powersave
The EN/PSV pin enables the supply. When EN/PSV is
tied to VCCA the controller is enabled and power save
will also be enabled. If PSAVE is enabled, the SC1485
PSAVE comparator will look for the inductor current to
cross zero on eight consecutive switching cycles by
comparing the phase node (LX) to PGND. Once observed,
the controller will enter power save and turn off the low
side MOSFET when the current crosses zero. To improve
light-load efficiency and add hysteresis, the on-time is
increased by 50% in power save. The efficiency
improvement at light-loads more than offsets the
disadvantage of slightly higher output ripple. If the
inductor current does not cross zero on any switching
cycle, the controller will immediately exit power save. Since
the controller counts zero crossings, the converter can
sink current as long as the current does not cross zero
on eight consecutive cycles. This allows the output
voltage to recover quickly in response to negative load
steps even when psave is enabled.
Pseudo-fixed Frequency Constant On-Time PWM
Controller
The PWM control architecture consists of a constant ontime, pseudo fixed frequency PWM controller (see Figure
1, SC1485 Block Diagram). The output ripple voltage
developed across the output filter capacitor’s ESR
provides the PWM ramp signal eliminating the need for a
current sense resistor. The high-side switch on-time is
determined by a one-shot whose period is directly
proportional to output voltage and inversely proportional
to input voltage. A second one-shot sets the minimum
off-time which is typically 400ns.
When the EN/PSV pin is tri-stated, an internal pull-up
will activate the controller and power save will be disabled.
On-Time One-Shot (tON)
The on-time one-shot comparator has two inputs. One
input looks at the output voltage, while the other input
samples the input voltage and converts it to a current.
 2005 Semtech Corp.
If the EN/PSV pin is pulled low, the related output will be
shut down and tri-stated.
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SC1485
POWER MANAGEMENT
Output Voltage Selection
In an extreme over-current situation, the top MOSFET
will never turn back on and eventually the part will latch
off due to output undervoltage (see Output Undervoltage
Protection).
The output voltage (OUT2 shown) is set by the feedback
resistors R9 & R13 of Figure 2 below. The internal
reference is 1.5V, so the voltage at the feedback pin is
multiplied by three to match the 1.5V reference.
Therefore the output can be set to a minimum of 0.5V.
The equation for setting the output voltage is:
The current sensing circuit actually regulates the
inductor valley current (see Figure 3). This means that if
the current limit is set to 10A, the peak current through
the inductor would be 10A plus the peak-to-peak ripple
current, and the average current through the inductor
would be 10A plus 1/2 the peak-to-peak ripple current.
The equations for setting the valley current and
calculating the average current through the inductor are
shown below:
R9 

VOUT = 1 +
 • 0.5
R
13 

9
C15
56p
0402
VOUT2
VOUT
10
R9
20k0
0402
11
12
13
R13
20k0
0402
14
EN/PSV2
TON2
BST2
DH2
VOUT2
LX2
VCCA2
ILIM2
FB2
VDDP2
PGD2
VSSA2
U1
DL2
PGND2
21
20
19
18
IPEAK
INDUCTOR CURRENT
8
17
16
15
SC1485 OUT2
ILOAD
ILIMIT
VSSA2
TIME
Valley Current-Limit Threshold Point
Figure 2: Setting The Output Voltage
Current Limit Circuit
Figure 3: Valley Current Limiting
Current limiting of the SC1485 can be accomplished in
two ways. The on-state resistance of the low-side MOSFET
can be used as the current sensing element or sense
resistors in series with the low-side source can be used
if greater accuracy is desired. RDS(ON) sensing is more
efficient and less expensive. In both cases, the RILIM
resistor between the ILIM pin and LX pin sets the over
current threshold. This resistor RILIM is connected to a
10µA current source within the SC1485 which is turned
on when the low side MOSFET turns on. When the
voltage drop across the sense resistor or low side
MOSFET equals the voltage across the RILIM resistor,
positive current limit will activate. The high side MOSFET
will not be turned on until the voltage drop across the
sense element (resistor or MOSFET) falls below the
voltage across the RILIM resistor.
 2005 Semtech Corp.
The equation for the current limit threshold is as follows:
ILIMIT = 10e -6 •
RILIM
A
R SENSE
Where (referring to Figure 8 on Page 16) RILIM is R10 and
RSENSE is the RDS(ON) of Q4.
For resistor sensing, a sense resistor is placed between
the source of Q4 and PGND. The current through the
source sense resistor develops a voltage that opposes
the voltage developed across RILIM. When the voltage
developed across the RSENSE resistor reaches the voltage
drop across RILIM, a positive over-current exists and the
high side MOSFET will not be allowed to turn on. When
using an external sense resistor RSENSE is the resistance
of the sense resistor.
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SC1485
POWER MANAGEMENT
The current limit circuitry also protects against negative
over-current (i.e. when the current is flowing from the
load to PGND through the inductor and bottom MOSFET).
In this case, when the bottom MOSFET is turned on, the
phase node, LX, will be higher than PGND initially. The
SC1485 monitors the voltage at LX, and if it is greater
than a set threshold voltage of 125mV (nom.) the
bottom MOSFET is turned off. The device then waits for
approximately 2.5µs and then DL goes high for 300ns
(typ.) once more to sense the current. This repeats until
either the over-current condition goes away or the part
latches off due to output overvoltage (see Output
Overvoltage Protection).
Switching always starts with DL to charge up the BST
capacitor. With the softstart circuit (automatically)
enabled, it will progressively limit the output current (by
limiting the current out of the ILIM pin) over a
predetermined time period of 440 switching cycles.
The ramp occurs in four steps:
1) 110 cycles at 25% ILIM with double minimum off-time
(for purposes of the on-time one-shot, there is an
internal positive offset of 120mV to VOUT during this
period to aid in startup)
2) 110 cycles at 50% ILIM with normal minimum off-time
3) 110 cycles at 75% ILIM with normal minimum off-time
4) 110 cycles at 100% ILIM with normal minimum
off-time.
At this point the output undervoltage and power good
circuitry is enabled. There is 100mV of hysteresis built
into the UVLO circuit and when VCCA falls to 4.1V (nom.)
the output drivers are shut down and tristated.
Power Good Output
The power good output is an open-drain output and
requires a pull-up resistor. When the output voltage is
10% above or below its set voltage, PGD gets pulled low.
It is held low until the output voltage returns to within
these tolerances once more. PGD is also held low during
start-up and will not be allowed to transition high until
soft start is over (440 switching cycles) and the output
reaches 90% of its set voltage. There is a 5µs delay built
into the PGD circuitry to prevent false transitions.
MOSFET Gate Drivers
The DH and DL drivers are optimized for driving
moderate-sized high-side, and larger low-side power
MOSFETs. An adaptive dead-time circuit monitors the DL
output and prevents the high-side MOSFET from turning
on until DL is fully off (below ~1V). Semtech’s
SmartDriver™ FET drive first pulls DH high with a pull-up
resistance of 10Ω (typ.) until LX = 1.5V (typ.). At this
point, an additional pull-up device is activated, reducing
the resistance to 2Ω (typ.). This negates the need for an
external gate or boost resistor. The adaptive dead-time
circuit also monitors the phase node, LX, to determine
the state of the high side MOSFET, and prevents the lowside MOSFET from turning on until DH is fully off (LX
below ~1V). Be sure to have low resistance and low
inductance between the DH and DL outputs to the gate
of each MOSFET.
Output Overvoltage Protection
When the output exceeds 10% of its set voltage the
low-side MOSFET is latched on. It stays latched on and
the controller is latched off until reset (see below). There
is a 5µs delay built into the OV protection circuit to
prevent false transitions.
Output Undervoltage Protection
When the output is 30% below its set voltage the output
is latched in a tri-stated condition. It stays latched and
the controller is latched off until reset (see below). There
is a 5µs delay built into the UV protection circuit to
prevent false transitions. Note: to reset from any fault,
VCCA or EN/PSV must be toggled.
Dropout Performance
The output voltage adjust range for continuousconduction operation is limited by the fixed 550ns
(maximum) minimum off-time one-shot. For best dropout
performance, use the slowest on-time setting of 200kHz.
When working with low input voltages, the duty-factor
limit must be calculated using worst-case values for on
and off times. The IC duty-factor limitation is given by:
POR, UVLO and Softstart
An internal power-on reset (POR) occurs when VCCA
exceeds 3V, starting up the internal biasing. VCCA
undervoltage lockout (UVLO) circuitry inhibits the
controller until VCCA rises above 4.2V. At this time the
UVLO circuitry resets the fault latch and soft start counter,
and allows switching to occur if the device is enabled.
 2005 Semtech Corp.
DUTY =
10
t ON( MIN )
t ON( MIN )
+ t OFF(MAX )
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SC1485
POWER MANAGEMENT
The maximum input voltage (VBAT(MAX)) is determined by
the highest AC adaptor voltage. The minimum input
voltage (V BAT(MIN)) is determined by the lowest battery
voltage after accounting for voltage drops due to
connectors, fuses and battery selector switches. For the
purposes of this design example we will use a VBAT range
of 8V to 20V and design OUT2. The design for OUT1
employs the same technique.
Be sure to include inductor resistance and MOSFET onstate voltage drops when performing worst-case dropout
duty-factor calculations.
SC1485 System DC Accuracy
Two IC parameters affect system DC accuracy, the error
comparator threshold voltage variation and the
switching frequency variation with line and load. The
error comparator threshold does not drift significantly
with supply and temperature. Thus, the error
comparator contributes 1% or less to DC system
inaccuracy.
Four parameters are needed for the output:
1) nominal output voltage, VOUT (we will use 1.2V)
2) static (or DC) tolerance, TOLST (we will use +/-4%)
3) transient tolerance, TOLTR and size of transient (we will
use +/-8% and 6A for purposes of this demonstration).
4) maximum output current, IOUT (we will design for 6A)
Board components and layout also influence DC
accuracy. The use of 1% feedback resistors contribute
1%. If tighter DC accuracy is required use 0.1%
feedback resistors.
Switching frequency determines the trade-off between
size and efficiency. Increased frequency increases the
switching losses in the MOSFETs, since losses are a
function of VIN2. Knowing the maximum input voltage and
budget for MOSFET switches usually dictates where the
design ends up. It is recommended that the two outputs
are designed to operate at frequencies approximately
25% apart to avoid any possible interaction. It is also
recommended that the higher frequency output is the
lower output voltage output, since this will tend to have
lower output ripple and tighter specifications. The
default RtON values of 1MΩ and 715kΩ are suggested
as a starting point, but these are not set in stone. The
first thing to do is to calculate the on-time, tON, at VBAT(MIN)
and VBAT(MAX), since this depends only upon VBAT, VOUT and
R tON.
The on pulse in the SC1485 is calculated to give a
pseudo fixed frequency. Nevertheless, some frequency
variation with line and load can be expected. This
variation changes the output ripple voltage. Because
constant-on regulators regulate to the valley of the
output ripple, ½ of the output ripple appears as a DC
regulation error. For example, if the feedback resistors
are chosen to divide down the output by a factor of five,
the valley of the output ripple will be VOUT. For example:
if VOUT is 2.5V and the ripple is 50mV with VBAT = 6V,
then the measured DC output will be 2.525V. If the ripple
increases to 80mV with VBAT = 25V, then the measured
DC output will be 2.540V.
For VOUT < 3.3V:
The output inductor value may change with current. This
will change the output ripple and thus the DC output
voltage. It will not change the frequency.

VOUT 
−9
t ON _ VBAT(MIN) = 3.3 • 10 −12 • (R tON + 37 • 103 ) •
 + 50 • 10 s
V

BAT ( MIN) 

Switching frequency variation with load can be minimized
by choosing MOSFETs with lower R DS(ON). High R DS(ON)
MOSFETs will cause the switching frequency to increase
as the load current increases. This will reduce the ripple
and thus the DC output voltage.
and

VOUT 
−9
t ON _ VBAT (MAX ) = 3.3 • 10 −12 • (R tON + 37 • 10 3 ) •
 + 50 • 10 s
V

BAT ( MAX ) 

Design Procedure
From these values of tON we can calculate the nominal
switching frequency as follows:
Prior to designing an output and making component
selections, it is necessary to determine the input voltage
range and the output voltage specifications. For purposes
of demonstrating the procedure the output for the
schematic in Figure 8 on Page 16 will be designed.
 2005 Semtech Corp.
fSW _ VBAT (MIN ) =
VOUT
Hz
BAT ( MIN ) • t ON _ VBAT ( MIN ) )
(V
and
11
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SC1485
POWER MANAGEMENT
fSW _ VBAT (MAX )
From this we can calculate the minimum inductor
current rating for normal operation:
VOUT
=
(VBAT(MAX ) • t ON _ VBAT(MAX ) )Hz
IINDUCTOR (MIN) = IOUT (MAX ) +
tON is generated by a one-shot comparator that samples
VBAT via RtON, converting this to a current. This current is
used to charge an internal 3.3pF capacitor to VOUT. The
equations above reflect this along with any internal
components or delays that influence tON. For our example
we select RtON = 1MΩ:
Next we will calculate the maximum output capacitor
equivalent series resistance (ESR). This is determined by
calculating the remaining static and transient tolerance
allowances. Then the maximum ESR is the smaller of the
calculated static ESR (R ESR_ST(MAX)) and transient ESR
(R ESR_TR(MAX)):
Now that we know tON we can calculate suitable values
for the inductor. To do this we select an acceptable
inductor ripple current. The calculations below assume
50% of IOUT which will give us a starting place.
(0.5 • I )
RESR _ ST (MAX ) =
H
and
t ON _ VBAT (MAX )
(0.5 • I )
(ERR
ST
− ERRDC ) • 2
IRIPPLE _ VBAT (MAX )
Ohms
Where ERRST is the static output tolerance and ERRDC is
the DC error. The DC error will be 1% plus the tolerance
of the feedback resistors, thus 2% total for 1%
feedback resistors.
OUT
L VBAT (MAX ) = (VBAT (MAX ) − VOUT ) •
A (MIN)
IINDUCTOR(MIN) = 7.1A(MIN)
fSW_VBAT(MIN) = 266kHz and fSW_VBAT(MAX) = 235kHz
t ON _ VBAT (MIN)
2
For our example:
tON_VBAT(MIN) = 563ns and tON_VBAT(MAX) = 255ns
L VBAT (MIN) = (VBAT (MIN) − VOUT ) •
IRIPPLE _ VBAT (MAX )
For our example:
H
OUT
ERRST = 48mV and ERRDC = 24mV, therefore
For our example:
RESR_ST(MAX) = 22mΩ
LVBAT(MIN) = 1.3µH and LVBAT(MAX) = 1.6µH
We will select an inductor value of 2.2µH to reduce the
ripple current, which can be calculated as follows:
IRIPPLE _ VBAT (MIN) = (VBAT (MIN) − VOUT ) •
t ON _ VBAT (MIN)
L
RESR _ TR (MAX ) =
A P −P
t ON _ VBAT (MAX )
L
A P −P
For our example:
ERRTR = 96mV and ERRDC = 24mV, therefore
For our example:
RESR_TR(MAX) = 10.2mΩ for a full 6A load transient
IRIPPLE_VBAT(MIN) = 1.74AP-P and IRIPPLE_VBAT(MAX) = 2.18AP-P
 2005 Semtech Corp.

 IOUT

TR − ERR DC )
Ohms
IRIPPLE _ VBAT (MAX ) 

+
2

Where ERRTR is the transient output tolerance. Note that
this calculation assumes that the worst case load
transient is full load. For half of full load, divide the IOUT
term by 2.
and
IRIPPLE _ VBAT (MAX ) = (VBAT (MAX ) − VOUT ) •
(ERR
12
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SC1485
POWER MANAGEMENT
We will select a value of 12.5mΩ maximum for our
design, which would be achieved by using two 25mΩ
output capacitors in parallel. Note that for constant-on
converters there is a minimum ESR requirement for
stability which can be calculated as follows:
RESR (MIN )
For our example we will use R TOP = 20.0kΩ and
RBOT = 14.3kΩ, therefore:
ZTOP = 6.67kΩ and CTOP = 60pF
We will select a value of CTOP = 56pF. Calculating the
value of VFB based upon the selected CTOP:
3
=
2 • π • COUT • fSW
This criteria should be checked once the output
capacitance has been determined.
VFB _ VBAT(MIN)
Now that we know the output ESR we can calculate the
output ripple voltage:
VFB_VBAT(MIN) = 14.8mVP-P - good
and
Next we need to calculate the minimum output
capacitance required to ensure that the output voltage
does not exceed the transient maximum limit, POSLIMTR,
starting from the actual static maximum, VOUT_ST_POS, when
a load release occurs:
VRIPPLE _ VBAT(MIN) = RESR • IRIPPLE _ VBAT(MIN) VP −P
For our example:
VRIPPLE_VBAT(MAX) = 27mVP-P and VRIPPLE_VBAT(MIN) = 22mVP-P
VOUT _ ST _ POS = VOUT + ERRDC V
Note that in order for the device to regulate in a
controlled manner, the ripple content at the feedback
pin, VFB, should be approximately 15mVP-P at minimum
V BAT , and worst case no smaller than 10mV P-P . If
VRIPPLE_VBAT(MIN) is less than 15mVP-P the above component
values should be revisited in order to improve this. Quite
often a small capacitor, CTOP, is required in parallel with
the top feedback resistor, RTOP, in order to ensure that
V FB is large enough. C TOP should not be greater than
100pF. The value of CTOP can be calculated as follows,
where R BOT is the bottom feedback resistor. Firstly
calculating the value of ZTOP required:
For our example:
VOUT_ST_POS = 1.224V
POSLIM TR = VOUT • TOL TR V
Where TOLTR is the transient tolerance. For our example:
POSLIMTR = 1.296V
The minimum output capacitance is calculated as
follows:
R
= BOT • (VRIPPLE _ VBAT (MIN) − 0.015 ) Ohms
0.015
2
Secondly calculating the value of CTOP required to achieve
this:
C TOP




 VP −P




For our example:
VRIPPLE _ VBAT(MAX) = RESR • IRIPPLE _ VBAT(MAX) VP −P
Z TOP




R BOT
= VRIPPLE _ VBAT(MIN) • 
1
 RBOT +
1

+ 2 • π • fSW _ VBAT(MIN) • C TOP

R TOp

C OUT (MIN)
 1
1 


−
Z TOP R TOP 

=
F
2 • π • fSW _ VBAT (MIN)
 2005 Semtech Corp.
I


 IOUT + RIPPLE _ VBAT (MAX ) 
2

=L• 
F
2
2
POSLIM TR − VOUT _ ST _ POS
(
)
This calculation assumes the absolute worst case
condition of a full-load to no load step transient occurring
when the inductor current is at its highest. The
capacitance required for smaller transient steps my be
calculated by substituting the desired current for the IOUT
term.
13
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SC1485
POWER MANAGEMENT
For our example:
Thermal Considerations
The junction temperature of the device may be
calculated as follows:
COUT(MIN) = 610µF.
We will select 440µF, using two 220µF, 25mΩ
capacitors in parallel. For smaller load release overshoot,
660µF may be used. Alternatively, one 15mΩ or 12mΩ
220µF, 330µF or 470µF capacitor may be used (with
the appropriate change to the calculation for C TOP),
depending upon the load transient requirements.
TJ = TA + PD • θ JA
Where:
TA = ambient temperature (°C)
PD = power dissipation in (W)
θJA = thermal impedance junction to ambient from
absolute maximum ratings (°C/W)
Next we calculate the RMS input ripple current, which is
largest at the minimum battery voltage:
IIN(RMS ) = VOUT • (VBAT (MIN) − VOUT ) •
IOUT
VBAT _ MIN
The power dissipation may be calculated as follows:
A RMS
PD = 2 • (VCCA • IVCCA + VDDP • IVDDP )
+ Vg • Q g1 • f1 + VBST • 1mA • D1
For our example:
+ Vg • Q g2 • f2 + VBST • 1mA • D 2
IIN(RMS) = 2.14ARMS
Finally, we calculate the current limit resistor value. As
described in the current limit section, the current limit
looks at the “valley current”, which is the average output
current minus half the ripple current. We use the
maximum room temperature specification for MOSFET
RDS(ON) at VGS = 4.5V for purposes of this calculation:
IRIPPLE _ VBAT (MIN)
2
Inserting the following values for VBAT(MIN) condition (since
this is the worst case condition for power dissipation in
the controller) as an example (OUT1 = 1.5V, OUT2 = 1.2V):
A
TA = 85°C
θJA = 84°C/W
VCCA = VDDP = 5V
IVCCA = 1100µA (data sheet maximum)
IVDDP = 150µA (data sheet maximum)
Vg = 5V
Qgx = 60nC
f1 = 250kHz
f2 = 300kHz
VBAT(MIN) = 8V
VBST(MIN) = VBAT(MIN)+VDDP = 13V
D1(MIN) = 1.5/8 = 0.1875
D2(MIN) = 1.2/8 = 0.15
The ripple at low battery voltage is used because we want
to make sure that current limit does not occur under
normal operating conditions.
RILIM = (IVALLEY • 1.2) •
RDS( ON) • 1.4
10 • 10 − 6
Ohms
For our example:
IVALLEY = 5.13A, RDS(ON) = 9mΩ and RILIM = 7.76kΩ
We select the next lowest 1% resistor value: 7.68kΩ
 2005 Semtech Corp.
W
Where:
VCCA = chip supply voltage (V)
IVCCA = operating current (A)
VDDP = gate drive supply voltage (V)
IVDDP = gate drive operating current (A)
Vg = gate drive voltage, typically 5V (V)
Qgx = FET gate charge, from the FET datasheet (C)
fx = switching frequency (kHz)
VBST = boost pin voltage during tON (V)
Dx = duty cycle
Input capacitors should be selected with sufficient ripple
current rating for this RMS current, for example a 10µF,
1210 size, 25V ceramic capacitor can handle
approximately 3A RMS . Refer to manufacturer’s data
sheets and derate appropriately.
IVALLEY = IOUT −
°C
14
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SC1485
POWER MANAGEMENT
gives us:
PD = 2 • (5 • 1100 • 10 −6 + 5 • 150 • 10 −6 )
+ 5 • 60 • 10 −9 • 250 • 10 3 + 13 • 1 • 10 −3 • 0.1875
+ 5 • 60 • 10 −9 • 300 • 103 + 13 • 1 • 10 −3 • 0.15
= 0.182 W
and:
TJ = 85 + 0.182 • 84 = 100
°C
As can be seen, the heating effects due to internal power
dissipation are practically negligible, thus requiring no
special consideration thermally during layout.
 2005 Semtech Corp.
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SC1485
POWER MANAGEMENT
Layout Guidelines
One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and
maximize heat dissipation. The IC ground references, VSSA1 and VSSA2, should be kept separate from power
ground. All components that are referenced to them should connect to them locally at the chip. VSSA1 and VSSA2
should connect to power ground at their respective output capacitors only.
Feedback traces must be kept far away from noise sources such as switching nodes, inductors and gate drives.
Route feedback traces with their respective VSSAs as a differential pair from the output capacitor back to the chip.
Run them in a “quiet layer” if possible.
Chip decoupling capacitors (VDDP, VCCA) should be located next to the pins and connected directly to them on the
same side.
Power sections should connect directly to the ground plane(s) using multiple vias as required for current handling
(including the chip power ground connections). Power components should be placed to minimize loops and reduce
losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not use
“minimum” land patterns for power components. Minimize trace lengths between the gate drivers and the gates of
the MOSFETs to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most critical.
Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling
requirement (and to reduce parasitics) if routed on more than one layer
Current sense connections must always be made using Kelvin connections to ensure an accurate signal.
We will examine the SC1485 OUT2 reference design used in the Design Procedure section while explaining the
layout guidelines in more detail, using the same generic components for OUT1.
5VSUS
VBAT
R1
R2
10R
0402
0402
22
23
VOUT
VOUT1
C7
0402
24
R4
25
0402
26
27
PGOOD
R3
C4
C9
0402
1nF
0402
28
U1
EN/PSV1
TON1
VOUT1
VCCA1
FB1
PGD1
VSSA1
SC1485
BST1
DH1
LX1
ILIM1
VDDP1
DL1
PGND1
Q2
0603
6
5
C2
0u1/25V
0603
10u/25V
1210
VOUT1
C8
0402
3
C1
2n2/50V
0402
L1
R5
4
C6
+
Q1
R6 0R (1)
2
C10
1
VSSA1
C3
+
7343
7343
0402
1uF
0603
1uF
0603
5VSUS
VBAT
5VSUS
R7
1M
0402
R8
10R
0402
8
9
C15
56p
0402
VOUT2
VOUT
10
R9
20k0
0402
11
12
13
PGOOD
1nF
0402
D1
SOD323
C5 0.1uF
7
VSSA1
VBAT
C18
VBAT
5VSUS
R13
20k0
0402
C19
14
1uF
0603
VSSA2
EN/PSV2
TON2
BST2
DH2
VOUT2
LX2
VCCA2
ILIM2
FB2
PGD2
VSSA2
VDDP2
DL2
PGND2
D2
SOD323
C11 0.1uF
21
0603
20
Q3
IRF7811AV
19
0402
17
C13
C14
2n2/50V
0402
0u1/25V
0603
10u/25V
1210
L2
R10 7k87
18
C12
2u2
VOUT2
C16
+
Q4
FDS6676S
R12 0R (1)
16
C20
15
VSSA2
C17
+
220u/25m
7343
220u/25m
7343
0402
1uF
0603
N OTES
(1) R 6 and R 12 aid in k eeping VSSA1 and VSSA2 s eparate f rom PGN D ex c ept where des ired in lay out.
Figure 8: Reference Design and Layout Example
 2005 Semtech Corp.
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SC1485
POWER MANAGEMENT
The layout can be considered in two parts, the control section referenced to VSSA1/2 and the power section.
Looking at the control section first, locate all components referenced to VSSA1/2 on the schematic and place
these components at the chip. Connect VSSA1 and VSSA2 using either a wide (>0.020”) trace. Very little current
flows in the chip ground therefore large areas of copper are not needed.
5VSUS
VBAT
5VSUS
R1
R2
10R
0402
0402
22
23
VOUT
VOUT1
C7
0402
24
EN/PSV1
TON1
SC1485
BST1
DH1
VOUT1
LX1
VCCA1
ILIM1
7
6
5
R4
25
0402
26
27
PGOOD
R3
C4
U1
28
C9
0402
1nF
0402
FB1
PGD1
VSSA1
VDDP1
DL1
PGND1
4
3
2
1
1uF
0603
1uF
0603
5VSUS
VSSA1
VBAT
5VSUS
R7
1M
0402
R8
10R
0402
8
9
C15
56p
0402
VOUT2
VOUT
10
R9
20k0
0402
11
12
13
PGOOD
C18
1nF
0402
C10
R13
20k0
0402
C19
14
EN/PSV2
TON2
BST2
DH2
VOUT2
LX2
VCCA2
ILIM2
FB2
PGD2
VSSA2
VDDP2
DL2
PGND2
21
20
19
18
17
16
15
C20
1uF
0603
1uF
0603
VSSA2
Figure 9: Components Connected to VSSA1 and VSSA2
 2005 Semtech Corp.
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SC1485
POWER MANAGEMENT
Figure 10: Example VSSA 0.020” Traces
In Figure 10, all components referenced to VSSA1 and VSSA2 have been placed and have been connected using
0.020” traces. Note that there are two separate traces, one for VSSA1 and one for VSSA2. Decoupling capacitors
C9 and C19 are as close as possible to their pins, as are VDDP decoupling capacitors C10 and C20. C10 and C20
should connect to the ground plane using two vias each.
 2005 Semtech Corp.
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SC1485
POWER MANAGEMENT
VOUT1
VSSA1
U1
22
23
VOUT
VOUT1
C7
R4
0402
0402
24
25
EN/PSV1
TON1
SC1485
BST1
DH1
VOUT1
LX1
VCCA1
ILIM1
7
6
5
VOUT1
4
C8
C3
+
26
27
R3
28
FB1
PGD1
VSSA1
VDDP1
DL1
PGND1
3
R6
2
VSSA1
1
+
0R (2)
7343
7343
C16
C17
0402
0402
VSSA1
8
9
C15
56p
0402
VOUT
VOUT2
10
R9
20k0
0402
11
EN/PSV2
TON2
BST2
DH2
VOUT2
LX2
VCCA2
ILIM2
21
20
19
VOUT2
18
+
12
13
R13
20k0
0402
14
FB2
PGD2
VSSA2
VDDP2
DL2
PGND2
17
R12 0R (2)
16
+
220u/25m
7343
220u/25m
7343
0402
VSSA2
15
VSSA2
VOUT2
VSSA2
Figure 11: Differential Routing of Feedback and Ground Reference Traces
In Figure 11, VOUT1 and VSSA1 are routed as a differential pair from the output capacitors back to the feedback
components and device. Similarly, VOUT2 and VSSA2 are routed as a differential pair from the output capacitors
back to the feedback components and device.
 2005 Semtech Corp.
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SC1485
POWER MANAGEMENT
Next, looking at the power section, the schematic in Figure 12 below shows the power section and input loop for
OUT2:
VBAT
C14
C13
C12
10u/25V
1210
0u1/25V
0603
2n2/50V
0402
8
7
6
5
Q3 IRF7811AV
1
D
S 2
D
S 3
D
S 4
D
G
4
3
2
1
Q4 FDS6676S
5
G
D
6
S
D
7
S
D
8
S
D
L2
2u2
VOUT2
C16
+
R12 0R (2)
C17
+
220u/25m
7343
220u/25m
7343
0402
Figure 12: Power Section and Input Loop
The schematic has been redrawn to emphasize the input loop. The highest di/dts occur in the input loops and thus
these should be kept as small as possible. The input capacitors should be placed with the highest frequency
capacitors closest to the loop to reduce EMI. Use large copper pours to minimize losses and parasitics. Exactly the
same philosophy applies to the OUT1 power section and input loop. Figure 13 below shows an example of the layout
for the power section using these guidelines.
Figure 13: Power Component Placement and Copper Pours
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SC1485
POWER MANAGEMENT
Key points for the power section:
1) there should be a very small input loop, well decoupled.
2) the phase node should be a large copper pour, but compact since this is the noisiest node.
3) input power ground and output power ground should not connect directly, but through the ground planes instead.
4) The two outputs should not share their input capacitors, and these should have separate PWR_SRC and PGND
(component-side) copper pours.
5) The two output inductors should not be placed adjacent to each other to avoid crosstalk.
6) Notice in Figure 13 placement of 0Ω resistor at the bottom of the output capacitor to connect to VSSA1/2 for
each output.
Connecting the control and power sections should be accomplished as follows (see Figure 14 below):
1) Route VSSA1/2 and their related feedback traces as differential pairs routed in a “quiet” layer away from noise
sources.
2) Route DL, DH and LX (low side FET gate drive, high side FET gate drive and phase node) to chip using wide traces
with multiple vias if using more than one layer. These connections to be as short as possible for loop minimization,
with a length to width ratio less than 20:1 to minimize impedance. DL is the most critical gate drive, with power
ground as its return path. LX is the noisiest node in the circuit, switching between PWR_SRC and ground at high
frequencies, thus should be kept as short as practical. DH has LX as its return path.
3) BST is also a noisy node and should be kept as short as possible.
4) Connect PGND pins on the chip directly to the VDDP decoupling capacitor and then drop vias directly to the
ground plane.
5) Locate the current limit sense resistors between the LX and ILIM pins at the device.
22
23
24
25
U1
EN/PSV1
TON1
SC1485
BST1
DH1
VOUT1
LX1
VCCA1
ILIM1
7
Q2
6
5
4
L1
R5
0402
26
27
28
8
9
10
FB1
PGD1
VSSA1
EN/PSV2
TON2
VOUT2
VDDP1
DL1
PGND1
BST2
DH2
LX2
3
Q1
2
1
21
Q3
IRF7811AV
20
19
L2
2u2
R10 7k87
11
VCCA2
ILIM2
18
0402
12
13
14
FB2
PGD2
VSSA2
VDDP2
DL2
PGND2
17
Q4
FDS6676S
16
15
Figure 14: Connecting Control and Power Sections
Phase nodes (black) to be copper islands (preferred) or wide copper traces. Gate drive traces (red) and phase node
traces (blue) to be wide copper traces (L:W < 20:1) and as short as possible, with DL the most critical.
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POWER MANAGEMENT
Typical Characteristics
1.2V Efficiency (Power Save Mode)
vs. Output Current vs. Input Voltage
1.2V Efficiency (Continuous Conduction Mode)
vs. Output Current vs. Input Voltage
100
100
95
95
VBAT = 8V
90
85
80
Efficiency (%)
85
Efficiency (%)
VBAT = 8V
90
VBAT = 20V
75
70
80
70
65
65
60
60
55
55
50
VBAT = 20V
75
50
0
1
2
3
4
5
6
0
1
2
3
IOUT (A)
1.2V Output Voltage (Power Save Mode)
vs. Output Current vs. Input Voltage
1.220
1.216
1.216
1.212
1.212
VOUT (V)
VOUT (V)
1.208
VBAT = 20V
1.204
1.200
1.196
VBAT = 8V
1.192
6
VBAT = 20V
1.204
1.200
1.196
VBAT = 8V
1.192
1.188
1.188
1.184
1.184
1.180
1.180
0
1
2
3
4
5
6
0
1
2
IOUT (A)
3
4
5
6
IOUT (A)
1.2V Switching Frequency (Power Save Mode)
vs. Output Current vs. Input Voltage
1.2V Switching Frequency (Continuous Conduction
Mode) vs. Output Current vs. Input Voltage
400
400
VBAT = 8V
VBAT = 8V
350
350
300
300
250
Frequency (kHz)
Frequency (kHz)
5
1.2V Output Voltage (Continuous Conduction Mode)
vs. Output Current vs. Input Voltage
1.220
1.208
4
IOUT (A)
VBAT = 20V
200
150
250
150
100
100
50
50
0
VBAT = 20V
200
0
0
1
2
3
4
5
6
0
IOUT (A)
1
2
3
4
5
6
IOUT (A)
Please refer to Figure 8 on Page 16 for test schematic (OUT2)
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SC1485
POWER MANAGEMENT
Typical Characteristics (Cont.)
Load Transient Response,
Continuous Conduction Mode, 0A to 6A to 0A
Trace 1: 1.2V, 50mV/div., AC coupled
Trace 2: LX, 20V/div
Trace 3: not connected
Trace 4: load current, 5A/div
Timebase: 40µs/div.
Load Transient Response,
Continuous Conduction Mode, 0A to 6A Zoomed
Trace 1: 1.2V, 20mV/div., AC coupled
Trace 2: LX, 10V/div
Trace 3: not connected
Trace 4: load current, 5A/div
Timebase: 10µs/div.
Load Transient Response,
Continuous Conduction Mode, 6A to 0A Zoomed
Trace 1: 1.2V, 50mV/div., AC coupled
Trace 2: LX, 10V/div
Trace 3: not connected
Trace 4: load current, 5A/div
Timebase: 10µs/div.
Please refer to Figure 8 on Page 16 for test schematic (OUT2)
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SC1485
POWER MANAGEMENT
Typical Characteristics (Cont.)
Load Transient Response,
Power Save Mode, 0A to 6A to 0A
Trace 1: 1.2V, 50mV/div., AC coupled
Trace 2: LX, 20V/div
Trace 3: not connected
Trace 4: load current, 5A/div
Timebase: 40µs/div.
Load Transient Response,
Power Save Mode, 0A to 6A Zoomed
Trace 1: 1.2V, 20mV/div., AC coupled
Trace 2: LX, 10V/div
Trace 3: not connected
Trace 4: load current, 5A/div
Timebase: 10µs/div.
Load Transient Response,
Power Save Mode, 6A to 0A Zoomed
Trace 1: 1.2V, 50mV/div., AC coupled
Trace 2: LX, 10V/div
Trace 3: not connected
Trace 4: load current, 5A/div
Timebase: 10µs/div.
Please refer to Figure 8 on Page 16 for test schematic (OUT2)
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SC1485
POWER MANAGEMENT
Typical Characteristics (Cont.)
Startup (PSV), EN/PSV Going High
Trace 1: 1.2V, 0.5V/div.
Trace 2: LX, 10V/div
Trace 3: EN/PSV, 5V/div
Trace 4: PGD, 5V/div.
Timebase: 1ms/div.
Startup (CCM), EN/PSV 0V to Floating
Trace 1: 1.2V, 0.5V/div.
Trace 2: LX, 10V/div
Trace 3: EN/PSV, 5V/div
Trace 4: PGD, 5V/div.
Timebase: 1ms/div.
Please refer to Figure 8 on Page 16 for test schematic (OUT2)
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SC1485
POWER MANAGEMENT
Outline Drawing - TSSOP-28
A
DIMENSIONS
INCHES
MILLIMETERS
DIM
MIN NOM MAX MIN NOM MAX
D
e
N
A
A1
A2
b
c
D
E1
E
e
L
L1
N
01
aaa
bbb
ccc
2X E/2
E1
E
PIN 1
INDICATOR
ccc C
2X N/2 TIPS
1 2 3
e/2
B
aaa C
SEATING
PLANE
D
.047
.002
.006
.031
.042
.007
.012
.003
.007
.378 .382 .386
.169 .173 .177
.252 BSC
.026 BSC
.018 .024 .030
(.039)
28
0°
8°
.004
.004
.008
1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
9.60 9.70 9.80
4.30 4.40 4.50
6.40 BSC
0.65 BSC
0.45 0.60 0.75
(1.0)
28
0°
8°
0.10
0.10
0.20
A2 A
C
bxN
bbb
H
A1
C A-B D
c
GAGE
PLANE
0.25
SIDE VIEW
SEE DETAIL
A
L
(L1)
DETAIL
01
A
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MO-153, VARIATION AE.
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SC1485
POWER MANAGEMENT
Land Pattern - TSSOP-28
X
DIM
(C)
G
Z
Y
C
G
P
X
Y
Z
DIMENSIONS
INCHES
MILLIMETERS
(.222)
.161
.026
.016
.061
.283
(5.65)
4.10
0.65
0.40
1.55
7.20
P
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
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