SC2738 Ultra Low Output Voltage Dual Linear FET Controller POWER MANAGEMENT Description Features ±3.5% reference voltage Two independant and fully adjustable outputs Wide supply voltage range permits operation from The SC2738 is an ultra low output voltage dual power supply controller designed to simplify power management for desktop PCs and graphics cards. It is part of Semtech’s Smart LDOTM family of products. The SC2738 has two user adjustable outputs that can be set anywhere between 0.5V and 3.3V (VIN = 12V, anywhere between 0.5V and 1.8V for VIN = 5V) using two external resistors per output. SC2738 features for each output include tight output voltage regulation (±3.5% over -40°C to +85°C), enable controls, open drain power good signals, under-voltage protection and soft start. The enable pins allow the part to enter a very low power standby mode. Pulling them high enables the outputs. The power good pins are open drain and assert low when the voltage at their respective adjust pins is below 88% (typ.) of nominal. If the voltage at the adjust pin is below 50% (typ.) of nominal, the under-voltage protection circuitry will shut down that output. The SC2738 is available in an MSOP-10 surface mount package. 5V or 12V rails Very low quiescent current (500µA typical with both outputs enabled and 5V input) Indivdual Enable control for each output Individual Power Good monitoring and signalling for each output Gate drives from input supply enable use of N-channel MOSFETs User selectable dropout voltage Individual under-voltage protection for each output MSOP-10 surface mount package Applications Desktop PCs Graphics cards Simple dual power supplies Typical Application Circuit 5V or 12V IN VIN1 VIN2 C1 C2 0.1uF (1) 0.1uF (1) 7 8 6 5 1 VOUT1 3 C3 C4 2 100uF, 25mOhm POSCAP R1 R5 2k (2) 11.0k 1 2 3 OUT1 Enable 4 OUT1 Power Good 5 R1 VOUT1 = 0.5 • 1 + R2 Revision: November 16, 2004 VOUT2 Q1 4 U1 SC2738 DRV1 IN ADJ1 DRV2 EN1 ADJ2 PGD1 GND EN2 PGD2 9 100uF, 25mOhm POSCAP R3 10 R6 2k (2) 20.0k 8 7 OUT2 Enable 6 OUT2 Power Good R2 C5 C6 C7 R4 10.0k 10nF (2) 0.1uF 10nF (2) 10.0k Notes: (1) Additional capacitance may be required if far from supply (2) Optional soft-start components 1 R3 VOUT 2 = 0.5 • 1 + R4 www.semtech.com SC2738 POWER MANAGEMENT Absolute Maximum Ratings PRELIMINARY Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability. Parameter Input Supply Voltage Drive Pins Symbol Maximum Units VIN -0.3 to +13.2 V VDRV -0.3 to +8.0 V VADJ, VPGD Adjust and Power Good Pins -0.3 to +5.5 V (1) Enable Pins V EN -0.3 to VIN V Thermal Impedance Junction to Ambient θJ A 113 °C/W Thermal Impedance Junction to Case θJ C 42 °C/W Operating Ambient Temperature Range TA -40 to +85 °C Operating Junction Temperature Range TJ -40 to +150 °C Storage Temperature Range TSTG -65 to +150 °C Lead Temperature (Soldering) 10 Sec. TLEAD 300 °C ESD Rating (Human Body Model) ESD 2 kV Note: (1) Or VIN, if VIN ≤ 5V. Electrical Characteristics Unless specified: TA = 25°C, VIN = VEN = 5V ± 5%, VPWR(1) = 1.5V ± 5%, 0A ≤ IOUT ≤ 3A. Values in bold apply over full operating ambient temperature range. Parameter Symbol Test Conditions Min Typ Max Units 13.2 V IN Supply Voltage VIN Quiescent Current IQ Standby Current IQ(OFF) 4.5 VIN = 5V 500 700 µA VIN = 12V 600 900 µA Both EN low 0.1 1.0 µA Both EN low, VIN = 12V 15.0 Undervoltage Lockout Start Threshold VUVLO VIN rising 3.75 V Hysteresis VHYST VIN falling 0.50 V 2004 Semtech Corp. 2 www.semtech.com SC2738 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: TA = 25°C, VIN = VEN = 5V ± 5%, VPWR(1) = 1.5V ± 5%, 0A ≤ IOUT ≤ 3A. Values in bold apply over full operating ambient temperature range. Parameter Symbol Test Conditions Min VIH Output on 1.3 VIL Output off IEN V E N = 0V Typ Max Units EN Enable Input Threshold Enable Input Bias Current 0.7 0 V µA VIN = VEN = 5V or 12V -1 +1 VADJ = 0.5V -100 0 +100 nA -3.5% 0.500 +3.5% V ADJ Adjust Input Bias Current IADJ Reference Voltage V AD J DRV Output Current IDRV Sourcing, startup (until VTH(PGD) is reached) 10 µA Sourcing, after startup 0.7 2.0 mA Sinking 350 700 µA Full On, IDRV = 0mA, VIN = 12V 6.6 6.9 V Full On, IDRV = 0mA, VIN = 5V 4.70 4.85 VTH(UV) Measured at ADJ pin 40 50 60 %VADJ VTH(PGD) Measured at ADJ pin -15 -12 -9 %VADJ Output Logic Low Voltage VPGD VADJ = 0.4V, IPGD = -1mA 0.4 V Power Good Leakage Current IPGD VADJ = 0.5V, 0V ≤ VPGD ≤ VIN +1 µA tr CDRV-GND = not placed 150 CDRV-GND = 10nF 850 Output Voltage VDRV Under Voltage Protection Trip Threshold (1) PGD Power Good Threshold (2) -1 0 Soft Start Output Rise Time 10% VOUT to 90% VOUT VOUT = 1.05V µs Error Amplifier Open Loop Gain AVOL 52 dB Gain Bandwidth GBW 1 MHz Notes: (1) If VTH(UV) is exceeded for longer than 50µs (nom.) the protection circuitry will shut down that output. (2) During startup only, VTH(PGD) is -6% (typ.), then switches to -12% (typ.). 2004 Semtech Corp. 3 www.semtech.com SC2738 POWER MANAGEMENT Pin Configuration PRELIMINARY Ordering Information Top View Part Number(1) Output Voltage P ackag e SC2738IMSTRT(2) Both adj. from 0.5V to 3.3V MSOP-10 Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant. (MSOP-10) Pin Descriptions Pin Pin Name Pin Function 1 DRV1 Output of regulator #1, output impedance ~ 1k Ω. Drives the gate of an N-channel MOSFET to maintain VOUT1 set by R1 and R2. 2 A D J1 Regulator #1 sense input. Used for sensing the output voltage for power good and under-voltage, and to set the output voltage as follows (refer to application circuit on page 1): R1 VOUT1 = 0.5 • 1 + R2 VOUT(MAX) = 3.3V for VIN = 12V, 1.8V for VIN = 5V. 3 EN1 Active high enable control. Connect to IN if not being used. Do not allow to float. 4 PGD1 Power good signal output for VOUT1. Open drain output pulls low when VOUT1 is below (VOUT1(NOM) -12%). 5 GND Ground. 6 PGD2 Power good signal output for VOUT2. Open drain output pulls low when VOUT2 is below (VOUT2(NOM) -12%). 7 EN2 Active high enable control. Connect to IN if not being used. Do not allow to float. 8 A D J2 Regulator #2 sense input. Used for sensing the output voltage for power good and under-voltage, and to set the output voltage as follows (refer to application circuit on page 1): R3 VOUT 2 = 0.5 • 1 + R4 V = 3.3V for V = 12V, 1.8V for V = 5V. OUT(MAX) 9 DRV2 10 IN 2004 Semtech Corp. IN IN Output of regulator #2, output impedance ~ 1k Ω. Drives the gate of an N-channel MOSFET to maintain VOUT2 set by R3 and R4. +5V or +12V supply. 4 www.semtech.com SC2738 POWER MANAGEMENT Block Diagram (0.94 VBG at start-up) (0.94 VBG at start-up) 2004 Semtech Corp. 5 www.semtech.com SC2738 POWER MANAGEMENT Applications Infomation PRELIMINARY and 3.75mA at 12V in during normal operation. The high side drive voltage is generated from VIN by a 7V (nominal) low dropout regulator, thus at 12V in, 6.9V is available and at 5V in, 4.85V is available (since the LDO will be in dropout). Theory Of Operation The SC2738 dual linear FET controller provides a simple way to drive two N-channel MOSFETs to produce tightly regulated output voltages from one or two available, higher, supply voltages. It takes its power from either a 5V or 12V supply, drawing typically 500µA while operating. At start-up, the source current available from the drive pins is limited to 10µA (typical) until the power good threshold is reached, at approximately 6% below nominal output voltage. At this point the full drive capability is enabled. With this constant current source at start-up, it is a simple matter to use a small capacitor on the drive pin to slow this rate of rise. The rate of rise of the drive pin voltage will be: It contains an internal bandgap reference which is compared to the output voltages via resistor dividers. These resistor dividers are external and user selectable . Depending upon the input voltage used for the device, the drive pin (DRV1, DRV2) can pull up to a guaranteed minimum of 6.6V (from 12V supply) or 4.7V (from 5V supply). Thus the device can be used to regulate a large range of output voltages by careful selection of the external MOSFETs (see component selection, below). dVDRV IDRV = V/s dt CSS A 10nF soft start capacitor will give a 1ms output rise time for VIN = 12V and VOUT = 1.05V, for example. The output rise time will of course depend upon the gate threshold of the MOSFET being used. Please refer to the Output Rise Time chart on Page 12 showing typical output rise times. For very low ESR output capacitors (<5mΩ) and very high soft start capacitance (>100nF), it may be necessary to add a resistor in series with the soft start capacitor to ensure stability. Generally, however, this resistor is not required, as this is a very unlikely situation. The SC2738 includes an active high enable control (EN1, EN2) for each output. If this pin is pulled low, the related drive pin is pulled low, turning off the N-channel MOSFET. If the pin is pulled up to 1.8V ≤ VEN ≤ VIN, the drive pin will be enabled. This pin should not be allowed to float. Each output has a power good output (PGD1, PGD2) which are open drain outputs that pull low if the related output is below the power good threshold (-12% of the programmed output voltage typical, -6% typical at startup). The power good circuitry is active if the device is enabled, regardless of the state of the over current latch. The power good circuitry is not active if that particular output is disabled. The soft start capacitance does not adversely affect transient response since the drive current capability is 200 times higher once the device has started. OCP and Power Supply Sequencing Also included for each output is an overcurrent protection circuit that monitors the output voltage. If the output voltage drops below 50% (typ.) of nominal, as would occur during an overcurrent or short condition, the device will pull the drive pin low and latch off. The device will need to have the power supply or enable pin toggled to reset the latch condition. Each output latches independently (i.e. if one output latches off, the other output will function normally). The SC2738 has output under-voltage protection that looks at a particular output to see if it is a) less than 50% (typical) of it’s nominal value and b) VDRV for that output is within 350mV (typical) of maximum. If both of these criteria are met, there is a 50µs (typical) delay and then the output is shut down. This provides inherent immunity to UV shutdown at start-up (which may occur while the output capacitors are being charged) since VDRV has a very slow rate of rise with IDRV limited to 10µA. Drive Outputs and Soft Start At start-up, it is necessary to ensure that the power supplies and enables are sequenced correctly to avoid erroneous latch-off. For UV latch-off not to occur at startup due to sequencing issues, the key is that the voltage The drive outputs for each output are source and sink capable. The sink current is typically 0.8mA at 5V in (1mA at 12V in). The source current is typically 2mA at 5V in 2004 Semtech Corp. 6 www.semtech.com SC2738 POWER MANAGEMENT Applications Infomation (Cont.) simplicity. Worst case under-voltage threshold is 60% (over temperature) of 1.5V, or 0.9V. The typical enable threshold is ~1V. See Figure 1 below. supplied to the MOSFET drain should be greater than the output under-voltage threshold when that output is enabled. This assumes that the drop through the pass MOSFET is negligible. If not, then this drop needs to be taken into account also since: VOUT = VDRAIN - (IOUT x RDS(ON)). Component Selection Output Capacitors: low ESR capacitors such as Sanyo POSCAPs or Panasonic SP-caps are recommended for bulk capacitance, with ceramic bypass capacitors for decoupling high frequency transients. Input Capacitors: placement of low ESR capacitors such as Sanyo POSCAPs or Panasonic SP-caps at the input to the MOSFET (VDRAIN) will help to hold up the power supply during fast load changes, thus improving overall transient response. If VDRAIN is located at the bulk capacitors for the upstream voltage regulator, additional capacitance may not be required. In this case a 0.1µF ceramic capacitor will suffice. The input supply to the SC2738 should be bypassed with a 0.1µF ceramic capacitor. If the supply to the SC2738 IN pin comes up before the supply to the MOSFET drain, then that output should be enabled as the supply to the MOSFET drain is applied - the Power Good signal for this rail would be ideal. If the power supply to the MOSFET drain comes up before the power supply to the SC2738 IN pin, then the output can either be enabled with the supply to the IN pin or afterwards. Please see the example below. Example: SC2738 powered from 5V, output 1 powered from 1.8V set for 1.5V out, output 2 not shown for SC2738 Supply Comes Up Before MOSFET Drain Supply MOSFET Drain Supply Comes Up Before SC2738 Supply Figure 1: Power Supply Sequencing 2004 Semtech Corp. 7 www.semtech.com SC2738 POWER MANAGEMENT Applications Infomation (Cont.) PRELIMINARY MOSFETs: very low or low threshold N-channel MOSFETs are required. Selecting FETs rated for VGS of 2.7V or 4.5V will depend upon the available drive voltage (6.9V from 12V in or 4.85V from 5V in), the output voltage and output current. For the device to work under all operating conditions, a maximum RDS(ON) must be met to ensure that the output will never go into dropout: RDS( ON)(MAX ) = VIN(MIN ) − VOUT (MAX ) IOUT (MAX ) Ω VOUT (V) R1 or R3 (kΩ ) R2 or R4 (kΩ ) 1.05 11.0 10.0 1.2 14.0 10.0 1.5 20.0 10.0 2.5 45.3 11.3 3.3 63.4 11.3 Table 1: Recommended Resistor Values For SC2738 Note that RDS(ON) must be met at all temperatures and at the minimum VGS condition. Design Example Setting The Output Voltage: the adjust pins connect directly to the inverting input of the error amplifiers, and the output voltage is set using external resistors (please refer to the Typical Application Circuit on page 1). Goal: 1.5V±5% static and ±7% transient @ up to 4A from 2.5V±5% and 5V±5% Total window for DC error and ripple is ±75mV. Total window for transient is ±105mV. Using output 1 as an example, the output voltage can be calculated as follows: Since this device is linear, and assuming that it has been designed to not ever enter dropout, we do not have ripple on the output. R1 VOUT = 0.5 • 1 + R2 The input bias current for the adjust pin is so low that it can be safely ignored. To avoid picking up noise, it is recommended that the total resistance of the feedback chain be less than 100kΩ. The DC error for this output is the sum of: VREF accuracy = ±3.5% = ±52.5mV Feedback chain tolerance = ±1% = ±15mV Please see Table 1 on this page for recommended resistor values for some standard output voltages. All resistors are 1%, 1/10W. Load regulation = ±0.25% = ±3.8mV Set resistors per Table 1 should be 20.0kΩ (top) and 10.0kΩ (bottom). The maximum output voltage that can be obtained from each output is determined by the input supply voltage and the R DS(ON) and gate threshold voltage of the external MOSFET. Assuming that the MOSFET gate threshold voltage is sufficiently low for the output voltage chosen and the worst-case drive voltage, VOUT(MAX) is given by: Total DC error = ±4.75% = 71.3mV This leaves ±2.25% = 33.7mV for the load transient ESR spike, therefore: R ESR(MAX ) = VOUT (MAX ) = VDRAIN(MIN ) − IOUT (MAX ) • RDS( ON)(MAX ) 33.7mV = 8.4m Ω 4A Bulk capacitance required is given by: dI • t µF dV Where dI is the maximum load current step, t is the maximum regulator response time and dV is the allowable voltage droop. Therefore with dI = 4A, t = 1µs, and dV = 33.7mV: CBULK (MIN ) = 2004 Semtech Corp. 8 www.semtech.com SC2738 POWER MANAGEMENT Applications Infomation (Cont.) CBULK (MIN) = 4 • 1• 10 −6 = 119µF 33.7 • 10 − 3 Layout Guidelines The advantages of using the SC2738 to drive external MOSFETs are a) that the bandgap reference and control circuitry are in a die that does not contain high power dissipating devices and b) that the device itself does not need to be located right next to the power devices. Thus very accurate output voltages can be obtained since changes due to heating effects will be minimal. So if we use 1% VOUT set resistors we would select 2 x >100µF, 18mΩ POSCAPs for output capacitance (which assumes that local ceramic bypass capacitors will absorb the balance of the (9 - 8.4)mΩ ESR requirement - otherwise 15mΩ capacitors should be used). If we use 0.1% set resistors, then the total DC error becomes ±3.85% = ±57.8mV, leaving ±3.15% = 47.2mV for the ESR spike. In this case: R ESR(MAX ) = CBULK (MIN) = The 0.1µF bypass capacitor should be located close to the supply (IN) and GND pins, and connected directly to the ground plane. 47.2mV = 11.8mΩ and 4A The feedback resistors should be located at the device, with the sense line from the output routed from the load (or top end of the droop resistor if passive droop is being used) directly to the feedback chain. If passive droop is being used, the droop resistor should be located right at the load to avoid adding additional unplanned droop. −6 4 • 1• 10 = 85µF 47.2 • 10 − 3 So for 0.1% resistors we could use 1 x 100µF, 12mΩ POSCAPs for output capacitance. The input capacitance needs to be large enough to stop the input supply from collapsing below -5% (i.e. the design minimum) during output load steps. If the input to the pass MOSFET is not local to the supply bulk capacitance then additional bulk capacitance may be required. Sense and drive lines should be routed away from noisy traces or components. For very low input to output voltage differentials, the input to output / load path should be as wide and short as possible. Where greater headroom is available, wide traces may suffice. MOSFET selection: since the input voltage to the SC2738 is 5V±5%, the minimum available gate drive is: Power dissipation within the device is practically negligible, thus requiring no special consideration during layout. The MOSFET pass devices should be laid out according to the manufacturer’s guidelines for the power being dissipated within them. VGS = ( 4.4 − 1.575 ) = 2.825 V So a MOSFET rated for VGS = 2.7V will be required, with an RDS(ON)(MAX) (over temp.) given by: RDS( ON)MAX ) = ( VIN(MIN) − VOUT ) IOUT(MAX ) = (2.375 − 1.5) = 22mΩ 4 Obviously, if a 12V rail is available to power the SC2738, the number of FET options increases dramatically. 2004 Semtech Corp. 9 www.semtech.com SC2738 POWER MANAGEMENT Typical Characteristics PRELIMINARY Quiescent Current vs. Junction Temperature Standby Current vs. Junction Temperature vs. Input Voltage 900 vs. Input Voltage 100 Both VEN = 5V Both VADJ < VBG 800 Both VEN = 0V VIN = 12V 700 10 VIN = 12V IQ(OFF) (µA) IQ (µA) 600 500 400 VIN = 5V 1 300 0.1 200 VIN = 5V 100 0 0.01 -50 -25 0 25 50 75 100 125 -50 -25 0 25 TJ (°C) Start Threshold vs. Junction Temperature VIN rising 100 125 VIN = 5V 1.4 VIH 3.0 VIN falling 2.5 VIH/L (V) VUVLO (V) 125 1.6 3.5 2.0 1.5 1.2 1.0 VIL 0.8 1.0 0.6 0.5 0.4 0.0 -50 -25 0 25 50 75 100 -50 125 -25 0 25 0.510 0.508 50 75 TJ (°C) TJ (°C) Reference Voltage vs. Drive Pin Output Current (Sourcing) at Startup Junction Temperature vs. Junction Temperature vs. Input Voltage 20 VIN = VEN = 5V 18 0.506 16 0.504 14 0.502 12 IDRV (µA) VADJ (mV) 100 vs. Junction Temperature 1.8 4.0 75 Enable Input Threshold Voltage 5.0 4.5 50 TJ (°C) 0.500 0.498 VEN = 5V VADJ < VTH(PGD) VIN = 12V 10 8 0.496 6 0.494 4 0.492 2 VIN = 5V 0 0.490 -50 -25 0 25 50 75 100 -50 125 2004 Semtech Corp. -25 0 25 50 75 100 125 TJ (°C) TJ (°C) 10 www.semtech.com SC2738 POWER MANAGEMENT Typical Characteristics (Cont.) Drive Pin Output Current (Sourcing) vs. Drive Pin Output Current (Sinking) vs. Junction Temperature vs. Input Voltage Junction Temperature vs. Input Voltage 1200 5.0 4.5 VEN = 5V VADJ < VBG VIN = 12V 4.0 1000 800 3.0 IDRV (µA) IDRV (mA) 3.5 VIN = 12V VEN = 5V VADJ > VBG 2.5 2.0 VIN = 5V 600 400 1.5 VIN = 5V 1.0 200 0.5 0.0 0 -50 -25 0 25 50 75 100 -50 125 -25 0 25 Drive Pin Output Voltage (Full On) vs. Junction Temperature vs. Input Voltage -44 VIN = 5V -46 VTH(UV) (%VADJ) VIN = 12V 5 VDRV (V) 125 100 125 vs. Junction Temperature VIN = VEN = 5V -42 6 4 3 -48 -50 -52 -54 VEN = 5V IDRV = 0mA VADJ < VBG -56 -58 0 -60 -50 -25 0 25 50 75 100 125 -50 -25 0 25 TJ (°C) 50 75 TJ (°C) Power Good Threshold vs. Power Good Logic Low Output Voltage Junction Temperature vs. Junction Temperature 0.0 200 VIN = VEN = 5V 175 -2.5 150 -5.0 -7.5 VPGD (mV) VTH(PGD) (%VADJ) 100 -40 7 1 75 Under Voltage Trip Threshold 8 2 50 TJ (°C) TJ (°C) Startup only -10.0 VIN = VEN = 5V VADJ = 0.4V IPGD = -1mA 125 100 75 50 -12.5 Normal operation 25 -15.0 0 -50 -25 0 25 50 75 100 125 -50 TJ (°C) 2004 Semtech Corp. -25 0 25 50 75 100 125 TJ (°C) 11 www.semtech.com SC2738 POWER MANAGEMENT Typical Characteristics (Cont.) PRELIMINARY Output Rise Time At Startup vs. Soft Start Capacitance vs. Input Voltage 100 VEN = 5V TJ = 25°C VOUT = 1.05V COUT = 100µF, 25mΩ IOUT = 0A MOSFET = IRF7311 tr(OUT) (ms) 10 VIN = 5V 1 VIN = 12V 0.1 0.1 1 10 100 CDRV (nF) Load Transient Response, No Passive Droop Load Transient Response, With Passive Droop VIN = 5V, 1.2V in to 1.05V out IOUT = 0.01A to 2.51A to 0.01A COUT = 2 x 100µF, 25mΩ Trace 1: VOUT, 20mV/div., offset 1V Trace 2: VDRV, 2V/div. Trace 3: 1.2V in, 50mV/div., offset 1V Trace 4: load FET drain Timebase: 20µs/div. Load rise/fall times ≥ 35A/µs 2004 Semtech Corp. VIN = 5V, 1.2V in to 1.05V out IOUT = 0.01A to 2.51A to 0.01A COUT = 1 x 100µF, 25mΩ RDROOP = 20mΩ Trace 1: VOUT, 20mV/div., offset 1V Trace 2: not connected Trace 3: 1.2V in, 50mV/div., offset 1V Trace 4: load FET drain Timebase: 20µs/div. Load rise/fall times ≥ 35A/µs 12 www.semtech.com SC2738 POWER MANAGEMENT Outline Drawing - MSOP-10 e A DIM D A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc N 2X E/2 ccc C 2X N/2 TIPS E E1 PIN 1 INDICATOR 12 B DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX .043 .000 .006 .030 .037 .007 .011 .003 .009 .114 .118 .122 .114 .118 .122 .193 BSC .020 BSC .016 .024 .032 (.037) 10 8° 0° .004 .003 .010 1.10 0.00 0.15 0.95 0.75 0.17 0.27 0.08 0.23 2.90 3.00 3.10 2.90 3.00 3.10 4.90 BSC 0.50 BSC 0.40 0.60 0.80 (.95) 10 0° 8° 0.10 0.08 0.25 D aaa C SEATING PLANE A2 H A bxN bbb c GAGE PLANE A1 C C A-B D 0.25 L (L1) DETAIL SEE DETAIL SIDE VIEW 01 A A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-187, VARIATION BA. Land Pattern - MSOP-10 X DIM (C) G Y Z C G P X Y Z DIMENSIONS INCHES MILLIMETERS (.161) .098 .020 .011 .063 .224 (4.10) 2.50 0.50 0.30 1.60 5.70 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 2004 Semtech Corp. 13 www.semtech.com