Evaluation board available. NX2305 SINGLE SUPPLY 12V SYNCHRONOUS PWM CONTROLLER WITH NMOS LDO CONTROLLER, POWER GOOD & ENABLES PRELIMINARY DATA SHEET Pb Free Product DESCRIPTION FEATURES n n n n n n n n 12V PWM controller plus LDO controller The NX2305 controller IC is a combination synchronous Hiccup current limit by sensing Rdson of MOSFET Buck and LDO controller IC designed to convert single 12V high side and low side driver 12V supply to low cost dual on board supply applicaFixed internal 300kHz for switching controller tions. The synchronous controller is used for high curDual Independent Digital Soft Start Function rent high efficiency step down DC to DC converter appliAdaptive Deadband Control cations while the LDO controller in conjunction with an Enable pin available to program the Vbus UVLO external low cost N ch MOSFET can be used as a very Shut Down switching and LDO via pulling down low drop out regulator in applications such as converting EnSW or ENLDO pins 3.3V to 2.5V output. Internal UVLO keeps both regulators off until the supply voltage exceeds 9V where inde- n Pb-free and RoHS compliant pendent internal digital soft starts get initiated to ramp up both outputs.The switching section has hiccup current limit by sensing the Rdson of synchronous MOSFET. n PCI Graphic Card on board converters The LDO controller has Feedback Under Voltage Lock n Mother board On board DC to DC applications Out as a short circuit protection.Other features includes: n On board Single Supply 12V DC to DC such as 12V to 3.3V, 2.5V or 1.8V 12V gate drive capability , Adaptive dead band control, Power good flag for the switcher controller and separate n Set Top Box and LCD Display Enable pins for independent power sequencing. APPLICATIONS TYPICAL APPLICATION R14 10 C11 open VOUT2 +1.6V/2A VIN2 +3.3V 5V REG R6 10k VCC PVCC C1 0.1uF 1N4148 PGOOD LDO OUT C9 M5 47uF BST C4 0.1uF C10 150pF HDRV LDO FB C8 150uF 25mohm R8 5k R9 5k R10 ENLDO 0.75k R11 1.4k M3 NX2305 VIN2 +3.3V C12 1uF L1 1uH C2 180uF M1 IRFR3709Z L2 2.2uH SW C7 2 x 470uF OCP LDRV M2 IRFR3709Z R1 4k PGND HI=SD VIN1 +12V R2 1.1k VOUT1 +1.8V/10A R3 10k C6 3.9nF R12 FB ENSW 6.8k VIN1 +12V C3 100uF R13 1.4k R5 C5 10k 5.6nF R4 8k COMP M4 AGND HI=SD C13 100pF Figure1 - Typical application of NX2305 ORDERING INFORMATION Device NX2305CMTR NX2305CSTR Rev.5.0 08/19/08 Temperature 0 to 70oC 0 to 70oC Package MLPQ-16L SOIC -16L Frequency 300kHz 300kHz Pb-Free Yes Yes 1 NX2305 ABSOLUTE MAXIMUM RATINGS Vcc to PGND & BST to SW voltage .................... -0.3V to 16V BST to PGND Voltage ...................................... -0.3V to 35V SW to PGND .................................................... -2V to 35V All other pins .................................................... -0.3V to 6.5V Storage Temperature Range ............................... -65oC to 150oC Operating Junction Temperature Range ............... -40oC to 125oC CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. PACKAGE INFORMATION BST SW OCP COMP 16-LEAD PLASTIC MLPQ 16 15 14 13 16-LEAD PLASTIC SOIC θ JA ≈ 83o C/W θ JA ≈ 46o C/W HDRV 1 BST HDRV GND LDRV PVCC VCC LDO-OUT LDO-FB 12 FB PGND 2 11 PGOOD 17 AGND LDRV 3 10 EN-SW 9 EN-LDO 5 6 7 8 VCC LDO-OUT LDO-FB 5V REG PVCC 4 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 SW OCP COMP FB PGOOD EN-SW EN-LDO 5V REG ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over Vcc =12V, V BST-VSW =12V, ENSW=ENLDO=3V, and TA = 0 to 70oC. Typical values refer to TA = 25oC. PARAMETER Reference Voltage Ref Voltage Ref Voltage line regulation Supply Voltage(Vcc&VBST) VCC Voltage Range VCC Supply Current (Static) SYM Test Condition VCC ICC (Static) ENSW=LOW ENLDO=LOW PVCC Supply Current (Dynamic) ICC CL=3300pF (Dynamic) 10V<=Vcc<=14V VBST to VSW VBST Supply Current(Static) VBST (Static) ENSW=LOW ENLDO=LOW TYP MAX 0.8 0.2 VREF VBST Voltage Range Rev.5.0 08/19/08 Min Units V % 8 V mA 8.5 mA 8.2 14 8.2 14 0.2 V mA 2 NX2305 PARAMETER VBST Supply Current (Dynamic) Under Voltage Lockout VCC -Threshold VCC hysterises Oscillator (Rt) Frequency Ramp-Amplitude Voltage Max Duty Cycle Min duty Cycle SYM VBST (dynamic) Test Condition C L=3300PF EN & SS Soft Start time Enable HI Threshold TYP 9.2 MAX Units mA VCC_UVLO VCC Rising (NOTE1) 6.8 V VCC Falling (NOTE1) 300 mV FS 300 KHz VRAMP 1.1 94 V % % 0 Error Amplifiers Open Loop Gain Transconductance Comp SD threshold Input Bias Current Min 50 gm 65 dB 2000 0.2 umho V nA Ib 100 Tss 6.8 1.24 mS V 30 mV I=200mA 3.6 ohm Rsink(Hdrv) I=200mA 1 ohm Rise Time THdrv(Rise) 10% to 90% 30 ns Fall Time Deadband Time THdrv(Fall) 90% to 10% Tdead(L to Ldrv going Low to Hdrv going H) High, 10% to 10% 20 50 ns ns R source(Ldrv) I=200mA 2.2 ohm Rsink(Ldrv) I=200mA 1 ohm Rise Time Fall Time TLdrv(Rise) TLdrv(Fall) 10% to 90% 90% to 10% 30 20 ns ns Deadband Time Tdead(H to L) SW going Low to Ldrv going High, 10% to 10% 50 ns VENTHH Enable Hysterises VENTHL High Side Driver, Hdrv, BST, SW (CL=3300pF) Output Impedance , Sourcing R source(Hdrv) Current Output Impedance , Sinking Current N Low Side Driver , Ldrv, PVcc, Pgnd(CL =3300pF) Output Impedance, Sourcing Current Output Impedance, Sinking Current LDO Controller FB Pin- Bias Current High Output Voltage Low Output Voltage High Output Source Current Rev.5.0 08/19/08 11.1 0.2 uA V V 1.9 mA 1 3 NX2305 PARAMETER Open Loop Gain FB Under Voltage trip point 50 Units dB % 90 % Hysteresis OCP Adjust 5 % OCP Current Setting 40 uA Power Good(Pgood) Threshold Voltage as % of Vref SYM Test Condition GBNT(Note 2) FB ramping up Min TYP MAX 50 NOTE1: VCC is connected to ENSW pin via a resistor divider. In VCC UVLO test, ENSW pin is open. NOTE2: This parameter is guaranteed by design but not tested in production(GBNT). Rev.5.0 08/19/08 4 NX2305 PIN DESCRIPTIONS PIN SYMBOL PIN DESCRIPTION VCC IC’s supply voltage. This pin biases the internal logic circuits. A high freq 1uF ceramic capacitor is placed as close as possible to and connected to this pin and ground pin. The maximum rating of this pin is 16V. BST This pin supplies voltage to high side FET driver. A high freq 0.1uF ceramic capacitor is placed as close as possible to and connected to these pins and SW pin. ENLDO A resistor divider is connected from the LDO bus voltage to this pin that holds off the LDO soft start until this threshold is reached. An external low cost MOSFET can be connected to this pin for external enable control. ENSW A resistor divider is connected from the respective switcher BUS voltage to this pin that holds off the controller's soft start until this threshold is reached. An external low cost MOSFET can be connected to this pin for external enable control. FB This pin is the error amplifier inverting input. This pin is connected via resistor divider to the output of the switching regulator to set the output DC voltage. COMP This pin is the output of error amplifier and is used to compensate the voltage control feedback loop. OCP This pin is connected to the drain of the external low side MOSFET and is the input of the over current protection(OCP) comparator. An internal current source 40uA is flown to the external resistor which sets the OCP voltage across the Rdson of the low side MOSFET. Current limit point is this voltage divided by the Rds-on. Once this threshold is reached the Hdrv and Ldrv pins are switched low and an internal hiccup circuit is set that recycles the soft start circuit after 2048 switching cycles. SW This pin is connected to source of high side FET and provides return path for the high side driver. It is also used to hold the low side driver low until this pin is brought low by the action of high side turning off. LDRV can only go high if SW is below 1V threshold . HDRV High side gate driver output. LDRV Low side gate driver output. PVCC Supply voltage for the low side fet driver. A high frequency 1uF ceramic cap must be connected from this pin to the PGND pin as close as possible. LDO_FB LDO controller feedback input. This pin is connected via resistor divider to the output of the switching regulator to set the output DC voltage.If the LDOFB pin is pulled below 0.4V, an internal comparator after a delay pulls down LDOOUT pin and initiates the HICCUP circuitry. During the startup this latch is not activated, allowing the LDOFB pin to come up and follow the soft started Vref voltage. LDO_OUT LDO controller output. This pin is controlling the gate of an external NCH MOSFET. The maximum rating of this pin is 16V. 5V REG Rev.5.0 08/19/08 Output of an internal 5V regulator. 5 NX2305 PIN SYMBOL PGOOD PGND A(( AGND Rev.5.0 08/19/08 PIN DESCRIPTION An open drain output that requires a pull up resistor to Vcc or a voltage lower than Vcc. When FB pin reaches 90% of the reference voltage PGOOD transitions from LO to HI state. Power ground pin for low side driver. In SOIC16 package, PGND and AGND are combined together called GND. Analog ground. In MLPD16 package, pad is AGND. 6 NX2305 BLOCK DIAGRAM 1.25V Bias Generator 5VREG 0.8V Bias Regulator VCC UVLO START ENSW_HI 20k BST POR 90k ENSW PGOOD FB 0.9Vref /0.85Vref HDRV VENTHH VENTHL COMP SW 0.2V OC Control Logic START 0.8V PWM OSC Digital start Up PVCC ramp S R LDRV Q OC PGND FB 0.6V CLAMP COMP START I OCP 40uA 1.3V CLAMP OCP Hiccup Logic 0.4 OCP comparator GND FBLDO ENLDO 1.25/1.15 POR ENSW_HI LDO digital start up LDOOUT Figure 2 - Simplified block diagram of the NX2305 Rev.5.0 08/19/08 7 NX2305 APPLICATION INFORMATION IRIPPLE = Symbol Used In Application Information: VIN - Input voltage VOUT - Output voltage IOUT - Output current = VIN -VOUT VOUT 1 × × LOUT VIN FS ...(2) 12V-1.8V 1.8V 1 × × = 2.3A 2.2uH 12V 300kHz Output Capacitor Selection DVRIPPLE - Output voltage ripple Output capacitor is basically decided by the FS - Switching frequency amount of the output voltage ripple allowed during steady DIRIPPLE - Inductor current ripple state(DC) load condition as well as specification for the load transient. The optimum design may require a couple VIN=12V of iterations to satisfy both condition. Based on DC Load Condition The amount of voltage ripple during the DC load VOUT=1.8V condition is determined by equation(3). Design Example Power stage design requirements: IOUT =10A ∆VRIPPLE = ESR × ∆IRIPPLE + DVRIPPLE <=20mV DVTRAN<=100mV @ 10A step ∆IRIPPLE 8 × FS × COUT ...(3) Where ESR is the output capacitors' equivalent FS=300kHz series resistance,COUT is the value of output capacitors. Typically when large value capacitors are selected Output Inductor Selection such as Aluminum Electrolytic,POSCAP and OSCON The selection of inductor value is based on induc- types are used, the amount of the output voltage ripple tor ripple current, power rating, working frequency and is dominated by the first term in equation(3) and the efficiency. Larger inductor value normally means smaller second term can be neglected. ripple current. However if the inductance is chosen too For this example, POSCAP are chosen as output large, it brings slow response and lower efficiency. Usu- capacitors, the ESR and inductor current typically de- ally the ripple current ranges from 20% to 40% of the termines the output voltage ripple. output current. This is a design freedom which can be decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations: L OUT = VIN -VOUT VOUT 1 × × IRIPPLE VIN FS IRIPPLE =k × IOUTPUT ESR desire = ∆VRIPPLE 20mV = = 8.7mΩ ∆IRIPPLE 2.3A ...(4) If low ESR is required, for most applications, multiple capacitors in parallel are better than a big capacitor. For example, for 20mV output ripple, POSCAP ...(1) where k is between 0.2 to 0.4. Select k=0.3, then 12V-1.8V 1.8V 1 × × 0.3 × 10A 12V 300kHz LOUT =1.7uH LOUT = Choose LOUT=2.2uH, then coilcraft inductor DO5010P-222HC is a good choice. 2R5TPE470M9 with 9mΩ are chosen. N = E S R E × ∆ IR I P P L E ∆ VR IPPLE ...(5) Number of Capacitor is calculated as N= 9m Ω × 2.3A 20mV N =1.03 The number of capacitor has to be round up to a integer. Choose N =2. Current Ripple is calculated as Rev.5.0 08/19/08 8 NX2305 If ceramic capacitors are chosen as output ca- put inductor is smaller than the critical inductance, the pacitors, both terms in equation (3) need to be evalu- voltage droop or overshoot is only dependent on the ESR ated to determine the overall ripple. Usually when this of output capacitor. For low frequency capacitor such type of capacitors are selected, the amount of capaci- as electrolytic capacitor, the product of ESR and ca- tance per single unit is not sufficient to meet the tran- pacitance is high and L ≤ L crit is true. In that case, the sient specification, which results in parallel configura- transient spec is mostly like to dependent on the ESR tion of multiple capacitors. of capacitor. For example, one 100uF, X5R ceramic capacitor with 2mΩ ESR is used. The amount of output ripple is Most case, the output capacitor is multiple capacitor in parallel. The number of capacitor can be calculated by the following 2.3A 8 × 300kHz × 100uF = 4.6mV + 9.6mV = 14.2mV ∆VRIPPLE = 2mΩ × 2.3A + N= Although this meets DC ripple spec, however it needs to be studied for transient requirement. Based On Transient Requirement Typically, the output voltage droop during transient is specified as ∆V droop < ∆V tran @step load DISTEP During the transient, the voltage droop during the ESR E × ∆Istep ∆Vtran + VOUT × τ2 2 × L × C E × ∆Vtran ...(9) where 0 if L ≤ L crit τ = L × ∆Istep − ESR E × CE V OUT if L ≥ L crit ...(10) For example, assume voltage droop during tran- transient is composed of two sections. One section is sient is 100mV for 10A load step. dependent on the ESR of capacitor, the other section is If the POSCAP 2R5TPE470M9 (470uF, 9mohm ESR) is used, the crticial inductance is given as a function of the inductor, output capacitance as well as input, output voltage. For example, for the over- L crit = shoot when load from high load to light load with a 9mΩ × 470µF ×1.8V = 0.76µH 10A DISTEP transient load, if assuming the bandwidth of system is high enough, the overshoot can be estimated as the following equation. ∆Vovershoot = ESR × ∆Istep + VOUT × τ2 2 × L × COUT ...(6) where τ is the a function of capacitor,etc. 0 if L ≤ L crit τ = L × ∆Istep − ESR × COUT V OUT if L ≥ L crit ...(7) where L crit = ESR × COUT × VOUT ESR E × C E × VOUT = ...(8) ∆Istep ∆Istep where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used in parallel. The above equation shows that if the selected out- Rev.5.0 08/19/08 ESR E × C E × VOUT = ∆Istep The selected inductor is 2.2uH which is bigger than critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance. number of capacitor is τ= = N= L × ∆Istep VOUT − ESR E × C E 2.2µH × 10A − 9mΩ × 470µF = 7.97us 1.8V ESR E × ∆Istep ∆Vtran + VOUT × τ2 2 × L × C E × ∆Vtran 9mΩ × 10A 1.8V = + × (7.97us) 2 100mV 2 × 2.2µH × 470µF × 100mV = 1.44 9 NX2305 The number of capacitors has to satisfied both ripple and transient requirement. Overall, we choose N=2. FZ1 = 1 2 × π × R 4 × C2 ...(11) FZ2 = 1 2 × π × (R 2 + R3 ) × C3 ...(12) FP1 = 1 2 × π × R3 × C3 ...(13) It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high frequency capacitor such as high quality POSCAP es- 1 FP2 = pecially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the ESR of capacitors is so low that the PCB parasitic can affect the results tremendously. More capacitors have to be selected to compensate these parasitic parameters. Compensator Design Due to the double pole generated by LC filter of the power stage, the power system has 180o phase shift , and therefore, is unstable by itself. In order to achieve accurate output voltage and fast transient response, compensator is employed to provide highest possible bandwidth and enough phase margin. Ideally, the Bode plot of the closed loop system has crossover frequency between 1/10 and 1/5 of the switching frequency, phase margin greater than 50o and the gain crossing 0dB with 20dB/decade. Power stage output capacitors usually decide the compensator type. If electrolytic capacitors ...(14) C × C2 2 × π × R4 × 1 C1 + C2 where FZ1,FZ2,FP1 and FP2 are poles and zeros in the compensator. The transfer function of type III compensator for transconductance amplifier is given by: Ve 1 − gm × Z f = VOUT 1 + gm × Zin + Z in / R1 For the voltage amplifier, the transfer function of compensator is Ve −Z f = VOUT Zin To achieve the same effect as voltage amplifier, the compensator of transconductance amplifier must satisfy this condition: R4>>2/gm. And it would be desirable if R1||R2||R3>>1/gm can be met at the same time. are chosen as output capacitors, type II compensator can be used to compensate the system, because the zero caused by output capacitor ESR is lower than cross- Zin Zf C1 Vout over frequency. Otherwise type III compensator should be chosen. R3 R2 A. Type III compensator design C3 caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compen- R4 Fb For low ESR output capacitors, typically such as Sanyo oscap and poscap, the frequency of ESR zero C2 gm Ve R1 Vref sate the system with type III compensator. The following figures and equations show how to realize the type III compensator by transconductance amplifier. Rev.5.0 08/19/08 Figure 3 - Type III compensator using transconductance amplifier 10 NX2305 Case 1: FLC<FO<FESR R1= R 2 × VREF 10k Ω × 0.8V = = 8k Ω VOUT -VREF 1.8V-0.8V Choose R1=8kΩ. Gain(db) 3. Set zero FZ2 = FLC and Fp1 =FESR . power stage 4. Calculate R 4 and C3 with the crossover FLC frequency at 1/10~ 1/5 of the switching frequency. Set 40dB/decade FO=25kHz. C3 = loop gain FESR 20dB/decade 1 1 1 ×( ) 2 × π × R2 Fz2 Fp1 1 1 1 ×( ) 2 × π × 10kΩ 3.5kHz 37.6kHz =4.1nF = VOSC 2 × π × FO × L × × Cout Vin C3 R4 = 1.1V 2 × π × 25kHz × 2.2uH × × 940uF 12V 3.9nF =10.4kΩ compensator = Choose C3=3.9nF, R 4=10.2k. FZ1 FZ2 FO FP1 FP2 5. Calculate C2 with zero Fz1 at 75% of the LC double pole by equation (11). Figure 4 - Bode plot of Type III compensator (FLC<FO<FESR) Typical design example of type III compensator in which the crossover frequency is selected as FLC<FO<FESR and FO<=1/10~1/5Fs is shown as the following steps. 1. Calculate the location of LC double pole F LC and ESR zero FESR. FLC = = 1 2 × π × L OUT × COUT 1 1 2 × π × ESR × COUT 1 2 × π × 4.5m Ω × 940uF = 37.6kHz = 2. Set R2 equal to 10kΩ. Rev.5.0 08/19/08 1 2 × π × 0.75 × 3.5kHz × 10.2kΩ = 5.95nF = Choose C2=5.6nF. 6. Calculate C 1 by equation (14) with pole F p2 at half the switching frequency. 1 2 × π × R 4 × FP2 C1 = 2 × π × 2.2uH × 940uF = 3.5kHz FESR = 1 2 × π × FZ1 × R 4 C2 = 1 2 × π × 10.2kΩ × 150kHz = 104pF = Choose C1=100pF. 7. Calculate R 3 by equation (13). R3 = 1 2 × π × FP1 × C3 1 2 × π × 37.6kHz × 3.9nF = 1.1kΩ = Choose R3 =1.1kΩ. 11 NX2305 Case 2: FLC<FESR<FO 2. Set R2 equal to 15kΩ. Gain(db) R1= power stage FLC 40dB/decade R 2 × VREF 15k Ω × 0.8V = = 12k Ω VOUT -VREF 1.8V-0.8V Choose R1=12kΩ. 3. Set zero FZ2 = FLC and Fp1 =FESR . 4. Calculate C3 . C3 = FESR 1 1 1 ×( ) 2 × π × R2 Fz2 Fp1 1 1 1 ×( ) 2 × π × 15kΩ 2.77kHz 8.16kHz =2.5nF = loop gain 20dB/decade Choose C3=2.7nF. 5. Calculate R3 . R3 = compensator 1 2 × π × FP1 × C3 1 2 × π × 8.16kHz × 2.7nF = 7.22kΩ = FZ1 FZ2 FP1 FO FP2 Figure 5 - Bode plot of Type III compensator (FLC<FESR<FO) Choose R3 =7.32kΩ. 6. Calculate R4 with FO=30kHz. R4 = VOSC 2 × π × FO × L R 2 × R 3 × × Vin ESR R 2 + R3 1.1V 2 × π × 30kHz × 2.2uH 15k Ω × 7.32k Ω × × 12V 13m Ω 15kΩ + 7.32k Ω =14.3k Ω = If electrolytic capacitors are used as output capacitors, typical design example of type III compensator in which the crossover frequency is selected as FLC<FESR<FO and F O<=1/10~1/5Fs is shown Choose R4=14.3kΩ. 5. Calculate C2 with zero Fz1 at 75% of the LC double pole by equation (11). as the following steps. Here one SANYO MV-WG1500 with 13 mΩ is chosen as output capacitor. 1. Calculate the location of LC double pole F LC and ESR zero FESR. FLC = = 1 2 × π × LOUT × COUT 1 2 × π × 2.2uH × 1500uF = 2.77kHz FESR = 1 2 × π × ESR × COUT 1 2 × π × 13m Ω × 1500uF = 8.16kHz = Rev.5.0 08/19/08 C2 = 1 2 × π × FZ1 × R 4 1 2 × π × 0.75 × 2.77kHz × 14.3kΩ = 3.9nF = Choose C2=3.9nF. 6. Calculate C 1 by equation (14) with pole F p2 at half the switching frequency. C1 = 1 2 × π × R 4 × FP2 1 2 × π × 14.3kΩ × 150kHz = 74pF = Choose C1=82pF. 12 NX2305 B. Type II compensator design C2 If the electrolytic capacitors are chosen as power Vout stage output capacitors, usually the Type II compensator can be used to compensate the system. R2 For this type of compensator, FO has to satisfy FLC<FESR<<FO<=1/10~1/5Fs. C1 R3 Fb gm R1 Ve Vref Case 1: Type II compensator can be realized by simple RC circuit as shown in figure 7. R3 and C1 introduce a zero to cancel the double pole effect. C2 introduces a Figure 7 - Type II compensator with transconductance amplifier(case 1) pole to suppress the switching noise. To achieve the same effect as voltage amplifier, the compensator of transconductance amplifier must satisfy this condition: R3>>1/gm and R1||R2>>1/gm. The ample for type II compensator design, three 1500uF following equations show the compensator pole zero lo- with 19mohm Sanyo electrolytic CAP 6MV1500WGL cation and constant gain. are used as output capacitors. Coilcraft DO5010P- The following parameters are used as an ex- 152HC 1.5uH is used as output inductor. See figure R Gain= 3 R2 ... (15) 1 Fz = 2 × π × R3 × C1 ... (16) 1 Fp ≈ 2 × π × R 3 × C2 ... (17) 19. The power stage information is that: VIN=12V, VOUT=1.2V, IOUT =12A, FS=300kHz. 1.Calculate the location of LC double pole F LC and ESR zero FESR. FLC = 1 2 × π × L OUT × COUT 1 = 2 × π × 1.5uH × 4500uF = 1.94kHz Gain(db) power stage 40dB/decade FESR = 1 2 × π × ESR × COUT 1 2 × π × 6.33m Ω × 4500uF = 5.6kHz = loop gain 20dB/decade 2.Set crossover frequency FO=30kHz>>FESR. 3. Set R2 equal to10kΩ. Based on output voltage, using equation 21, the final selection of R 1 is 20kΩ. 4.Calculate R3 value by the following equation. compensator Gain R3= FZ FLC FESR FO FP Figure 6 - Bode plot of Type II compensator Rev.5.0 08/19/08 V O S C 2 × π × FO × L × × R2 V in ESR 1.1V 2 × π × 3 0 k H z × 1 .5uH × × 10kΩ 12V 6.33m Ω =37.2kΩ = Choose R 3 =37.4kΩ. 13 NX2305 5. Calculate C1 by setting compensator zero FZ at 75% of the LC double pole. 1 2 × π × 37.4kΩ × 0.75 × 1.94kHz =2.9nF = Gain(db) power stage 1 2 × π × R3 × Fz C1= 40dB/decade loop gain Choose C1=2.7nF. 6. Calculate C 2 by setting compensator pole Fp 20dB/decade at half the swithing frequency. C2= 1 π × R 3 × Fs compensator 1 = π × 3 7 .4k Ω × 1 5 0 k H z =57pF Gain Choose C2=56pF. FZ FLC FESR FO FP Case 2: Type II compensator can also be realized by simple Figure 8 - Bode plot of Type II compensator RC circuit without feedback as shown in figure 9. R3 and C1 introduce a zero to cancel the double pole effect. C2 Vout introduces a pole to suppress the switching noise. The following equations show the compensator pole zero lo- R2 Fb cation and constant gain. gm Gain=gm × R1 × R3 R1+R2 1 Fz = 2 × π × R3 × C1 Fp ≈ 1 2 × π × R3 × C2 ... (18) R1 Vref ... (19) Ve R3 C2 C1 ... (20) Figure 9 - Type II compensator with transconductance amplifier For this type of compensator, FO has to satisfy FLC<FESR<<FO<=1/10~1/5Fs. The following is parameters for type II compensator design. Input voltage is 12V, output voltage is 3.3V, output inductor is 1.5uH, output capacitors are two 680uF with 41mΩ electrolytic capacitors. 1.Calculate the location of LC double pole F LC and ESR zero FESR. Rev.5.0 08/19/08 14 NX2305 FLC = Output Voltage Calculation 1 2 × π × L OUT × COUT 1 = 2 × π × 1.5uH × 1360uF = 3.5kHz FESR = 1 2 × π × ESR × COUT 1 2 × π × 20.5m Ω × 1360uF = 5.7kHz = Output voltage is set by reference voltage and external voltage divider. The reference voltage is fixed at 0.8V. The divider consists of two ratioed resistors so that the output voltage applied at the Fb pin is 0.8V when the output voltage is at the desired value. The following equation and picture show the relationship between VOUT , VREF and voltage divider.. Vout R2 Fb 2.Set R2 equal to10.2kΩ. Using equation 21, the final selection of R1 is 3.24kΩ. 3. Set crossover frequency at 1/10~ 1/5 of the R1 Vref swithing frequency, here FO=30kHz. 4.Calculate R3 value by the following equation. Figure 10 - Voltage divider V 2 × π × FO × L 1 R1 +R 2 × × R 3 = OSC × Vin RESR gm R1 1.1V 2 × π × 30kHz × 1.5uH 1 × × = 12 20.5Ω 2mA/V 10.2kΩ+3.24k Ω × 3.24kΩ =2.6kΩ Choose R 3 =2.61kΩ. 5. Calculate C1 by setting compensator zero FZ at 75% of the LC double pole. C1 = 1 2 × π × R 3 × Fz 1 2 × π × 2.61kΩ × 0.75 × 3.5kHz =23nF = Choose C1=22nF. 6. Calculate C2 by setting compensator pole Fp at half the swithing frequency. C2= 1 π × R 3 × Fs 1 = π × 2 . 6 1k Ω × 3 0 0 k H z =406pF Choose C1=390pF. Rev.5.0 08/19/08 R 1= R 2 × VR E F V O U T -V R E F ...(21) where R 2 is part of the compensator, and the value of R1 value can be set by voltage divider. See compensator design for R1 and R2 selection. Input Capacitor Selection Input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk capacitors supply current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the high frequency noise.The bulk input capacitors are decided by voltage rating and RMS current rating. The RMS current in the input capacitors can be calculated as: IRMS = IOUT × D × 1- D D= VOUT VIN ...(22) VIN = 12V, VOUT=1.8V, IOUT=10A, using equation (22), the result of input RMS current is 3.6A. For higher efficiency, low ESR capacitors are recommended. 15 NX2305 One Sanyo OS-CON 16SVP180M 16V 180uF where QHGATE is the high side MOSFETs gate 20mΩ with 3.64A RMS rating are chosen as input bulk charge,QLGATE is the low side MOSFETs gate charge,VHGS capacitors. is the high side gate source voltage, and VLGS is the low Power MOSFETs Selection side gate source voltage. This power dissipation should not exceed maximum power dissipation of the driver device. The NX2305 requires two N-Channel power MOSFETs. The selection of MOSFETs is based on maximum drain source voltage, gate source voltage, Soft Start and Enable maximum current rating, MOSFET on resistance and NX2305 has digital soft start for switching control- power dissipation. The main consideration is the power ler and has one enable pin for this start up. When the loss contribution of MOSFETs to the overall converter efficiency. In this design example, two IRFR3709Z are used. They have the following parameters: VDS=30V,RDSON =6.5mΩ,QGATE =17nC. Power Ready (POR) signal is high and the voltage at There are two factors causing the MOSFET power force the output voltage follows the reference and starts loss:conduction loss, switching loss. starts to operate and the voltage at positive input of Error amplifier starts to increase, the feedback network will the output slowly. After 2048 cycles, the soft start is Conduction loss is simply defined as: PHCON =IOUT 2 × D × RDS(ON) × K PLCON =IOUT × (1 − D) × RDS(ON) × K enable pin is above VENTHH, the internal digital counter complete and the output voltage is regulated to the desired voltage decided by the feedback resistor divider. 2 ...(23) Vbus + PTOTAL =PHCON + PLCON where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature dependency. As a result, RDS(ON) should be selected for the worst case, in which K approximately equals to 1.4 OFF R1 ENSW or ENLDO R2 V ENTHH V ENTHL ON 10k POR Digital start up at 125oC according to IRFR3709Z datasheet. Conduction loss should not exceed package rating or overall system thermal budget. Figure 11 - Enable and Shut down the NX2305 Switching loss is mainly caused by crossover with Enable pin. conduction at the switching transition. The total switching loss can be approximated. The start up of NX2305 can be programmed through 1 × VIN × IOUT × TSW × FS ...(24) 2 where IOUT is output current, TSW is the sum of TR and TF which can be found in mosfet datasheet, and FS is switching frequency. Switching loss PSW is frequency dependent. Also MOSFET gate driver loss should be considered when choosing the proper power MOSFET. MOSFET gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver circuits.It is proportional to frequency and is defined as: PSW = Pgate = (QHGATE × VHGS + QLGATE × VLGS ) × FS Rev.5.0 08/19/08 resistor divider at Enable pin. For example, if the input bus voltage is 12V and we want NX2305 starts when Vbus is above 8V. We can select R1 = (8V − VENTHH ) × R2 VENTHH The NX2305 can be turned off by pulling down the Enable pin by extra signal MOSFET as shown in the above Figure. When Enable pin is below VENTHL, the digital soft start is reset to zero. In addition, all the high side and low side driver is off and no negative spike will be generated during the turn off. ...(25) 16 NX2305 R RDSON = (VLDOIN − VLDOOUT ) × I LOAD Over Current Protection = (3.3V − 2.5V) / 2A = 0.4Ω Over current protection for NX2305 is achieved by sensing current through the low side MOSFET. An inter- Most of MOSFETs can meet the requirement. More nal current source of 40uA flows through an external re- important is that MOSFET has to be selected right pack- sistor connected from OCP pin to SW node sets the age to handle the thermal capability. For LDO, maxi- over current protection threshold. When synchronous FET mum power dissipation is given as is on, the voltage at node SW is given as PLOSS = (VLDOIN − VLDOOUT ) × I LOAD VSW =-IL × RDSON = (3.3V − 2.5V) × 2A = 1.6W The voltage at pin OCP is given as Select IR MOSFET IRFR3706 with 9mΩ RDSON is IOCP × ROCP +VSW sufficient. When the voltage is below zero, the over current occurss as shown in figure 12. LDO Compensation vbus The diagram of LDO controller including VCC regulator is shown in figure 13. I OCP 40uA LDO input SW + OCP R OCP OCP comparator Figure 12 - Over current protection Vref Rf1 ESR Rf2 Rc Rload Cc Co The over current limit can be set by the following equation ISET = IOCP × ROCP /RDSON If the MOSFET R DSON=9mΩ, and the current limit is set at 15A, then ROCP = ISET × RDSON 15A × 9mΩ = = 3.375kΩ IOCP 40uA Choose ROCP=4kΩ LDO Selection Guide NX2305 offers a LDO controller. The selection of MOSFET to meet LDO is more straight forward. The selection is that the Rdson of MOSFET should meet the dropout requirement. For example. VLDOIN =3.3V VLDOOUT =2.5V ILoad =2A The maximum Rdson of MOSFET should be Figure 13 - NX2305 LDO controller. For most low frequency capacitor such as electrolytic, POSCAP, OSCON, etc, the compensation parameter can be calculated as follows. CC = g × ESR 1 × m 4 × π × FO × R f1 1+gm × ESR where FO is the desired crossover frequency. Typically, in this LDO compensation, crossover frequency F O has to be higher than zero caused by ESR. FO is typically around several tens kHz to a few hundred kHz. For this example, we select Fo=100kHz. gm is the forward trans-conductance of MOSFET. For IRFR3706, gm=53. Select Rf1=5kohm. Output capacitor is Sanyo POSCAP 4TPE150MI with 150uF, ESR=18mohm. Rev.5.0 08/19/08 17 NX2305 CC = 1 53 × 18m Ω × =77pF 4 × π × 100kHz × 5k Ω 1+53 × 18m Ω channel for 2048 cycles and start to restart system again. Layout Considerations Choose CC=82pF. For electrolytic or POSCAP, RC is typically selected to be zero. Rf2 is determined by the desired output voltage. R f1 × VREF VLDOOUT − VREF R f2 = 5kΩ × 0.8V 1.6V − 0.8V =5kΩ = Choose Rf2=5kΩ. When ceramic capacitors or some low ESR bulk capacitors are chosen as LDO output capacitors, the zero caused by output capacitor ESR is so high that crossover frequency FO has to be chosen much higher than zero caused by RC and CC and much lower than zero caused by ESR . For example, 10uF ceramic is used as output capacitor. We select Fo=100kHz, Rf1=5kohm and select MOSFET MTD3055(gm=5). R C and CC can be calculated as follows. 2 × π × FO × CO RC =R f1 × 0.5 × gm 2 × π × 100kHz × 10uF =5kΩ × 0.5 × 5S =12.56kΩ Choose RC=12.7kΩ. CC = 10 × CO RC × gm 10 × 10uF 12.7kΩ × 5S =1.6nF = The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. There are two sets of components considered in the layout which are power components and small signal components. Power components usually consist of input capacitors, high-side MOSFET, low-side MOSFET, inductor and output capacitors. A noisy environment is generated by the power components due to the switching power. Small signal components are connected to sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is recommended . Layout guidelines: 1. First put all the power components in the top layer connected by wide, copper filled areas. The input capacitor, inductor, output capacitor and the MOSFETs should be close to each other as possible. This helps to reduce the EMI radiated by the power loop due to the high switching currents through them. 2. Low ESR capacitor which can handle input RMS ripple current and a high frequency decoupling ceramic cap which usually is 1uF need to be practically touching the drain pin of the upper MOSFET, a plane connection is a must. 3. The output capacitors should be placed as close as to the load as possible and plane connection is required. 4. Drain of the low-side MOSFET and source of the high-side MOSFET need to be connected thru a plane Choose CC=1.5nF. ans as close as possible. A snubber nedds to be placed as close to this junction as possible. Current Limit for LDO Current limit of LDO is achieved by sensing the LDO feedback voltage. When LDO_FB pin is below 0.4V, the IC goes into hiccup mode. The IC will turn off all the 5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not enough. This is very important. The same applies to the output capacitors and input capacitors. 6. Hdrv and Ldrv pins should be as close to MOSFET gate as possible. The gate traces should be Rev.5.0 08/19/08 18 NX2305 wide and short. A place for gate drive resistors is needed to fine tune noise if needed. 7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the IC and as close as possible. The capacitor on comp to GND or comp back to FB needs to be place as close to the pin as well as resistor divider. 8. The output sense line which is sensing output back to the resistor divider should not go through high frequency signals. 9. All GNDs need to go directly thru via to GND plane. 10. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. 11. In multilayer PCB, separate power ground and analog ground. These two grounds must be connected together on the PC board layout at a single point. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. R14 10 C11 open VOUT2 +1.2V/2A VOUT1 +1.8V 5V REG R6 10k VCC PVCC PGOOD C9 M5 47uF C10 R7 0 LDO OUT C4 0.1uF 150pF HDRV LDO FB C8 150uF 25mohm R8 5k R9 5k R10 ENLDO 0.75k R11 1.4k C1 1uF 1N4148 BST M3 NX2305 VOUT1 +1.8V C12 1uF C7 1500uF 13mohm OCP LDRV M2 IR3711 R1 5k R2 22.1k VOUT1 +1.8V/10A R3 49.9k C6 820pF R12 FB ENSW 6.8k C2 180uF M1 IR3709 L2 2.2uH VIN1 +12V C3 100uF SW PGND HI=SD VIN1 +12V L1 1uH R13 1.4k R5 C5 COMP M4 40.2k 1.8nF R4 40.2k AGND HI=SD C13 27pF Figure 14 - Typical application of NX2305 with single power supply Rev.5.0 08/19/08 19