SC4611 Wide Input Range High Performance Synchronous Buck Switching Regulator POWER MANAGEMENT Description Features SC4611 comes with a rich set of features like regulated Wide input range, 4.5 to 30V Output voltage as low as 0.5V 2A output drive capability Asynchronous start up mode Multimode overcurrent protection with current limit, hiccup mode and latched shutdown Overvoltage crowbar protection Power OK signal Programmable frequency up to 1 MHz with external synchronization –40 to +85 degree C operating temperature Thermal shutdown Small package TSSOP-20 Vcc supply, soft start, power-good signaling, high current gate drivers, bootstrapped supply for driving high side Nchannel MOSFETs, shoot through protection, frequency synchronization and the option for overvoltage crowbar. It also features multi mode overload protection that includes continuous current limiting, hiccup mode followed by latch off. The user has the option of bypassing the hiccup mode and latch off the output if required. Distributed power architectures Telecommunication equipment Servers/work stations Mixed signal applications Paralleled synchronous buck convertors Base station power management SC4611 is a high performance synchronous buck controller that can be configured for a wide range of applications. The SC4611 utilizes synchronous rectified buck topologies where high efficiency is the primary consideration. It is optimized for applications involving multiple and redundant convertors connected together. The star tup is asynchronous, which keeps the lower side FET off during soft start. This is a desired feature when a convertor is turned on with a preset external voltage or pre-bias voltage already present across its output. With the lower FET off, external bus is not discharged which avoids latch-up of modern ASIC circuits. Applications Typical Application Circuit VIN (30V MAX) QH Cin VOUT (0.5V MIN) Lout Rcs QL 5 17 20 14 13 RTN RT 16 12 9 8 VIN BS T BD I GDH AVC C PH P VC C GDL S S /S H OS C S YN C SC4611 4 CS+ CSOVP CLM AG N D E AO PGND FB P OK Cout 3 2 1 Rclset 19 7 6 11 15 18 10 RTN Revision: November 10, 2004 1 www.semtech.com SC4611 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability. Parameter Symbol Maximum Units BST to PGND VBSTMAX 37 V VIN and BDI to PGND VINMAX 30 V PVCC, AVCC to PGND AVCCMAX 7 V ±0.3 V -0.3 to 7 V PVCC +0.3 V AVCC +0.3 V IGDHMAX, IGDLMAX 2 A TSTGMAX -60 to +150 °C TJMAX -40 to +125 °C 260 °C PGND to AGND BST to PH VGDHMAX, VGDLMAX GDH to PH, GDL to PGND All Other Pins to AGND GDH, GDL Source or Sink Current Storage Temperature Range Junction Temperature Lead Temperature (Soldering) 10 Sec. Electrical Characteristics Unless specified: TA = TJ = -40 to +85°C, Vin = 12V, PVCC = AVCC = 6V, Fsw = 625 kHz, SS/SH = 5V Parameter Symbol Test Conditions Min Typ Max Unit AVCC AVCC VIN > 5.5V 4.5 6 6.5 V PVCC PVCC VIN > 5.5V 4.5 6 6.5 V Operating Current ISUPPLY No load on GDH and GDL pins 7 10 mA Quiescent Current IQUI SS/SH = 0V 4 6 mA VUVLO AVCC Rising 4.2 4.4 V Power Supply Undervoltage Lockout Start Threshold 4.0 UVLO Hysteresis 0.16 V Soft Start/Shut Down Charge Current ISSC Discharge Current ISSD 4 Disable Threshold Voltage Disable Low to Shut Dow n 2004 Semtech Corp. (1) 2 7 10 µA 0.5 mA 0.5 V 50 nS www.semtech.com SC4611 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: TA = TJ = -40 to +85°C, Vin = 12V, PVCC = AVCC = 6V, Fsw = 625 kHz, SS/SH = 5V Parameter Symbol Test Conditions Min Typ Max Unit 1000 kHz 700 kHz Oscillator Frequency Range Fsw Frequency Fsw Peak to Peak Ramp Voltage(1) VRAMP SY NC Input High Pulse Width TSYNC 150 RT = 15K 550 625 3.0 100 nS SY NC Rise/Fall Time SY NC Frequency Range SY NC High/Low Threshold V Fsw 50 nS Fsw +15% kHz 2.0 VSYNC V Error Amplifier Feedback Voltage VFB TA = 25 Deg C 0.493 0.5 0.507 V 0.2 µA Unity Gain Bandwidth (1) 3 MHz Open Loop DC Gain (1) 90 dB + 10 mA Input Bias Current (1) Output Source/Sink Current IEAO Current Sense Comparator CS- pin offset current (ILIM ADJ) ICS- Current limit sense threshold VCL RT = 15K Rclset = 1K 66 82 98 µA 66 82 98 mV Current limit hysteresis 30 % Power Good and Overvoltage Protection FB Level for Output High Sense 0.52 VLTH 0.58 6 Hysteresis (1) FB Level for Output Low Sense 0.55 0.42 VHTH Hysteresis (1) PWR OK Output Low Level VPOK OVP Trip Reference VOVP IPOK = 0 0.475 0.45 V mV 0.48 V 6 mV 0.2 V 0.5 0.525 V (1) Guaranteed by design. Not tested in production. 2004 Semtech Corp. 3 www.semtech.com SC4611 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: TA = TJ = -40 to +85°C, Vin = 12V, PVCC = AVCC = 6V, Fsw = 625 kHz, SS/SH = 5V Parameter Symbol Test Conditions Min Typ Min Units Dmax Fsw = 150 kHz 90 % Fsw = 1 MHz 80 % 150 nS Duty Cycle Maximum Duty Cycle Tpulsemin Minimum Pulse Width (1) Output Gate Drive ON-Resistance (H) RONGDH ISOURCE = 20 mA 2 Ω Gate Drive OFF-Resistance (H) ROFFGDH ISINK = 20 mA 1 Ω Gate Drive ON-Resistance (L) RONGDL ISOURCE = 20 mA 2 Ω Gate Drive OFF-Resistance (L) ROFFGDL ISINK = 20 mA 1 Ω Rise Time Trise COUT = 2000 pF 15 nS Fall Time Tfall COUT = 2000 pF 15 nS 30 nS P ackag e Temp. Range TSSOP-20 (1) -40°C to +85°C Dead Time Between Drive Signals (1) NOTES: (1) Guaranteed by design. Not tested in production. (2) This device is ESD sensitive. Use of standard ESD handling precautions is required Pin Configuration Ordering Information TOP VIEW Part Number SC4611ITSTRT PH 1 20 PVCC GDH 2 19 GDL BST 3 18 PGND VIN 4 17 AVCC BDI 5 16 SYNC CS- 6 15 AGND CS+ 7 14 SS/SH FB 8 13 OSC EAO 9 12 CLM POK 10 11 OVP (2) Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free device. This product is fully WEEE and RoHS compliant. (20 Pin TSSOP) 2004 Semtech Corp. 4 www.semtech.com SC4611 POWER MANAGEMENT Pin Descriptions Pin # Pin Name 1 PH 2 GDH Gate drive output for high side N-Channel MOSFET. 3 BST Boost capacitor connection for the high side gate drive. Connect an external capacitor and a diode as shown in the Typical Application Circuit. 4 VIN Input supply voltage. 5 BD I Base drive for AVCC/PVCC regulator. 6 C S- Inverting input for the current sense comparator 7 C S+ Non inverting input for the current sense comparator 8 FB 9 EAO Error amplifier output for compensation. 10 POK Open drain of power good output. 11 OVP Overvoltage protection input. The reference level is 0.5V 12 C LM Current Limit Mode select input. Connect to AVCC to enable hiccup or connect to AGND to bypass hiccup mode. 13 OSC Connect a resistor to AGND for programming the oscillator frequency. 14 SS/SH Soft start pin. Hold low to shutdown the device. 15 AGND Analog signal ground. 16 SYNC Oscillator synchronization pin. Connect to AGND if not used. 17 AVCC Supply voltage for analog circuitry. 18 PGND Power ground. 19 GDL 20 PVC C 2004 Semtech Corp. Pin Function Switching junction of high side Mosfet source and low side Mosfet drain. Feedback input pin.The reference level is 0.5V Gate drive output for the low side N-Channel MOSFET. Supply voltage for output drivers. 5 www.semtech.com OSC SYNC OVP 0.5V AGND PVCC BDI AVCC + OVP COMP - + R 4R EA - + ENABLE Q QB IN SYNC RAMP CLK OSC & SYNC S R SHDN VS OUT UVLO SS-SEQ REF SR LATCH_2 VBG VS BANDGAP CLM OUT ILIM SS SHDN + 0.45V + 0.55V - + - + Q QB PW M COMP S R VEA IN OUTL FB OUTH + 0.5V DRIVER PVCC DRIVER EAO FB PGND GDL PH GDH BST CS- DRV LOGIC CS+ CLM SS - ILIM ADJ 7 uA AVCC POK + ILIM COMP UV MONITOR SR LATCH_1 FB FB OV MONITOR + + 6 - 2004 Semtech Corp. - VIN SC4611 POWER MANAGEMENT Block Diagram - SC4611 www.semtech.com SC4611 POWER MANAGEMENT Applications Information When the SS pin reaches 2V, the low side MOSFET will begin to switch and the convertor is fully operational in the synchronous mode. The reference input of the error amplifier is released and the SS pin is pulled up to AVCC. The soft start duration is controlled by the value of the SS cap. If the SS pin is pulled below 0.5V, the device is disabled and draws only 4 mA current. INTR ODUCTION INTRODUCTION The SC4611 is designed to control and drive N-Channel MOSFET synchronous rectified buck convertors. The switching frequency is programmable to optimize design. The SC4611 switching regulator section features external current sensing and provides a hiccup mode overcurrent protection followed by a latched shutdown. It is also optimized for multiple convertors operating in parallel redundant mode. Note that the SS pin threshold for soft-start is supply dependant and defined above for AVCC = 6V. If AVCC is lower, the threshold should be reduced proportionately, i.e. SS enable threshold will be 0.375V when AVCC = 4.5V. PO WERING THE CONTR OLLER POWERING CONTROLLER GATE DRIVERS Supplies VIN, PVCC and AVCC from the input source are used to power the SC4611. The VIN supply provides the bias for the internal reference and UVLO circuitry. The AVCC supply provides the bias for the oscillator, PWM switcher, voltage feedback, current sense and the Power OK circuitry. PVCC is used to drive the low and high side MOSFET gates. The low side gate driver is supplied from PVCC and provides a peak source/sink current of 2A. The high side gate drive is also capable of sourcing and sinking peak currents of 2A. Protection logic provides a 30 nS dead time to ensure both the upper and lower MOSFETs will not turn on simultaneously and cause a shoot through condition. An external PNP transistor can be set up as a linear regulator to generate well regulated AVCC and PVCC as shown in the Typical Application Circuit. The maximum current into the BDI pin should be limited to 5 mA under all conditions. For example if an external PNP transistor is used with Vin less than 7V, the BDI pin will saturate and pull down the Vin input. A series resistor between the base of the external PNP transistor and the BDI should be used to limit the current into the BDI pin. The high side MOSFET gate drive can be provided by an external 12V supply that is connected from BST to GND. The actual gate to source voltage of the upper MOSFET will approximately equal 6V (12V-VCC). If the external 12V supply is not available, a classical bootstrap technique can be implemented from the PVCC supply. A bootstrap capacitor is connected from BST to Phase while PVCC is connected through a diode (Low VF Schottky or ultrafast diode) to the BST. This will provide a gate to source voltage approximately equal to the VCC-Vdiode drop. The VCC pins have an absolute maximum rating of 7V. If maximum VIN is less than 7V it may be connected directly to AVCC and PVCC, leaving the BDI pin open. OSCILLA TOR OSCILLAT STAR T UP SEQUENCE ART The switching frequency fsw of the SC4611 is set by an external resistor using the following formula: Start up is inhibited until AVCC input reaches its UVLO threshold. The UVLO limit is 4.2V typical. The power up sequence is initiated by a 7 uA current source charging the soft start capacitor connected to the SS pin. When the SS pin reaches 1V, the converter will start switching. The reference input of the error amplifier is ramped up with the soft-start signal, level shifted down by 1V. Initially only the high side driver is enabled. Keeping the low side MOSFET off during start up is useful where multiple convertors are operating in parallel. It prevents forward conduction in the freewheeling MOSFET which might otherwise cause a dip in the common output bus. 2004 Semtech Corp. RT = 9375 Fsw RT is in kOhm and fsw is in kHz. This relation is a first order approximation of the more complex relationship between RT and Fsw. The oscillator can be synchronised to an external clock that is nominally faster than the internal frequency set by ROSC. The external voltage level applied should be lower than AVCC of the device. 7 www.semtech.com SC4611 POWER MANAGEMENT Applications Information (Cont.) OVER CURRENT PR OTECTION VERCURRENT PRO PO WER OK MONIT OR POWER MONITOR SC4611 includes a precision current sense comparator for maximum flexibility. The current feedback can be taken either from the output inductor for lossless sensing and better efficiency, or from a series resistor for improved accuracy. An offset current of 1.225/RT pulls up on the CSpin, providing an offset voltage across a resistance on the input to this pin. The offset voltage should be set to > 50 mV. A voltage across the current sense resistor of greater than this value will produce a current limit pulse. There is 30% hysteresis on the offset current. Since the offset current into CS- is set by RT, the current limit needs to be adjusted if the frequency setting is changed. Note that the operational limit for CS- and CS+ inputs is 0.5V below the AVCC supply. The power OK circuitry monitors the FB input of the error amplifier. If the voltage on this input goes above 0.55V or below 0.45V the POK pin is pulled low. The POK is an open drain output and is held low until the end of the startup sequence i.e. till the SS pin reaches 2V or more. VOL TAGE AND THERMAL PR OTECTION OVER PRO VERV OLT The overvoltage input can be connected to OVP pin with a low reference of 0.5V. If this feedback exceeds the reference the low side FET is continuously gated on to crowbar the input VIN. This feature may be used to protect the load from possible overvoltage in case the high side FET fails and shorts. The crowbar current in the power devices is limited only by the source of VIN. The first stage of protection against overloads is peak current limiting on a pulse by pulse basis. Once an overload is sensed, the high side FET is turned off and held low for the rest of the cycle. This provides peak current limiting on a pulse by pulse basis. The final response of the device to a severe overload can be programmed using the CLM pin. If the CLM pin is connected to AVCC, the hiccup mode is enabled. A soft-start/hiccup cycle is initiated if 64 current limit pulses are detected in any counting period of 128 oscillator cycles. The SS capacitor is discharged with a 0.6 mA sink current. There will be 3 dummy soft-starts, i.e. the SS pin will be pulled up to 2V and then discharged to < 1V. This will be repeated 7 times, and if the overload persists the part will be latched off on the eighth attempt. Reset is by recycling the input power. During the hiccups, the device will operate in asynchronous mode, just as in the powerup sequence. SC4611 also incorporates thermal protection. If the chip temperature exceeds approximately 150 Deg C, the outputs are shutdown. ERR OR AMPLIFIER DESIGN ERROR SC4611 is a voltage mode buck controller that utilizes an externally compensated high bandwidth error amplifier to regulate output voltage. The power stage of the synchronous rectified buck converter control-to-output transfer function is as shown below: V 1 + sESR C C G ( s) = IN × VD L V 2 LC + + s 1 s S R L In some cases the repeated soft start cycling may not be desirable, depending on the nature of load. If the CLM is taken low to AGND, the hiccup mode will be skipped. When an overcurrent event occurs a comparator detects it and puts out a signal into a latch counter. The counter keeps track of the number of current-limit pulses and is reset after every 128 oscillator cycles. If 64 current-limit pulses are detected in any counting period of 128 cycles, the SS pin will be pulled low. The device is latched off until power is recycled. The CLM pin should be connected to either AGND or AVCC at all times and should not be left open. 2004 Semtech Corp. where, VIN – Input voltage RL – Load resistance L – Output inductance C – Output capacitance ESRC – Output capacitor ESR VS – Peak to peak ramp voltage 8 www.semtech.com SC4611 POWER MANAGEMENT Applications Information (Cont.) The design guidelines are as following: The classical Type III compensation network can be built around the error amplifier as shown below 1. Set the loop gain crossover frequency wC for given switching frequency. C3 C2 R3 R2 C1 2. Place an integrator in the origin to increase DC and low frequency gains. R1 - 3. Select wZ1 and wZ2 such that they are placed near wO to dampen peaking; the loop gain has –20 dB rate to go across the 0 dB line for obtaining a wide bandwidth. + Vref 4. Cancel wESR with compensation pole wP1 (wP1 = wESR ). Figure 1. Voltage Mode Buck Converter Compensation Network 5. Place a high frequency compensation pole wP2 at half the switching frequency to get the maximum attenuation of the switching ripple and the high frequency noise with the adequate phase lag at wC. The transfer function of the compensation network is as follows: s s )(1 + ) ωI ωZ1 ωZ 2 ⋅ GCOMP ( s ) = s (1 + s )(1 + s ) ω P1 ωP2 (1 + where, ωZ1 = ωI = 1 , R2C1 1 , R1(C1 + C3) ωZ 2 = ωP1 = PCB LA YOUT FFOR OR SC46 11 LAY SC461 Careful attention to layout requirements is necessary for successful implementation of the SC4611 PWM controller. High switching currents with fast rise and fall times are present in the application and their effect on ground plane voltage differentials must be understood and minimized. A good layout with minimum parasitic loop areas will 1 (R1 + R3 )C2 1 , R3C2 ωP2 = 1 CC R2 1 3 C1 + C3 a) reduce EMI b) lower ground injection currents, resulting in electrically “cleaner” grounds for the rest of the system and T ω Z1 c) minimize source ringing, resulting in more reliable gate switching signals. Loop gain T(s) ωo ω Z2 Gd ωc LA YOUT GUIDELINES LAY 0dB ω p1 In the following QT and QB denote the high side and low side MOSFETs respectively. ω p2 1) A ground plane should be used. The number and position of ground plane interruptions should be minimised so as not to compromise ground plane integrity. Isolated or semiisolated areas of the ground plane may be deliberately introduced to constrain ground currents into particular paths, such as the output capacitor or the QB source. ω ESR Figure 2. Simplified asymptotic diagram of buck power stage and its compensated loop gain. 2004 Semtech Corp. 9 www.semtech.com SC4611 POWER MANAGEMENT Applications Information (Cont.) 4) The output capacitor Cout should be located as close to the load terminals as possible. Fast transient load currents are supplied by Cout and connections between Cout and the load must be kept short with wide copper areas to minimize inductance and resistance. This will improve the transient response to step loads. 2). The high power, high current parts of the circuit should be laid out first. The on time loop formed by the input capacitor Cin, the high side FET QT, the output inductor and the output capacitor bank Cout must be kept as small as possible. Another loop area to minimise is formed by low side FET QB, the output inductor and the output capacitor bank Cout during the off period. These loops contain all the high current, fast transition switching. Connections should be as wide and as short as possible to minimize loop inductance. 5) The SC4611 is best placed over a quiet ground plane area. Avoid pulse currents of the Cin, QT, QB loop flowing in this area. This analog ground plane should be connected to the power ground plane at a “quiet” point near the input capacitor. Under no circumstance should it be returned to a point inside the Cin, QT, QB, Cout power ground loops. 3). The connection between the junction of QT, QB and the output inductor should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. Also keep the Phase connection to the IC short. The top FET gate charge currents flow in this trace. 6) The SC4611 AGND pin is connected to the separate analog ground plane with minimum lead length . All analog grounding paths including decoupling capacitors, feedback resistors, compensation components, and current-limit setting resistors should be connected to the same plane. 3.3V/10A Evaluation Board Schematic 10-15V Vin to 3.3V/10A 300 kHz Reference Design With SC4611 SHORT VDC R3 R7 L2 2.2 uF T P6 1K Q5 Q3 6670 R6 Q4 R8 R5 .01R/1W TP15 C6 6670 C7 C8 C9 J4 RTN AVCC VOUT 30.1K 47 nF R13 10K 1K R17 T P8 CLM 1.62K PVCC R12 R16 R11 C10 1.62K R10 10K 5R R15 T P7 R14 3906 SS C5 2R R9 J6-3 J3 VOUT 2R TP14 T P4 N/U T P5 GDL .01R/1W R4 10 uF RTN 1R PH T P3 Q2 GDH 10 uF J2 N/U 390 uF C4 2.2 uF 3.3V C3 2.2 uF C2 T P1 Q1 6612 R1 R2 220 uF C1 220 uF T P2 390 uF VIN 390 uF L1 J1 20K R18 J5-1 10R N/U RTN 11 O VP 2K RED D2 POK CLM E AO 9 J5-3 R19 +S 10 12 13 8 FB C S + S S /S H 7 CS6 BD I 5 O SC 14 15 AG N D 16 S YN C 17 AVC C VI N 18 PGND BS T 19 GDL GDH SC4611ITSTR 4 1K 3 1 D3 U1 2 20 PH D1 P VC C 4148 C11 R20 J6-4 SYNC OVP 1 uF TP12 TP13 R21 R22 10K 249R J5-2 N/U J6-1 VGG BST CS+ CS- VFB T P9 C18 10 uF 10 uF RTN 100 uF 2004 Semtech Corp. C19 C20 N/U C21 N/U 1 nF C14 100 pF J6-2 C13 C17 EAO T P10 R26 C12 C15 R24 C16 10 nF N/U 33.2K 2.2 nF R23 TP11 1.78K R25 10R J5-4 -S 100 uF 10 www.semtech.com SC4611 POWER MANAGEMENT Outline Drawing - TSSOP-20 A D e 2X E/2 E PIN 1 INDICATOR ccc C 1 2 3 2X N/2 TIPS e/2 B 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.20 0.09 6.40 6.50 6.60 4.30 4.40 4.50 6.40 BSC 0.65 BSC 0.45 0.60 0.75 (1.0) 20 0° 8° 0.10 0.10 0.20 D aaa C SEATING PLANE .047 .006 .002 .042 .031 .007 .012 .007 .003 .251 .255 .259 .169 .173 .177 .252 BSC .026 BSC .018 .024 .030 (.039) 20 8° 0° .004 .004 .008 A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc N E1 DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX DIM A2 A C H A1 bxN bbb C A-B D c GAGE PLANE 0.25 SEE DETAIL SIDE VIEW L (L1) DETAIL A 01 A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE-H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AC. Land Pattern - TSSOP-20 X DIM (C) G C G P X Y Z Z Y DIMENSIONS INCHES MILLIMETERS (.222) .161 .026 .016 .061 .283 (5.65) 4.10 0.65 0.40 1.55 7.20 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 2004 Semtech Corp. 11 www.semtech.com