SC4510
High Performance Synchronous Buck
Controller With Reference Tracking
POWER MANAGEMENT
Description
Features
The SC4510 can be configured as a synchronous buck
convertor capable of sourcing and sinking current from load
without losing output regulation. The output can be set to
track an internal reference or an external voltage. The
actual reference used by the error amplifier is buffered
and brought out as a reference. It is the ideal choice for
externally referenced or tracking buck convertors such as
those for DDR memory applications.
u Synchronous buck operation with current sink or
The controller is also designed for point of use DC-DC
convertors with 2.5-16V power sources with a Vcc of 4.5V
or higher. Soft start, current limit, programmable oscillator
and external compensation functions are provided to
ensure high degree of integration and low external
component count. Semetch’s patented Combi-Sense™
technique is utilised for lossless current sening and
maximising efficiency. Both high and low side MOSFET
drivers are built in and rated for substantial peak currents
to minimise switching losses. The SC4510 is offered in a
space saving TSSOP-20 package.
u
u
u
u
u
u
u
u
u
source without loss of regulation
Output can track internal or external reference
Buffered reference output from external reference
Combi-Sense mode lossless current sensing
2.5V to 16V operation with 4.75V minimum VCC
Direct drive for high side N-channel MOSFETs with
diode and capacitor bootstrap
Undervoltage lockout, Soft Start, Enable and Power
Good functions
Fast transient response with external compensation
Current mode control with transconductance error
amplifier
Programmable oscillator frequency with external sync
Applications
u Externally referenced buck convertors
u DDR memory terminators
u Point of use power supplies
Typical Application Circuit
VIN
Q1
15V MAX
C1
C2
D1
R1
RTN
L1
VOUT
C3
0.5V MIN
Q2
C4
C5
R2
R3
C6
R4
C7
SYNC
11
GDH
12
PGND
R6
R7
10
GDL
9
PVCC
8
AVCC
7
PGOOD
6
CS5
BST
13
VPN
14
VIN
15
SS/EN
16
ROSC
17
INCS+
R5
U1
SC4510
4
18
COMP
REFOUT
3
19
2
1
REF
C8
REFIN
AGND
SYNC
20
RTN
PGOOD
INT REF
IN+
C9
REFOUT
EXT REF
C10
Revision: Jan 07, 2005
C11
C12
C13
United States Patent #6,441,597
1
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SC4510
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in
the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device
reliability.
Parameter
Symbol
Maximum
BST, GDH to PGND
Units
-0.3 to 32 (steady state)
V
-0.3 to 40
(for < 10ns @ freq. < 500kHz)
PVCC, AVCC, VIN, VPN, GDL to PGND
-0.3 to 16
V
±0.3
V
-0.3 to AVCC
V
COMP, IN-, REFIN, REFOUT, ROSC, SS/EN to AGND
-0.3 to 6
V
REFIN and REFOUT to AGND
0 to 3.0
V
GDH Source or Sink Current
+ 0.75
A
GDL Source or Sink Current
+1
A
Storage Temperature Range
-60 to +150
°C
Junction Temperature
-40 to +125
°C
260
°C
2
kV
PGND to AGND
CS+ to AGND
Lead Temperature ( Soldering ) 10 Sec.
ESD Rating ( Human Body Model )
Electrical Characteristics
Unless specified: TA = TJ = -40°C to +85°C, AVCC/PVCC = 12V, Fosc = 300 kHz, SS/EN = 5V
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
8
12
mA
Power Supply
Operating Current
No load on GDL and GDH
Analog Supply Input
AVCC
VIN > 2.5V
4.75
16
V
Drive Supply Input
PVCC
VIN > 2.5V
4.75
16
V
VIN
2.5
16
V
AVCCMIN
4.2
4.7
V
Convertor Power Input
Undervoltage Lockout
Start Threshold
UVLO Hysteresis
4.5
AVCCHYST
0.2
V
Charge Current
ISSCHG
2
µA
Discharge Current
ISSDIS
1
µA
Output Enable Threshold
VENTH
Shutdown Threshold
VSSTH
Soft Start and Shudown
2004 Semtech Corp.
2.0
V
0.6
2
V
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SC4510
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: TA = TJ = -40°C to +85°C, AVCC/PVCC = 12V, Fosc = 300 kHz, SS/EN = 5V
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
0.4
0.7
µA
2.5
mV
Error Amplifier
Input Bias Current
Input Offset Voltage
Transconductance Gain
GM
Output Source Mode
Output Sink Mode
Unity Gain Bandwidth (1)
Output Sink/Source Current
VCOMP = 2.5V
275
375
µΩ−1
3
MHz
15
µA
Buffered Reference
Internal reference
VREF
Line regulation
-40C to +85C
0.49
5V < AVCC < 15V
External reference input range
VREFOUT
Reference output current
IREFOUT
0.51
0.02
0.3
VREFIN
Tracking accuracy
0.5
With respect to VREFIN
(Greater of the two)
V
%/V
3.0
V
+ 0.5
+10.0
%
mV
5
mA
Oscillator and Synchronisation
Frequency range
Fosc
Frequency setting
Fosc
0.1
ROSC = 221K
Sync input High voltage
270
300
1
MHz
330
KHz
1.5
V
Sync input Low voltage
0.5
V
Duty Cycle
Maximum Duty Cycle
Fosc = 1 MHz
70
%
Fosc = 300 kHz
90
%
Minimum Duty Cycle
Fosc = 100 kHz
5
%
Minimum pulse width
Fosc = 0.1 to 1 MHz
250
nS
Current Limit
Current limit sense threshold
Delay to Output
(1)
2004 Semtech Corp.
VCSLIM
tCSDLY
Output source mode
60
75
90
mV
Output sink mode
-85
-110
-130
mV
10 mV Overdrive
3
50
nS
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SC4510
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: TA = TJ = -40°C to +85°C, AVCC/PVCC = 12V, Fosc = 300 kHz, SS/EN = 5V
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Overvoltage sense threshold
VOVTH
REFIN = 2.5V
2.8
V
Undervoltage sense threshold
VUVTH
REFIN = 2.5V
2.2
V
VPG
IPG = 5 mA
IPG = 2.5 mA
Output under fault
1.5
High Side Gate Drive
IGDH
Source or sink
1
A
Low Side Gate Drive
IGDL
Source or sink
1
A
Power Good Output
Power Good voltage
V
V
0.4
Output Drive
Dead Time Between Drives
60
90
120
nS
Rise Time
COUT = 1000 pF
20
nS
Fall Time
COUT = 1000 pF
20
nS
Note:
(1) Guaranteed by design. Not tested in production.
Ordering Information
Part Number
Pin Configuration
Package(1)
Temp. Range (TJ)
TSSOP-20
-40°C to +85°C
TOP VIEW
SC4510ITSTR
SC4510ITSTRT(2)
Notes:
(1) Only available in tape and reel packaging.
A reel contains 2500 devices.
(2) Lead free product. This product is fully WEEE and RoHS
compliant.
REF
1
20
AGND
REFIN
2
19
SYNC
REFOUT
3
18
COMP
CS+
4
17
IN-
CS-
5
16
ROSC
PGOOD
6
15
SS/EN
AVCC
7
14
VIN
PVCC
8
13
VPN
GDL
9
12
BST
10
11
GDH
PGND
(20 Pin TSSOP)
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SC4510
POWER MANAGEMENT
Pin Descriptions
Pin #
Pin Name
1
REF
2
REFIN
3
REFOUT
4
CS+
Current sense input +ve
5
CS-
Current sense input -ve. Typically connected to the VOUT end of the output inductor.
6
PGOOD
7
AVCC
Supply voltage for internal analog circuits.
8
PVCC
Supply voltage for output drivers. Bypass with a large ceramic capacitor to PGND.
9
GDL
10
PGND
11
GDH
Gate drive output for the high side N-Channel MOSFET.
12
BST
Boost capacitor connection for the high side gate drive.
Connect an external capacitor and a diode as shown in the Typical Application Circuit.
13
VPN
Virtual Phase Node. Auxiliary pin used for virtual current sense.Connect an RC between this
pin and the VOUT end of the output inductor to sense the integrated current feedback signal.
14
VIN
Input supply for the virtual current sense circuit.
This should be at the same potential as the drain of the high side power MOSFET.
15
SS/EN
Soft Start and Enable pin. Grounding the pin shuts down the controller. Connect a capacitor to
soft start the output.The output will start switching when the SS pin voltage goes above 0.5V.
16
ROSC
Connect a resistor to AGND to program the oscillator frequency.
17
IN-
18
COMP
Error amplifier output for compensation.
19
SYNC
Pin for external synchronisation signal input
20
AGND
Analog signal ground. Return the ground connections of noise sensitive components such as
ROSC, soft start capacitor, sync signal, feedback resistor chain and feedback compensation
components separately to this pin.
2004 Semtech Corp.
Pin Function
Internal 0.5V bandgap reference
Non inverting input of the error amplifier. Can be connected to REF pin or an external voltage
such as VDDQ/2. Maximum input range is 3V
Buffered reference output fro external use. Tracks the REFIN voltage
Power Good output signal. Open collector output goes low under fault and sinks up to 5 mA.
Monitors the output at thresholds of + 12% with respect to REFIN voltage.
Gate drive output for the low side N-Channel MOSFET.
Power ground for returning the drive currents.
Inverting feedback input for the error amplifier. Follows the reference input provided at the
REFIN pin. Maximum voltage range is 3V.
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SC4510
POWER MANAGEMENT
Characteristic Curves
Operating Frequency vs ROSC
1000
11.5
900
11
800
Freq in kHz
Ibias mA
AVCC vs Bias Current
12
10.5
10
9.5
9
700
600
500
400
300
8.5
200
8
100
4.5
5
6
7
8
9
10
11
12
13
14
15
0
100
200
300
400
500
600
700
ROSC in kOhm
AVCC
Typical Dmax vs Operating Frequency
100
Typical Dmax %
95
90
85
80
75
70
100
250
400
550
700
850
1000
Operating Frequency kHz
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SC4510
POWER MANAGEMENT
Characteristic Curves
Internal Reference vs Temperature
Current Limit vs Temperature
74.50
500.50
74.00
Current Limit (mV)
Internal Ref. (mV)
500.00
499.50
499.00
73.50
73.00
72.50
72.00
498.50
71.50
71.00
498.00
-40 -30 -20 -10 0
-40 -30 -20 -10
10 20 30 40 50 60 70 80 90
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
Temperature (°C)
Frequency vs Temperature
@ ROSC = 220K
Max Duty Cycle vs Temperature
@ ROSC = 220K
94.30
300.50
94.25
Frequency in kHz
Max Duty Cycle (%)
300.00
94.20
94.15
94.10
94.05
94.00
93.95
299.50
299.00
298.50
298.00
93.90
93.85
297.50
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
-40 -30 -20 -10
Temperature (°C)
2004 Semtech Corp.
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
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SC4510
POWER MANAGEMENT
Block Diagram
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SC4510
POWER MANAGEMENT
Application Schematic
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SC4510
POWER MANAGEMENT
Functional Description
INTRODUCTION
In tracking applications such as DDR memories an external
reference may be brought in and applied at REFIN pin. The
range of applicable external voltage is up to 3V. The UV
and OV sensing thresholds for PGOOD output are centered
+12% around REFIN voltage.
The SC4510 is designed to control and drive N-Channel
MOSFET synchronous rectified buck convertors. It has
additional features such as reference tracking, buffered
REFOUT that make it particularly attractive for tracking
output applications such as DDR memories. It can operate
the convertor in both the source and sink modes. The
switching frequency is programmable to optimize design.
The current mode switching regulator section features
Semtech’s patented Combi Sense technique for lossless
current sensing and provides a hiccup mode overcurrent
protection.
The voltage at REFIN pin is buffered and put out as REFOUT.
This output tracks REFIN accurately within + 10 mV offset
or 0.5% of REFIN, whichever is higher. It can also source
up to 5 mA current. The REFOUT output is particularly useful
in DDR memory termination applications.
OSCILLATOR
The switching frequency FOSC of the SC4510 is set by an
external resistor using the following formula:
POWERING THE CONTROLLER
Supplies VIN, PVCC and AVCC from the input source are
used to power the SC4510. The AVCC and PVCC can be
tied to VIN supply or can be from separate source to
optimise efficiency. The AVCC supply provides the bias for
the oscillator, PWM switcher, voltage feedback, current
sense and the Power OK circuitry. PVCC is used to drive
the low and high side MOSFET gates. Minimum operating
limit for VIN is 2.5V typical. However, PVCC and AVCC have
higher UVLO limits as explained below. Maximum range
for all of the input and supply voltages is 16V.
ROSC = 66,000 / FOSC
ROSC is in kΩ and FOSC is in kHz. The nominal range for the
oscillator frequency is from 100 kHz to 1 MHz. The
maximum duty cycle available at any given frequency is
limited by minimum pulse width requirement which is
typically 250 nS. This gives a typical Dmax of 70% at the
highest frequency of 1 MHz or about 90% at 300 kHz.
The oscillator can be synchronised to an external clock that
is nominally faster than the internal frequency set by ROSC.
The synchronising signal should be TTL compatible, with
transitions above 2.0V and below 0.6V. The external voltage
level applied should be lower than AVCC of the device.
STARTUP AND ENABLE
Startup is inhibited until AVCC input reaches its UVLO
threshold . The UVLO limit is 4.5V typical. When AVCC is
below the UVLO threshold, the soft start pin is pulled low
and output drivers are turned off. The power up sequence
is initiated by a 2 uA current source charging the soft start
capacitor connected to the SS pin. When the SS pin reaches
0.5V, the convertor will start switching. The reference input
of the error amplifier is ramped up with the soft-start signal.
The soft start duration is controlled by the value of the SS
cap. The soft start pin also functions as an enabler with
TTL compatible input thresholds. If the SS/EN pin is pulled
below 0.6V, the SC4510 is disabled and draws very low
current.
GATE DRIVERS
The low side gate driver is supplied from PVCC and provides
a peak source/sink current of 1A. The high side gate drive
is capable of sourcing and sinking peak currents of 0.75A.
Protection logic provides a typical dead time of 90 nS to
ensure both the upper and lower MOSFETs will not turn on
simultaneously and cause a shoot through condition.
The high side Mosfet gate drive can be derived from the
PVCC supply using the classical bootstrap technique as
illustrated in the applications circuits. A bootstrap capacitor
is connected from BST to the Phase node while PVCC is
connected through a low VF Schottky or an ultrafast diode
to the BST. This will provide a gate to source voltage
approximately equal to the (VCC - Vfwd).
REFERENCE INPUT AND BUFFERED OUTPUT
The SC4510 comes with a low level built in reference of
0.5V. The non inverting input of the error amplifier is
brought out to provide additional flexibility and output
tracking functions. In the basic operation, the REF and
REFIN pins may be shorted together and the output voltage
feedback is provided at IN- pin.
2004 Semtech Corp.
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SC4510
POWER MANAGEMENT
Functional Description
Alternately if an external 12V supply is available it can be
directly connected between BST and GND. The actual gate
to source voltage of the upper Mosfet will then be
approximately be equal to (12V - VIN). This technique is
useful if the input voltage is 5V but a 12V supply is also
available in the system.
POWER GOOD MONITOR
The PGOOD circuitry monitors the FB input of the convertor
error amplifier. If the voltage on this input goes above +12%
or below -12% of the REFIN voltage the PGOOD pin is pulled
low. The PGOOD is an open drain output and can sink up
to 5 mA. The PGOOD pin is held low during the startup
sequence.
ERROR AMPLIFIER
The SC4510 is a current mode controller and operates by
matching the peak of the sensed inductor current to the
output of the voltage error amplifier. The error amplifier is
transconductance type and should be compensated
accordingly. It has a transconductance gain of 275 µΩ−1
in the source mode. Current is sensed losslessly by taking
the weighted average of both the MOSFET drops and adding
it to the DC voltage drop across the inductor. More
information on this patented Combi Sense technique is
provided in the next section.
Current mode controllers are inherently unstable at duty
ratios above 50% and need some form of slope
compensation to operate correctly. This slope
compensation is built into the architecture of SC4510 where
a portion of the ramp is internally added to the current
sense signal. The amount of added ramp is optimised and
varies with the operating duty cycle. Larger duty ratios result
in larger ramps being added to the current sense signal.
Note that the uncorrected current signal is used for
overcurrent comparator. The current limit point is
unaffected by the slope compensation.
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SC4510
POWER MANAGEMENT
Application Information
COMBI-SENSE OPERATION AND CURRENT LIMIT
When Q1/Q3 turn OFF and Q2/Q4 turn ON, the equivalent
circuit of Fig.1 becomes the sub-circuit as shown in Fig.
2b). Where Rds2 is the channel resistance of the bottom
MOSFET. In this case, the branch {Rs,Cs} is in parallel with
{(Rds2+RL), L} and VCs=(Rds2+RL)Io.
Effective current sensing is important for the current mode
control of power convertors. Instead of using the traditional
lossy resistive current sense scheme, a novel lossless
Combi-Sense technique is used in SC4510. This SEMTECH
proprietary technology has the advantages of
1) lossless current sensing,
Vin
Rds1
2) bigger signal-to-noise ratio, and
3) thermal run-away prevention.
iL(t)
L
RL
Rs
Cs
PN
Cin
The basic structure of the Combi-Sense is shown in Fig.1.
Where RL is the equivalent resistance of the output inductor.
The added Rs and Cs form the RC branch in “parallel” with
the output inductor for inductor current sensing. This
branch works with a small signal totem pole (Q3 and Q4)
integrated in SC4510 in order to improve the signal-to-noise
ratio. The base signals Vbe3 and Vbe4 are designed to
closely follow the gate signals Vgs1 and Vgs2, respectively.
Ideally, the leading and falling edges of the Virtual Phase
Node (VPN) follow that of the Phase Node (PH) when Q1~Q4
switch in perfect synchronism.
Vo
VPN
Cout
Rload
vC(t)
Fig.2 a) Equivalent sub-circuit.
When averaged over a complete cycle,
VCs = [D(Rds1+RL)+(1-D)(Rds2+RL)] Io
= [D Rds1+(1-D)Rds2+RL]Io
= ReqIo.
Vin
Q1
D is the operating duty ratio. It is noted that the average
DC value in VCs is independent of the value of L, Rs and Cs.
If only the average load current information is needed (such
as in average current mode control), this current sensing
method is effective without further requirements.
Vgs1
iL(t)
L
RL
Rs
Cs
PN
Cin
Vo
Q2
Rload
vC(t)
Vgs2
Vbe3
Cout
Q3
VPN
Vbe4
Vin
Q4
iL(t)
PN
Cin
Fig.1 The Basic Structure of Combi-Sense.
When Q1/Q3 turn ON and Q2/Q4 turn OFF, the equivalent
circuit of Fig.1 is shown in Fig. 2a). Where, Rds1 is the onresistance of the top MOSFET. The two branches, consisting
of {(Rds1+RL), L} and {Rs, CS}, are in parallel. The DC voltage
drop (Rds1+RL)Io equals VCs. In this way, the output current
is sensed from VCs when (Rds1+RL) is known.
2004 Semtech Corp.
Rds2
L
RL
Rs
Cs
Vo
VPN
Cout
Rload
vC(t)
Fig.2 b) Equivalent sub-circuit.
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SC4510
POWER MANAGEMENT
Application Information (Contd.)
In peak current mode control as in SC4510, the voltage
ripple on Cs is critical for PWM operation. In fact, the peakto-peak value of the voltage ripple across VCs (denoted as
∆VCs) directly affects the signal-to-noise ratio of the PWM
operation. In general, smaller ∆VCs leads to small signal-tonoise ratio and more noise sensitive operation. Larger ∆VCs
leads to more circuit (power stage) parameter sensitive
operation. A good engineering compromise is to make
In the application circuit, Req=5.6 mΩ. However the peak
value of the sensed current is not exact for a number of
reasons. Though the Phase Node PH and Virtual Phase
Node VPN voltages are assumed to be identical, there will
be some offset between them which adds to the average
value of the current feedback signal. This is particularly
true during the switching transitions where rise and fall
times of the true Phase Node are dependent on the power
MOSFET characteristics. The peak value of the signal also
∆VCs~Req∆ Io.
includes the ripple current ∆ Io riding on the output DC
current. In addition, the signal level is subject to variations
with respect to input and PVCC voltages. The difference
between sensed current magnitude and the actual current
gets more pronounced for low output voltages where the
operating duty is also low.
Where ∆ Io is the peak to peak ripple current in the inductor.
The prerequisite for such relation is the so called time
constant matching condition
L
≈ RsC s .
R eq
Given these differences, some amount of scaling the
current sense signal is required to adjust the current limit
in most applications. This can be accomplished easily by
simple resistor networks and the possible configurations
are shown in Fig.3.
When Rds1 = Rds2, the above approximations become
precise equalities. For the example in the Application Circuit
shown on p9 the inductor value is 1 uH,
RL= 1.4 mΩ , Rds1 = 11 mΩ and Rds2 = 3 mΩ
a) When the required current limit value ILM is greater than
ILMcp, remove Rs3 and solve for for Rs2 = Rseq and
Since the operating duty ratio is very small the effective
Rds is determined mostly by Rds2. The time constant RsCs
should be set close to 0.2 mS. Since the effective value of
Rs is 20 kΩ // 18 kΩ = 9.5 kΩ, Cs= 22 nF was chosen .
R seq C s =
L
R eq
Rseq is the parallel combination of Rs and Rs1 as shown in
Fig 3). Rs2 helps to reduce the offset at the input of current
sense amplifier inside SC4510.
CURRENT LIMIT SCALING
In SC4510, the current limiting is performed on cycle-bycycle basis. When the voltage difference between CS+ and
CS- exceeds 65 mV, the top MOSFET duty ratio is clipped
in order to limit the output source current. Similarly, when
the voltage difference between CS- and CS+ exceeds 113
mV, the bottom MOSFET duty ratio is clipped in order to
limit the sink current. For the configuration in Fig.1, the
convertor output current limit is set around
Vin
Q1
Vgs1
iL(t)
L
RL
PN
Cin
Rs
Rs1
Vo
Q2
Cs
Cout
Rload
Vgs2
vC(t)
I LMcp =
75 mV
,
Req
Vbe3
Vbe4
for the current sourcing mode and
I LMcn = −
110 mV
Req
ISEN
Q4
+
1
-
2
Rs2
Rs3
for the current sinking mode.
2004 Semtech Corp.
Q3
VPN
Fig.3 Current limit scaling.
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SC4510
POWER MANAGEMENT
Application Information (Contd.)
For simplicity Rs2 can be omitted and the current limit can
be estimated from
a) The time it takes to discharge the capacitor from 3.4V to
0.4V
R +R
I LM R eq = 75 mV × sR s1
tssf = CSS ×
s1
In the application circuit the current feedback signal had
to be halved to account for variations explained above and
ensure that the current limit is at least 20% above nominal
at minimum input.
In the application circuit, CSS= 47 nF and tssf is calculated
as 140 mS.
b) The time interval of the soft start process from 0.4V to
3.4V
b) When the required current limit value ILM is less than
ILMcp remove Rs1 solve
R sC s =
(3.4 − 0.4)V
.
1 µA
tssr = C SS ×
L
R eq
( 3 .4 − 0 .4 ) V
.
2 µA
for Rs and solve
When CSS = 47 nF, tssr is calculated as 70 mS.
R
I LM Req + s Vo = 75 mV
Rs 3
Notice that during the soft start process, the convertor only
starts switching when the voltage at SS/EN exceeds 1.3V.
Then,
to set the current limit.
Similar steps and equations apply to the current limit setting
and scaling for current sinking mode.
c) The effective operation time interval
t sso = C SS ×
OVERCURRENT PROTECTION AND HICCUP MODE
In addition to the current limit capabilty, SC4510 provides
overcurrent protection in case the convertor output is
shorted to ground. If this fault condition happens, the
controller senses the output voltage via voltage feedback
pin IN-. When the sensed voltage is below 70% of the
normal feedback voltage, the controller shuts down both
top and bottom MOSFETs. At the same time, a current sink
of 1 µA discharges the soft start capacitor CSS connected
to the SS/EN pin.
This is the interval where the gate drive outputs are active
and current builds up in the inductor.
The effective inductor current is then
I Leff = I LMcp
When the capacitor is discharged until its voltage reaches
0.4V, the controller initiates the soft start process. If the
short circuit fault persists, the controller shuts down the
convertor again when the voltage across the soft start
capacitor reaches 3.4V. This hiccup process repeats until
the fault condition is removed. Under this situation, it is
important to make sure that the convertor does not fail.
One important parameter is the convertor thermal condition
which is directly related to the effective inductor and
MOSFETs current. The effective currents in inductor and
MOSFETs can be estimated using the following equations.
2004 Semtech Corp.
( 3 .4 − 1 .3) V
.
2 µA
t sso
.
t ssf + t ssr
It turns out that ILeff is independent of the soft start
capacitor value and is determined as 0.3ILMcp. This should
lead to a reasonable thermal condition in the convertor
hiccup operation. Note that ILeff calculated is not the true
average value of the inductor current since the convertor
is still in the soft start mode during the tsso interval.
14
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SC4510
POWER MANAGEMENT
Application Information (Contd.)
5) The SC4510 is best placed over a quiet ground plane
area. Avoid pulse currents of the Cin, Q T, QB loop flowing in
this area. This analog ground plane should be connected
to the power ground plane at a “quiet” point near the input
capacitor. Under no circumstance should it be returned to
a point inside the Cin, QT, QB, Cout power ground loops.
PCB LAYOUT FOR SC4510
Careful attention to layout requirements is necessary for
successful implementation of the SC4510 PWM controller.
High switching currents with fast rise and fall times are
present in the application and their effect on ground plane
voltage differentials must be understood and minimized.
A good layout with minimum parasitic loop areas will
6) The SC4510 AGND pin is connected to the separate
analog ground plane with minimum lead length . All analog
grounding paths including decoupling capacitors, feedback
resistors, compensation components, soft start capacitor,
frequency and current-limit setting resistors should be
connected to the same plane.
a) reduce EMI
b) lower ground injection currents, resulting in electrically
“cleaner” grounds for the rest of the system and
c) minimize source ringing, resulting in more reliable gate
switching signals.
7) Locate the critical filtering capacitors as close as possible
to their respective device. This is particularly true for the
current feedback filtering capacitor connected between
CS+ and CS-. A high value ceramic capacitor is also
recommended between PVCC and PGND pins close to the
device.
LAYOUT GUIDELINES
In the following QT and QB denote the high side and low
side MOSFETs respectively.
1) A ground plane should be used. The number and position
of ground plane interruptions should be minimised so as
not to compromise ground plane integrity. Isolated or semiisolated areas of the ground plane may be deliberately
introduced to constrain ground currents into particular
paths, such as the output capacitor or the QB source.
2) The high power, high current parts of the circuit should
be laid out first. The on time loop formed by the input
capacitor Cin, the high side FET QT, the output inductor and
the output capacitor bank Cout must be kept as small as
possible. Another loop area to minimise is formed by low
side FET QB, the output inductor and the output capacitor
bank Cout during the off period. These loops contain all
the high current, fast transition switching. Connections
should be as wide and as short as possible to minimize
loop inductance.
3) The connection between the junction of QT, QB and the
output inductor should be a wide trace or copper region. It
should be as short as practical. Since this connection has
fast voltage transitions, keeping this connection short will
minimize EMI. Also keep the Phase connection to the IC
short. The top FET gate charge currents flow in this trace.
4) The output capacitor Cout should be located as close to
the load terminals as possible. Fast transient load currents
are supplied by Cout and connections between Cout and
the load must be kept short with wide copper areas to
minimize inductance and resistance. This will improve the
transient response to step loads.
2004 Semtech Corp.
15
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SC4510
POWER MANAGEMENT
Outline Drawing - TSSOP-20
A
D
e
2X E/2
E
PIN 1
INDICATOR
ccc C 1 2 3
2X N/2 TIPS
e/2
B
1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
6.40 6.50 6.60
4.30 4.40 4.50
6.40 BSC
0.65 BSC
0.45 0.60 0.75
(1.0)
20
0°
8°
0.10
0.10
0.20
D
aaa C
SEATING
PLANE
.047
.006
.002
.042
.031
.012
.007
.007
.003
.251 .255 .259
.169 .173 .177
.252 BSC
.026 BSC
.018 .024 .030
(.039)
20
8°
0°
.004
.004
.008
A
A1
A2
b
c
D
E1
E
e
L
L1
N
01
aaa
bbb
ccc
N
E1
DIMENSIONS
INCHES
MILLIMETERS
MIN NOM MAX MIN NOM MAX
DIM
A2 A
C
H
A1
bxN
bbb
C A-B D
c
GAGE
PLANE
0.25
SEE DETAIL
SIDE VIEW
L
(L1)
DETAIL
A
01
A
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B-
TO BE DETERMINED AT DATUM PLANE-H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MO-153, VARIATION AC.
Land Pattern - TSSOP-20
X
DIM
(C)
G
C
G
P
X
Y
Z
Z
Y
DIMENSIONS
MILLIMETERS
INCHES
(.222)
.161
.026
.016
.061
.283
(5.65)
4.10
0.65
0.40
1.55
7.20
P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
2004 Semtech Corp.
16
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