EMIF01-1003M3 1 line IPAD™, EMI filter and ESD protection in Micro QFN package Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Single line EMI symmetrical (I/O) low-pass filter High efficiency in EMI filtering Very low PCB space consumption: 1.0 mm x 0.6 mm Very thin package: 0.6 mm max High efficiency in ESD suppression (IEC 61000-4-2 level 4). High reliability offered by monolithic integration High reduction of parasitic elements through integration and wafer level packaging. Lead free package Easy layout and flexibility due to single line topology Low capacitance SOT-883 (JEDEC MO-236AA compliant) Figure 1. IN Complies with following standards ■ IEC 61000-4-2 level 4 input and output pins – 15 kV (air discharge) – 8 kV (contact discharge) ■ MIL STD 883G - Method 3015-7 Class 3B (all pins) Applications Pin configuration (top view) OUT GND Figure 2. Basic cell configuration Where EMI filtering in ESD sensitive equipment is required: ■ Keyboard for mobile phones ■ Computers and printers ■ Communication systems ■ MCU boards Input Output R = 100 Ω CLINE = 30 pF typ. @ 0 V Description The EMIF01-1003M3 is a 1 line highly integrated device designed to suppress EMI/RFI noise in all systems exposed to electromagnetic interference. This filter includes ESD protection circuitry, which prevents damage to the application when subjected to ESD surges up to 15 kV on all pins. October 2007 TM: IPAD is a trademark of STMicroelectronics Rev 1 1/10 www.st.com Characteristics EMIF01-1003M3 1 Characteristics Table 1. Absolute ratings (limiting values at Tamb = 25° C unless otherwise specified) Symbol VPP Parameter Value Unit 15 8 kV ESD discharge IEC61000-4-2 air discharge on input and output pins ESD discharge IEC61000-4-2 contact discharge on input and output pins 125 °C Top Operating temperature range -40 to + 85 °C Tstg Storage temperature range -55 to +150 °C Tj Table 2. Junction temperature Electrical characteristics (Tamb = 25° C) Symbol Parameter I VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage Rd Dynamic resistance IPP Peak pulse current RI/O Series resistance between Input & Output Cline Input capacitance per line Symbol Test conditions IF VBR VCL V IRM IR IPP Min. Typ. 5 6.5 VBR IR = 1 mA IRM VRM = 3 V per line RI/O Tolerance ± 10% 100 Cline VR= 0 VDC, VOSC = 30 mV, F = 1 MHz 30 S21 F = 900 MHz 2/10 VF VRM Max. Unit 8 V 100 nA Ω 39 pF -25 dB EMIF01-1003M3 Figure 3. 0.00 Characteristics S21 attenuation measurement (Vbias = 0 V) dB -5.00 -10.00 -15.00 -20.00 -25.00 F (Hz) -30.00 100.0k 1.0M 10.0M 100.0M 1.0G I-O Figure 4. ESD response to IEC 61000-4-2 (+15 kV air discharge) Figure 5. ESD response to IEC 61000-4-2 (- 15 kV air discharge) INPUT INPUT OUTPUT OUTPUT Figure 6. Line capacitance versus reverse voltage applied (typical value) C LINE (pF) 3.50E+01 3.00E+01 2.50E+01 2.00E+01 1.50E+01 1.00E+01 V R (V) 5.00E+00 0.00E+00 0 1 2 3 4 5 3/10 Application schematic 2 EMIF01-1003M3 Application schematic Figure 7. Application schematic Keypad protection Key_Row_1 IN OUT GND Key_Row_2 IN OUT GND Key_Col_y IN OUT GND 3 Ordering information scheme Figure 8. Ordering information scheme EMIF EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) Package M3 = SOT-883 4/10 yy - xxx z Mx EMIF01-1003M3 4 Package information Package information ● Epoxy meets UL94, V0 In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Table 3. SOT-883 dimensions Dimensions E Ref. Min. D A A1 L b L1 2 3 e Millimeters b1 Typ. Inches Max. Min. Typ. Max. A 0.45 0.50 0.18 0.2 A1 0.00 0.05 0.00 0.02 b 0.10 0.15 0.20 0.04 0.06 0.08 b1 0.45 0.50 0.55 0.18 0.20 0.22 D 0.60 0.24 E 1.00 0.39 e 0.35 0.14 e1 0.65 0.26 1 e1 Figure 9. L 0.20 0.25 0.30 0.08 0.10 0.12 L1 0.20 0.25 0.30 0.08 0.10 0.12 Footprint (dimensions in mm) Figure 10. Marking 0.40 0.40 2 F 0.50 0.20 0.15 0.40 3 1 5/10 Package information EMIF01-1003M3 Figure 11. Tape and reel specification 3.5 ±- 0.05 F F F 0.70 ± 0.05 F F 6/10 F Note: F All dimensions in mm 1.15 ± 0.05 8.0 ± 0.3 0.55 ± 0.05 Ø 1.55 ± 0.05 4.0 ± 0.1 1.75 ± 0.1 2.0 ± 0.05 2.0 ± 0.1 User direction of unreeling Product marking may be rotated by 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. EMIF01-1003M3 Recommendation on PCB assembly 5 Recommendation on PCB assembly 5.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 12. Stencil opening dimensions L T b) W General Design Rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = ----- ≥ 1.5 T L×W Aspect Area = ---------------------------- ≥ 0.66 2T ( L + W ) 2. 5.2 Reference design a) Stencil opening thickness: 100 µm b) Stencil opening for leads: Opening to footprint ratio is 90%. Solder paste 1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste is recommended. 3. Offers a high tack force to resist component movement during high speed 4. Solder paste with fine particles: powder particle size is 20-45 µm. 7/10 Recommendation on PCB assembly 5.3 5.4 5.5 EMIF01-1003M3 Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. Reflow profile Figure 13. ST ECOPACK® recommended soldering reflow profile for PCB mounting Temperature (°C) 260°C max 255°C 220°C 180°C 125 °C 2°C/s recommended 2°C/s recommended 6°C/s max 6°C/s max 3°C/s max 3°C/s max 0 0 1 2 3 4 5 10-30 sec 90 to 150 sec Note: 8/10 6 7 Time (min) 90 sec max Minimize air convection currents in the reflow oven to avoid component movement. EMIF01-1003M3 6 Ordering information Ordering information Table 4. Ordering information Part number Marking Package Weight Base qty Delivery mode EMIF01-1003M3 F(1) SOT-883 0.96 mg 3000 Tape and reel (7”) 1. The marking can be rotated by 90° to diferentiate assembly location 7 Revision history Table 5. Document revision history Date Revision 07-Oct-2007 1 Changes Initial release. 9/10 EMIF01-1003M3 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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