STMICROELECTRONICS EMIF04

EMIF04-1502M8
4-line IPAD™
low capacitance EMI filter and ESD protection in micro QFN package
Features
■
EMI asymmetrical (I/O) low-pass filter
8
■
High efficiency in EMI filtering
7
■
Very low PCB space consumption:
1.7 mm x 1.5 mm
6
3
5
4
■
Very thin package: 0.6 mm max
■
High efficiency in ESD suppression on input
pins (IEC 61000-4-2 level 4)
■
High reliability offered by monolithic integration
■
High reducing of parasitic elements through
integration and wafer level packaging
■
Lead-free package
■
G ND
2
GND
Micro QFN 1.7 mm x 1.5 mm
(bottom view)
Figure 1.
Complies with following standards:
■
1
Pin configuration (top view)
1 Input
Output 8
2 Input
Output 7
IEC 61000-4-2 level 4 input pins
– 15 kV (air discharge)
– 8 kV (contact discharge)
3 Input
Output 6
MIL STD 883G - Method 3015-7 Class 3A
(all pins)
4 Input
Output 5
Applications
Where EMI filtering in ESD sensitive equipment is
required:
■
LCD and camera for mobile phones
■
Computers and printers
■
Communication systems
■
MCU boards
Figure 2.
Input
Basic cell configuration
170 Ω
Output
Typical line capacitance = 14 pF @ 2.5 V
Description
The EMIF04-1502M8 is a 4-line, highly integrated
device designed to suppress EMI/RFI noise in all
systems exposed to electromagnetic interference.
This filter includes an ESD protection circuitry,
which prevents damage to the application when
subjected to ESD surges up to 15 kV on the input
pins.
February 2008
TM: IPAD is a trademark of STMicroelectronics
Rev 5
1/10
www.st.com
Characteristics
EMIF04-1502M8
1
Characteristics
Table 1.
Absolute ratings (limiting values at Tamb = 25° C unless otherwise specified)
Symbol
VPP
Tj
Parameter
Value
Unit
ESD IEC 61000-4-2 air discharge on input pins
ESD IEC 61000-4-2 contact discharge on input pins
ESD IEC 61000-4-2 contact discharge on output pins
15
8
4
kV
Junction temperature
125
°C
Top
Operating temperature range
-40 to + 85
°C
Tstg
Storage temperature range
-55 to +150
°C
Table 2.
Electrical characteristics (Tamb = 25° C)
Symbol
Parameter
I
VBR
Breakdown voltage
IRM
Leakage current @ VRM
VRM
Stand-off voltage
VCL
Clamping voltage
Rd
Dynamic resistance
IPP
Peak pulse current
RI/O
Series resistance between Input & Output
Cline
Input capacitance per line
IF
VBR
VCL
VF
VRM
V
IRM
IR
Symbol
IPP
Test conditions
Min.
Typ.
Max.
Unit
6
8
10
V
100
nA
VBR
IR = 1 mA
IRM
VRM = 3 V per line
RI/O
Tolerance ± 10%
153
170
187
Ω
Cline
VLINE = 2.5 V dc, VOSC = 30 mV, F = 1 MHz
12
14
16.5
pF
Figure 3.
0.00
S21 attenuation measurement
Figure 4.
Analog cross talk measurements
dB
dB
0.00
-10.00
-20.00
-30.00
-15.00
-40.00
-50.00
-60.00
-30.00
-70.00
-80.00
F (Hz)
-45.00
100.0k
2/10
1.0M
10.0M
F (Hz)
-90.00
100.0M
1.0G
-100.00
100.0k
1.0M
10.0M
100.0M
1.0G
EMIF04-1502M8
Figure 5.
Ordering information scheme
ESD response to IEC 61000-4-2
Figure 6.
(+15 kV air discharge) on one input
(Vin) and on one output (Vout)
ESD response to IEC 61000-4-2
(- 15 kV air discharge) on one input
(Vin) and on one output (Vout)
Vin
C1 = 10 V/d
C1 = 10 V/d
Vin
Vout
C2 = 5 V/d
100 ns/d
C2 = 5 V/d
Vout
100 ns/d
Figure 7.
Line capacitance versus reverse voltage applied (typical value)
CLINE(pF)
24
22
20
18
16
14
12
10
8
6
4
2
0
VLINE(V)
0.0
2
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Ordering information scheme
Figure 8.
Ordering information scheme
EMIF
yy
-
xxx z
Mx
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
Package
Mx = Micro QFN x leads
3/10
Package information
3
EMIF04-1502M8
Package information
●
Epoxy meets UL94, V0
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at
www.st.com.
Table 3.
QFN 1.7 x 1.5 package dimensions
Dimensions
D
N
Ref
E
1
2
A
1
TYP
MAX
MIN
TYP
MAX
A
0.50
0.55
0.60
0.20
0.22
0.24
A1
0.00
0.02
0.05
0.00
0.01
0.02
b
0.15
0.18
0.25
0.06
0.07
0.10
D2
2
L
E2
0.9
e
Footprint
1.00
0.67
1.10
0.35
1.50
0.30
e
b
0.40
1.70
E
k
inches
MIN
D
A1
Figure 9.
Millimeters
0.40
0.20
L
0.25
0.50
0.12
0.30
0.35
0.10
Dot: Pin 1 Identification
XX= Marking
0.25
2.10
1.00
4/10
0.24
0.08
0.20
0.40
0.16
0.16
Figure 10. Marking
0.60
0.43
0.59
0.40
k
0.39
XX
0.12
0.14
EMIF04-1502M8
Package information
Figure 11. Tape and reel specification
φ 1.5 +/- 0.1
XX
XX
3.5 +/- 0.03
1.90
8.0 +/- 0.3
0.75
4.00+/-0.1
1.75 +/- 0.1
2.0+/-0.05
XX
1.70
4.00
User direction of unreeling
Note:
Product marking may be rotated by 90° for assembly plant differentiation. In no case should
this product marking be used to orient the component for its placement on a PCB. Only pin 1
mark is to be used for this purpose.
5/10
Recommendation on PCB assembly
EMIF04-1502M8
4
Recommendation on PCB assembly
4.1
Stencil opening design
1.
General recommendation on stencil opening design
a)
Stencil opening dimensions: L (Length), W (Width), T (Thickness).
Figure 12. Stencil opening dimensions
L
T
b)
W
General design rule
Stencil thickness (T) = 75 ~ 125 µm
W
Aspect Ratio = ----- ≥ 1.5
T
L×W
Aspect Area = ---------------------------- ≥ 0.66
2T ( L + W )
2.
Reference design
a)
Stencil opening thickness: 100 µm
b)
Stencil opening for central exposed pad: Opening to footprint ratio is 50%.
c)
Stencil opening for leads: Opening to footprint ratio is 90%.
Figure 13. Recommended stencil window position
5 µm
5 µm
0.40
570 µm
600 µm
15 µm
0.20
0.60
190 µm
15 µm
0.25
2.10
0.40
200 µm
1000 µm
400 µm
300 µm
50 µm
1.00
680 µm
Footprint
50 µm
160 µm
6/10
160 µm
Stencil window
Footprint
EMIF04-1502M8
4.2
4.3
4.4
Recommendation on PCB assembly
Solder paste
1.
Halide-free flux qualification ROL0 according to ANSI/J-STD-004.
2.
“No clean” solder paste is recommended.
3.
Offers a high tack force to resist component movement during high speed
4.
Solder paste with fine particles: powder particle size is 20-45 µm.
Placement
1.
Manual positioning is not recommended.
2.
It is recommended to use the lead recognition capabilities of the placement system, not
the outline centering
3.
Standard tolerance of ± 0.05 mm is recommended.
4.
3.5 N placement force is recommended. Too much placement force can lead to
squeezed out solder paste and cause solder joints to short. Too low placement force
can lead to insufficient contact between package and solder paste that could cause
open solder joints or badly centered packages.
5.
To improve the package placement accuracy, a bottom side optical control should be
performed with a high resolution tool.
6.
For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is
recommended during solder paste printing, pick and place and reflow soldering by
using optimized tools.
PCB design preference
1.
To control the solder paste amount, the closed via is recommended instead of open
vias.
2.
The position of tracks and open vias in the solder area should be well balanced. The
symmetrical layout is recommended, in case any tilt phenomena caused by
asymmetrical solder paste amount due to the solder flow away.
7/10
Recommendation on PCB assembly
4.5
EMIF04-1502M8
Reflow profile
Figure 14. ST ECOPACK® recommended soldering reflow profile for PCB mounting
Temperature (°C)
260°C max
255°C
220°C
180°C
125 °C
2°C/s recommended
2°C/s recommended
6°C/s max
6°C/s max
3°C/s max
3°C/s max
0
0
1
2
3
4
5
10-30 sec
90 to 150 sec
Note:
8/10
6
7
Time (min)
90 sec max
Minimize air convection currents in the reflow oven to avoid component movement.
EMIF04-1502M8
5
Ordering information
Ordering information
Table 4.
Ordering information
Order code
Marking
Package
Weight
Base qty
Delivery mode
EMIF04-1502M8
G4(1)
Micro QFN
4 mg
3000
Tape and reel (7”)
1. The marking can be rotated by 90° to differentiate assembly location
6
Revision history
Table 5.
Document revision history
Date
Revision
Changes
12-Dec-2005
1
Initial release.
03-Jul-2006
2
Reformatted to current standard. Changed Figure 1 to show
improved results.
01-Feb-2007
3
Added note on marking rotation in section 3. Package information.
26-Feb-2007
4
Pins range corrected on Micro QFN bottom view picture on page 1.
04-Feb-2008
5
Reformatted to current standards. Updated ECOPACK statement.
Updated Section 4: Recommendation on PCB assembly.
9/10
EMIF04-1502M8
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10/10