EMIF06-1005M12 6-line IPAD™ low capacitance EMI filter and ESD protection in micro QFN package Features 12 1 ■ EMI symmetrical (I/O) low-pass filter 11 2 ■ High efficiency in EMI filtering: -34 dB at frequencies from 900 MHz to 1.8 GHz 10 ■ Very low PCB space consumption: 2.5 mm x 1.5 mm ■ Very thin package: 0.6 mm max ■ High efficiency in ESD suppression on inputs pins (IEC 61000-4-2 level 4) ■ High reliability offered by monolithic integration ■ High reduction of parasitic elements through integration and wafer level packaging ■ GND 3 9 4 8 5 7 6 Micro QFN 2.5 mm x 1.5 mm (bottom view) Figure 1. Pin configuration (top view) 1 Input Output 12 2 Input Output 11 3 Input Output 10 4 Input Output 9 5 Input Output 8 Lead-free package Complies with following standards: ■ ■ IEC 61000-4-2 level 4 input and output pins – 15 kV (air discharge) – 8 kV (contact discharge) MIL STD 883G - Method 3015-7 Class 3B (all pins) 6 Input Applications Output 7 Where EMI filtering in ESD sensitive equipment is required: ■ LCD and camera for mobile phones ■ Computers and printers ■ Communication systems ■ MCU boards Figure 2. Input Description Basic cell configuration 100 Ω Output Typical line capacitance = 45 pF @ 0 V EMIF06-1005M12 is a 6-line, highly integrated device designed to suppress EMI/RFI noise in all systems exposed to electromagnetic interference. This filter includes ESD protection circuitry, which prevents damage to the application when subjected to ESD surges up to 15 kV on the input pins. February 2008 TM: IPAD is a trademark of STMicroelectronics Rev 3 1/10 www.st.com Characteristics EMIF06-1005M12 1 Characteristics Table 1. Absolute ratings (limiting values at Tamb = 25 °C unless otherwise specified) Symbol Parameter Value Unit 15 15 kV ESD IEC 61000-4-2, air discharge ESD IEC 61000-4-2, contact discharge VPP 125 °C Top Junction temperature Operating temperature range -40 to + 85 °C Tstg Storage temperature range -55 to +150 °C Tj Table 2. Electrical characteristics (Tamb = 25 °C) Symbol Parameter I VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage Rd Dynamic resistance IPP Peak pulse current RI/O Series resistance between Input & Output Cline Input capacitance per line IF VBR VCL VF VRM V IRM IR Symbol IPP Test conditions Min. Typ. Max. Unit V VBR IR = 1 mA 6 8 10 VF IF = 10 mA 0.5 1.0 1.5 IRM VRM = 3 V per line 200 nA RI/O Tolerance ± 10% 90 100 110 Ω Cline VLINE = 0 V dc, VOSC = 30 mV, F = 1 MHz 38 45 52 pF Figure 3. 0.00 S21 attenuation measurement dB Figure 4. 0.00 Analog cross talk measurements dB - 10.00 - 20.00 -10.00 - 30.00 - 40.00 -20.00 - 50.00 - 60.00 - 70.00 -30.00 - 80.00 F (Hz) - 90.00 -40.00 100.0k 2/10 1.0M 10.0M 100.0M 1.0G F (Hz) - 100.00 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G EMIF06-1005M12 Ordering information scheme Figure 5. ESD response to IEC 61000-4-2 Figure 6. (+15 kV air discharge) on one input (Vin) and on one output (Vout) Figure 7. Line capacitance versus reverse voltage applied (typical value) (pF) C 50.00 LINE 45.00 40.00 35.00 30.00 25.00 20.00 15.00 10.00 5.00 0.00 0 2 ESD response to IEC 61000-4-2 (- 15 kV air discharge) on one input (Vin) and on one output (Vout) V LINE (V) 1 2 3 4 5 Ordering information scheme Figure 8. Ordering information scheme EMIF yy - xxx z Mx EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) Package Mx = Micro QFN x leads 3/10 Package information 3 EMIF06-1005M12 Package information ● Epoxy meets UL94, V0 In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Table 3. QFN 2.5 x 1.5 package dimensions Dimensions D N Ref E 1 A1 TYP MAX MIN TYP MAX A 0.50 0.55 0.60 0.20 0.22 0.24 A1 0.00 0.02 0.05 0.00 0.01 0.02 b 0.15 0.18 0.25 0.06 0.07 0.10 D2 D2 2 E2 E2 k N b Footprint 0.60 0.25 2.10 1.80 1.80 0.98 1.90 0.67 1.50 0.30 0.40 0.20 L 0.25 0.75 0.59 0.50 0.12 0.40 k 0.71 0.16 0.24 0.16 0.08 0.30 0.35 0.10 0.12 Figure 10. Marking 0.20 0.40 1.70 e e 0.40 2.50 E L 4/10 MIN D 1 inches 2 A Figure 9. Millimeters Dot: Pin 1 Identification X = Marking YWW= Data code (Y=year WW= week XY ww 0.14 EMIF06-1005M12 Package information Figure 11. Tape and reel specification f 1.5 +/- 0.1 3.5 +/- 0.05 2.70 8.1 +/- 0.1 0.75 4.00+/-0.1 1.75 +/- 0.1 2.0+/-0.05 XY ww XY ww 1.70 XY ww 4.00 User direction of unreeling Note: Product marking may be rotated by 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. 5/10 Recommendation on PCB assembly EMIF06-1005M12 4 Recommendation on PCB assembly 4.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 12. Stencil opening dimensions L T b) W General design rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = ----- ≥ 1.5 T L×W Aspect Area = ---------------------------- ≥ 0.66 2T ( L + W ) 2. Reference design a) Stencil opening thickness: 100 µm b) Stencil opening for central exposed pad: Opening to footprint ratio is 50%. c) Stencil opening for leads: Opening to footprint ratio is 90%. Figure 13. Recommended stencil window position 5 µm 5 µm 570 µm 600 µm 15 µm 0.40 0.20 0.60 190 µm 0.25 15 µm 2.10 0.40 200 µm 1800 µm 400 µm 1224 µm Footprint 50 µm 288 µm 6/10 1.80 300 µm 50 µm 288 µm Stencil window Footprint EMIF06-1005M12 4.2 4.3 4.4 Recommendation on PCB assembly Solder paste 1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste is recommended. 3. Offers a high tack force to resist component movement during high speed 4. Solder paste with fine particles: powder particle size is 20-45 µm. Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. 7/10 Recommendation on PCB assembly 4.5 EMIF06-1005M12 Reflow profile Figure 14. ST ECOPACK® recommended soldering reflow profile for PCB mounting Temperature (°C) 260°C max 255°C 220°C 180°C 125 °C 2°C/s recommended 2°C/s recommended 6°C/s max 6°C/s max 3°C/s max 3°C/s max 0 0 1 2 3 4 5 10-30 sec 90 to 150 sec Note: 8/10 6 7 Time (min) 90 sec max Minimize air convection currents in the reflow oven to avoid component movement. EMIF06-1005M12 5 Ordering information Ordering information Table 4. Ordering information Order code Marking Package Weight Base qty Delivery mode EMIF06-1005M12 F(1) Micro QFN 6 mg 3000 Tape and reel (7”) 1. The marking can be rotated by 90° to differentiate assembly location 6 Revision history Table 5. Document revision history Date Revision Changes 3-Jul-2006 1 Initial release. 1-Feb-2007 2 Added note on marking rotation in section 3. Package information. 04-Feb-2008 3 Reformatted to current standards. Updated ECOPACK statement. Updated Section 4: Recommendation on PCB assembly. 9/10 EMIF06-1005M12 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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