STMICROELECTRONICS L6382DTR

L6382D
POWER MANAGEMENT UNIT FOR MICROCONTROLLED
BALLAST
1
■
■
■
■
■
■
■
■
■
2
■
3
FEATURES
Figure 1. Package
INTEGRATED HIGH-VOLTAGE START-UP
4 DRIVERS FOR PFC, HALF-BRIDGE & PREHEATING MOSFETS
3.3V MICROCONTROLLER COMPATIBLE
FULLY INTEGRATE POWER MANAGEMENT
FOR ALL OPERATING MODES
INTERNAL TWO POINT Vcc REGULATOR
OVER-CURRENT PROTECTION WITH
DIGITAL OUTPUT SIGNAL
CROSS-CONDUCTION PROTECTION
(INTERLOCKING)
UNDER VOLTAGE LOCK OUT
INTEGRATED BOOTSTRAP DIODE
SO20
Table 1. Order Codes
Part Number
Package
L6382D
SO20 tube
L6382DTR
SO20 in Tape & Reel
high voltage start-up generator conceived for applications managed by a microcontroller.
It allows the designer to use the same ballast circuit for different lamp wattage/type by simply
changing the µC software.
APPLICATIONS
DIMMABLE/NON-DIMMABLE BALLST
The digital input pins - able to receive signals up to
400KHz - are connected to level shifters that provide the control signals to their relevant drivers;
DESCRIPTION
Designed in High-voltage BCD Off-line technology, the L6382D is provided with 4 input pins and a
Figure 2. Block Diagram
HVSU
TPR
BOOTSTRAP
BOOT
>600V
HIGH
“ON”
IC BIAS
VOLTAGE
START-UP
“OFF”
GENERATOR
mP UVLO
R
Q
LEVEL SHIFT
3.3V
S
HSD
HSG
600V
OUT
Q
LSD
R Q
ON
PSW
3.3V
SUPPLY
L
O
G
I
C
S
LSG
Q
CSO
OCP
TPR
CSI
HED
HEG
PFD
DIM
REF
January 2005
GND
PFG
Vcc
HSI LSI
HEI
PFI
Rev. 2
1/14
L6382D
in particular the L6382D embeds one driver for the PFC pre-regulator stage, two drivers for the ballast halfbridge stage (High Voltage, including also the bootstrap function) and the last one to provide supplementary features like preheating of filaments supplied through isolated filaments in dimmable applications.
A precise reference voltage (+3.3V ±1%) able to provide up to 30mA is available to supply the µC in operating mode. Instead, during start-up and save mode the current available at VREF is up to 10mA and it
is provided by the internal high voltage start-up generator.
The chip has been conceived with advanced power management logic to minimize power losses and increase the application reliability.
In the half-bridge section, a patented integrated bootstrap section replaces the external bootstrap diode.
The L6382D integrates also a function that regulates the IC supply voltage (without the need of any external charge pump) and optimizes the current consumption.
Figure 3. Pin Connection (Top View)
PFI
LSI
HSI
HEI
PFG
N.C.
TPR
GND
LSG
VCC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VREF
CSI
CSO
HEG
N.C.
HVSU
N.C.
OUT
HSG
BOOT
Figure 4. Typical System Block Diagram
PFC
CIRCUIT
AC
MAINS
HV
START-UP
CHARGE
PUMP
REGULATOR
BOOTSTRAP
HB
DRIVER
PFC
3.3V
DRIVER
SUPPLY
µC
2/14
PROTECTION
TL
L6382D
Table 2. Pin Functions
N.
Pin
Function
1
PFI
Digital input signal to control the PFC gate driver. This pin has to be connected to a TTL
compatible signal.
2
LSI
Digital input signal to control the half-bridge low side driver. This pin has to be connected to a
TTL compatible signal.
3
HSI
Digital input signal to control the half-bridge high side driver. This pin has to be connected to a
TTL compatible signal.
4
HEI
Digital input signal to control the HEG output. This pin has to be connected to a TTL compatible
signal.
5
PFG
PFC Driver Output. This pin must be connected to the PFC power MOSFET gate. A resistor
connected between this pin and the power MOS gate can be used to reduce the peak current.
An internal 10KΩ resistor toward ground avoids spurious and undesired MOSFET turn-on
The totem pole output stage is able to drive the power MOS with a peak current of 120mA
source and 250mA sink.
6
N.C.
Not connected
7
TPR
Input for two point regulator; by coupling the pin with a capacitor to a switching circuit, it is
possible to implement a charge circuit for the Vcc.
8
GND
Chip ground. Current return for both the low-side gate-drive currents and the bias current of the
IC. All of the ground connections of the bias components should be tied to a track going to this
pin and kept separate from any pulsed current return.
9
LSG
Low Side Driver Output. This pin must be connected to the gate of the half-bridge low side
power MOSFET. A resistor connected between this pin and the power MOS gate can be used
to reduce the peak current.
An internal 20KΩ resistor toward ground avoids spurious and undesired MOSFET turn-on.
The totem pole output stage is able to drive power with a peak current of 120mA source and
120mA sink.
10
Vcc
Supply Voltage for the signal part of the IC and for the drivers.
11
BOOT
High-side gate-drive floating supply Voltage. The bootstrap capacitor connected between this
pin and pin 13 (OUT) is fed by an internal synchronous bootstrap diode driven in phase with the
low-side gate-drive. This patented structure normally replaces the external diode.
12
HSG
High Side Driver Output. This pin must be connected to the gate of the half bridge high side
power MOSFET . A resistor connected between this pin and the power MOS gate can be used
to reduce the peak current.
An internal 20KΩ resistor toward OUT pin avoids spurious and undesired MOSFET turn-on
The totem pole output stage is able to drive the power MOS with a peak current of 120mA
source and 120mA sink.
13
OUT
High-side gate-drive floating ground. Current return for the high-side gate-drive current. Layout
carefully the connection of this pin to avoid too large spikes below ground.
14
N.C.
Not connected
15
HVSU
High-voltage start-up. The current flowing into this pin charges the capacitor connected
between pin Vcc and GND to start up the IC. Whilst the chip is in save mode, the generator is
cycled on-off between turn-on and save mode voltages. When the chip works in operating
mode the generator is shut down and it is re-enabled when the Vcc voltage falls below the
UVLO threshold. According to the required VREF pin current, this pin can be connected to the
rectified mains voltage either directly or through a resistor.
16
N.C.
High-voltage spacer. The pin is not connected internally to isolate the high-voltage pin and
comply with safety regulations (creepage distance) on the PCB.
17
HEG
Output for the HEI block; this driver can be used to drive the MOS employed in isolated
filaments preheating. An internal 20KΩ resistor toward ground avoids spurious and undesired
MOSFET turn-on.
3/14
L6382D
Table 2. Pin Functions (continued)
N.
Pin
Function
18
CSO
Output of current sense comparator, compatible with TTL logic signal; during operating mode,
the pin is forced low whereas whenever the OC comparator is triggered (CSI> 0.55 typ.) the pin
latches high.
19
CSI
Input of current sense comparator, it is enabled only during operating mode; when the pin
voltage exceeds the internal threshold, the CSO pin is forced high and the half bridge drivers
are disabled. It exits from this condition by either cycling the Vcc below the UVLO or with
LGI=HGI=low simultaneously.
20
VREF
Voltage reference. During operating mode an internal generator provides an accurate voltage
reference that can be used to supply up to 30mA (during operating mode) to an external circuit.
A small film capacitor (0.22µF min.), connected between this pin and GND is recommended to
ensure the stability of the generator and to prevent noise from affecting the reference.
Table 3. Absolute Maximum Ratings
Symbol
Pin
VCC
10
IC supply voltage (ICC = 20mA)
Self-limited
VHVSU
15
High voltage start-up generator voltage range
-0.3 to 600
V
VBOOT
11
Floating supply voltage
-1 to VHVSU+VCC
V
VOUT
13
Floating ground voltage
-1 to 600
V
ITPR(RMS)
6
Maximum TPR RMS current
±200
mA
ITPR(PK)
6
Maximum TPR peak current
±600
mA
VTPR
6
Maximum TPR voltage (*)
14
V
19
CSI input voltage
-0.3 to 7
V
1, 2, 3, 4
Logic input voltage
-0.3 to 7
V
9, 12, 17
Operating frequency
15 to 400
KHz
5
Operating frequency
15 to 600
KHz
Storage Temperature
-40 to +150
°C
Ambient Temperature operating range
-40 to +125
°C
Value
Unit
120
°C/W
Tstg
Tj
Parameter
Value
Unit
(*) excluding operating mode
Table 4. Thermal Data
Symbol
Rth j-amb
4/14
Parameter
Max. Thermal Resistance, Junction-to-ambient
L6382D
Table 5. Electrical Characteristcs (Tj = 25°C, VCC=12V unless otherwise specified)
Symbol
Pin
Parameter
Test condition
min.
typ
max
UNIT
SUPPLY VOLTAGE
VccON
10
Turn-on voltage
13
14
15
V
VccOFF
10
Turn-off voltage
7.5
8.25
9.2
V
VccSM
10
Save mode voltage
12.75
13.8
14.85
V
VSMhys
10
Save mode hysteresys
0.15
0.2
0.25
V
VREF(OFF)
10
Reference turn-off
5.7
6
6.33
V
IvccON
10
Start-up current
150
µA
IvccSM
10
Save
Mode
consumption
190
µA
230
µA
2
mA
current
(1)
Ivcc
10
Quiescent current
operating mode
Vz
10
Internal Zener
150
in Vcc=13V; LGI=HGI=high; no
load on VREF.
TBD
V
20
mA
HIGH VOLTAGE START-UP
IMSS
ILSS
15
Maximum current
VHVSU > 50V
15
Turn-on Voltage
IHVSU=5mA
15
Leakage current off state
VHVSU = 600V
TBD
V
40
µA
TWO POINT REGULATOR (TPR) PROTECTION
TPRst
10
Vcc Protection level
Operating mode
14.0
15.0
V
TPR(ON)
10
Vcc Turn-on level
Operating mode; after the first
falling edge on LSG
12.5
13.5
V
TPR(OFF)
10
Vcc Turn-off level
Operating mode; after the first
falling edge on LSG
12.45
13.48
V
7
Output voltage on state
ITPR = 200mA
2
V
7
Forward
Diode
2
V
7
Leakage current off state
5
µA
voltage
drop @ 600mA forward current.
VTPR = 13V
LSG, HEG & PFG DRIVERS
VOH(LS)
5, 9, 17
HIGH Output Voltage
ILSG = 10mA
VCC 0.5
V
VOL(LS)
5, 9, 17
LOW Output Voltage
ILSG = 10mA
0.5
V
Sink Current Capability
LSG and PFG
120
mA
HEG
50
mA
5/14
L6382D
Table 5. Electrical Characteristcs (continued)
Symbol
Pin
Parameter
Source Current
Capability
Test condition
min.
LSG
120
HEG
70
PFG
250
typ
max
UNIT
mA
TRISE
5, 9, 17
Rise time
Cload = 1nF
TBD
ns
TFALL
5, 9, 17
Fall time
Cload = 1nF
TBD
ns
TDELAY
RB
Propagation delay (input LSG; high to low and low to
to output)
high
300
ns
HEG; high to low and low to
high
200
ns
PFG; high to low
250
ns
PFG; low to high
200
ns
Pull down Resistor
LSG
20
KΩ
HEG
50
KΩ
PFG
10
KΩ
HSG DRIVER (VOLTAGES REFERRED TO OUT)
VOH(HS)
12
HIGH Output Voltage
IHSG = 10 mA
VOUT 0.5
V
VOL(HS)
12
LOW Output Voltage
IHSG = 10 mA
0.5
V
12
Sink Current Capability
120
mA
12
Source Current
Capability
120
mA
TRISE
12
Rise time
Cload = 1nF
TBD
ns
TFALL
12
Fall time
Cload = 1nF
TBD
ns
TDELAY
12
Propagation delay (LGI to high to low and low to high
LSG)
RB
12
Pull down Resistor
300
to OUT
20
ns
KΩ
HIGH-SIDE FLOATING GATE-DRIVER SUPPLY
ILKBOOT
11
VBOOT
current
ILKOUT
13
OUT pin leakage current
VOUT = 562V
Synchronous bootstrap
diode on-resistance
VLVG = HIGH
100
Forward Voltage Drop
at 10 mA forward current
1.9
Forward Current
at 5V forward voltage drop
RDS(on)
6/14
pin
leakage VBOOT = 580V
25
5
µA
5
µA
Ω
2.4
V
mA
L6382D
Table 5. Electrical Characteristcs (continued)
Symbol
Pin
Parameter
20
Reference voltage
Test condition
min.
typ
max
UNIT
15mA load.
3.267
3.3
3.333
V
15mA load, (1)
3.234
3.3
3.366
V
2
mV
15
mV
VREF
VREF
IREF
20
Load regulation
IRef = -3 to +30 mA
20
Voltage change
15mA load; Vcc = 9V to 15V
20
VREF latched protection
20
VREF Clamp @3mA
20
Current Drive Capability
-20
2
VCC from 0 to VCCON during
start-up; Vcc from VREF(OFF) to
0 during shut-down.
Save mode
V
1.2
V
-3
+30
mA
-3
+10
mA
5.01
V
500
nA
200
ns
0.5
V
135
µs
OVERCURRENT BUFFER STAGE
VCSI
19
Comparator Level
ICSI
19
Input Bias Current
Bandgap
Propagation delay
CSO turn off to LSG low
18
High output voltage
I CSO= 200µA
18
Low output voltage
I CSO = -150µA
0.49
0.5
VREF0.5V
DIM
Normal Mode Time Out
TED
65
100
Vref enabling drivers
3.0
V
Time enabling drivers
10
µs
LOGIC INPUT
1 to 4
Low Level Logic Input
Voltage
1 to 4
High Level Logic Input
Voltage
LGI
Pull down resistor
0.8
2.2
V
V
100
KΩ
Notes: 1. Specification over the -40°C to +125°C junction temperature range are ensured by design, characterization and statistical correlation.
7/14
L6382D
4
APPLICATION INFORMATION
4.1 POWER MANAGEMENT
The L6382D has two stable states (save mode and operating mode) and two additional states that manage the Start-up and fault conditions (fig. 5): the Over Current Protection is a parallel asynchronous process enabled when in operating mode.
Following paragraphs will describe each mode and the condition necessary to shift between them.
Figure 5.
START-UP
VCC>VCC(ON)
VCC<VREF(OFF)
SAVE MODE
VREF>3V
&
TDE>10ms
VCC<VREF(OFF)
VCC<VCC(ON)
LGI low
for more
than 100ms
SHUT DOWN
VCC < VCC(OFF)
or
OPERATING
MODE
VREF<2V
4.1.1 START-UP mode
With reference to the timing diagram of figure 6, when power is first applied to the converter, the voltage
on the bulk capacitor builds up and the HV generator is enabled to operate drawing about 10mA. This current, diminished by the IC consumption (less than 150µA), charges the bypass capacitor connected between pin Vcc and ground and makes its voltage rise almost linear.
During this phase, all IC's functions are disabled except for:
the current sinking circuit on VREF pin that maintains low the voltage by keeping disabled the
microcontroller connected to this pin;
■ the High-Voltage Start-Up (HVSU) that is ON (conductive) to charge the external capacitor on pin Vcc.
As the Vcc voltage reaches the start-up threshold (14V typ.) the chip starts operating and the HV generator
is switched off.
■
Summarizing:
■
the high-voltage start-up generator is active;
■
VREF is disabled with additional sinking circuit on pin VREF is enabled;
■
TPR is disabled;
■
OCP is disabled;
■
the drivers are disabled.
4.1.2 SAVE Mode
This mode is entered after the Vcc voltage reaches the turn-on threshold; the VREF is enabled in low current source mode to supply the µC connected to it, whose wake-up required current must be less than
10mA: if no switching activity is detected at LGI input, the high voltage start-up generator cycles ON-OFF
keeping the Vcc voltage between VccON and VccSM.
8/14
L6382D
Summarizing:
■
the high-voltage start-up generator is cycling;
■
VREF is enabled in low source current capability (IREF ≤ 10mA);
■
TPR circuit is disabled;
■
OCP is disabled;
■
the drivers are disabled.
If the Vcc voltage falls below the VREF(OFF) threshold, the device enters the start-up mode.
4.1.3 OPERATING Mode
After 10µs in save mode and only if the voltage at VREF is higher than 3.0V, on the falling edge on the
HGI input, the drivers are enabled as well as all the IC's functions; this is the mode correspondent to the
proper lamp behavior.
Summarizing:
■
HVSU is OFF
■
VREF is enabled in high source current mode (IREF < 30mA)
■
TPR circuit is enabled
■
OCP is enabled
■
the drivers are enabled
If there is no switching activity on LGI for more than 100µs, the IC returns in save mode.
4.1.4 Shut Down
This state permits to manage the fault conditions in operating mode and it is entered by the occurrence
on one of the following conditions:
– 1. Vcc<VccOff (Under Voltage fault on Supply),
– 2. VREF<2.0V (Under Voltage fault on VREF)
In this state the functions are:
■
The HVSU generator is ON
■
VREF is enabled in low source current mode (IREF < 10mA)
■
TPR is disabled
■
OCP is disabled
■
the drivers are disabled
In this state if Vcc reaches VccOn, the device enters the save mode otherwise, if Vcc<VREF(OFF), also the
µC is turned off and the device will be ready to execute the Start-up sequence.
Figure 6. Timing Sequences: TPR behavior (left) Start-up, save mode and operating mode (right).
Vcc
VCCon
TPR(OFF)
TPR(ON)
Vcc
VCCon
VccSM
TPR Switching
VccOFF
VREF
VREF
LGI
LGI
LGI
HGI
PSW
HVSU
10µs
OPERATING MODE
9/14
L6382D
5
BLOCK DESCRIPTION
5.1 SUPPLY SECTION
■
PUVLO ( Power Under Voltage Lock Out): This block controls the power management of the L6382D
ensuring the right current consumption in each operating state, the correct VREF current capability, the
driver enabling and the high-voltage start-up generator switching.
During Start-up the device sinks the current necessary to charge the external capacitor on pin VCC from
the high voltage bus; in this state the other IC's functions are disabled and the current consumption of
the whole IC is less than 150µA.
When the voltage on VCC pin reaches VccON, the IC enters the save mode where the µPUVLO block
controls Vcc between VccON and VccSM by switching ON/OFF the high voltage start-up generator.
■
HVSU (High-Voltage Start-Up generator): a 600V internal MOS transistor structure controls the Vcc
supply voltage during start-up and save mode conditions and it reduces the power losses during
operating Mode by switching OFF the MOS transistor. The transistor has a source current capability of
up to 30mA.
■
TPR (Two Point Regulator) & PWS: during operating mode, the TPR block controls the PSW switch
in order to regulate the IC supply voltage (VCC) to a value in the range between TPR(ON) and
TPR(OFF) by switching ON and OFF the PSW transistor.
– Vcc > TPRst: the PSW is switched ON immediately;
– TPR(ON) < Vcc < TPRst: the PSW is switched ON at the following falling edge of LGI;
– Vcc < TPR(OFF): the PSW is switched OFF at the following falling edge on LGI.
When the PSW switch is OFF, the diodes build a charge pump structure so that, connecting the TPR pin
to a switching voltage (through a capacitor) it is possible to supply the low voltage section of the chip without adding any further external component. The diodes and the switch are designed to withstand a peak
current of at least 200mARMS.
5.2 3.3V REFERENCE VOLTAGE
This block is used to supply the microcontroller; this source is able to supply 10mA in save mode and
30mA in operating mode; moreover, during start-up when VREF is not yet available, an additional circuit is
ensures that, even sinking 3mA, the pin voltage doesn't exceed 1.2V.
The reference is available until Vcc is above VREF(OFF); below that it turns off and the additional sinking
circuit is enabled again.
5.3 DRIVERS
■
LSD (Low Side Driver): it consists of a level shifter from 3.3V logic signal (LGI) to Vcc MOS driving level;
conceived for the half-bridge low-side power MOS, it is able to source and sink 120mA (min).
■
HSD (Level Shifter and High Side Driver): it consists of a level shifter from 3.3V logic signal (HGI) to the
high side gate driver input up to 600V. Conceived for the half-bridge high-side power MOS, the HSD is
able to source 120mA from HSB to HSG (turn-on) and to sink 120mA to HSS (turn-off).
■
PFD (Power Factor Driver): it consists of a level shifter from 3.3V logic signal (PFI) to Vcc MOS driving
level: the driver is able to source 120mA from Vcc to PFG (turn-on) and to sink 250mA to GND (turnoff); it is suitable to drive the MOS of the PFC pre-regulator stage.
■
HED (Heat Driver): it consists of a level shifter from 3.3V logic signal (HEI) to Vcc MOS driving level;
the driver is able to source 30mA from Vcc to HEG and to sink 75mA to GND and it is suitable for the
10/14
L6382D
filament heating when they are supplied by independent winding.
■
Bootstrap Circuit: it generates the supply voltage for the high side Driver (HSD). This circuit sources
current from Vcc to PIN HSB when LSG in ON. A patented integrated bootstrap section replaces an
external bootstrap diode. This section together with a bootstrap capacitor provides the bootstrap voltage
to drive the high side power MOSFET. This function is achieved using a high voltage DMOS driver
which is driven synchronously with the low side external power MOSFET. For a safe operation, current
flow between BOOT pin and Vcc is always inhibited, even though ZVS operation may not be ensured.
5.4 INTERNAL LOGIC, OVER CURRENT PROTECTION (OCP) AND INTERLOCKING FUNCTION.
The DIM (Digital Input Monitor) block manages the input signals delivered to the drivers ensuring that they
are low during the described start-up procedure; the DIM block controls the L6382D behaviour during both
save and operating modes.
When the voltage on pin CSI overcomes the internal reference of 0.5V (typ.) the block latches the fault
condition: in this state the OCP block forces low both HSD and LSD signals while CSO will be forced high.
This condition remains latched until LSI and HSI are simultaneously low and CSI is below 0.5V.
This function is suitable to implement an over current protection or hard-switching detection by using an
external sense resistor.
As the voltage on pin CSI can go negative, the current must be limited below 2mA by external components.
Another feature of the DIM block is the internal interlocking that avoids cross-conduction in the halfbridge FET's: if by chance both HGI and LGI input's are brought high at the same time, then LSG and HSG
are forced low as long as this critical condition persists.
11/14
L6382D
Figure 7. SO20 Mechanical Data & Package Dimensions
mm
inch
DIM.
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.10
0.30
0.004
0.012
B
0.33
0.51
0.013
0.200
C
0.23
0.32
0.009
0.013
D (1)
12.60
13.00
0.496
0.512
E
7.40
7.60
0.291
0.299
e
1.27
0.050
H
10.0
10.65
0.394
0.419
h
0.25
0.75
0.010
0.030
L
0.40
1.27
0.016
0.050
k
ddd
OUTLINE AND
MECHANICAL DATA
0˚ (min.), 8˚ (max.)
0.10
0.004
(1) “D” dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
SO20
0016022 D
12/14
L6382D
Table 6. Revision History
Date
Revision
Description of Changes
November 2004
1
First Issue
January 2005
2
Changed from “Preliminary Data” to “Final Datasheet”.
13/14
L6382D
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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14/14