STMICROELECTRONICS L6740LTR

L6740L
Hybrid controller (4+1) for AMD SVID and PVID processors
Features
■
Hybrid controller: compatible with PVI and SVI
CPUs
■
Dual controller: 2 to 4 scalable phases for CPU
CORE, 1 Phase for NB
■
Dual-Edge asynchronous architecture with
LTB technologyTM
■
PSI management to increase efficiency in
Light-Load conditions
Description
■
Dual Over-Current protection:
Average and per-Phase
■
Load indicator (CORE section)
L6740L is a hybrid CPU Power Supply Controller
compatible with both Parallel (PVI) and Serial
(SVI) protocols for AMD Processors.
■
Voltage positioning
■
Dual remote sense
■
Adjustable independent reference offset
■
Feedback disconnection protection
■
Programmable OV protection
■
Oscillator internally fixed at 150kHz externally
adjustable
■
LSLess startup to manage Pre-biased output
■
Flexible driver support
■
HTQFP48 package
HTQFP48
The Dual-Edge Asynchronous Architecture is
optimized by LTB technologyTM allowing fast loadtransient response minimizing the output capacitor and reducing the total BOM cost.
Applications
■
■
Hybrid High-Current VRM / VRD for Desktop /
Server / Workstation / IPC CPUs supporting
PVI and SVI interface
High-density DC / DC converters
Table 1.
August 2007
The device embeds two independent control
loops for the CPU core and the integrated NB,
each one with its own set of protections. L6740L
is able to work in Single-Plane mode, addressing
only the CORE Section, according to the parallel
DAC codification. When in Dual-Plane mode, it is
compatible with the AMD SVI specification
addressing the CPU and NB voltages according
to the SVI bus commands.
PSI management allows the device to selectively
turn-off phases when the CPU is in low-power
states increasing the over-all efficiency.
Fast protection against load over current is provided for both the Sections. Furthermore, feedback disconnection protection prevents from
damaging the load in case of misconnections in
the system board..
Device summary
Order codes
Package
Packaging
L6740L
HTQFP48
Tube
L6740LTR
HTQFP48
Tape and reel
Rev 2
1/44
www.st.com
1
Contents
L6740L
Contents
1
2
3
Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4
1.1
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
Device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5
Hybrid CPU support and CPU_TYPE detection . . . . . . . . . . . . . . . . . . 16
6
2/44
5.1
PVI - parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2
PVI start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3
SVI - serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.4
SVI start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.4.1
Set VID command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.4.2
PWROK de-assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.4.3
PSI_L and efficiency optimization at light-load. . . . . . . . . . . . . . . . . . . . 21
5.4.4
HiZ management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.4.5
Hardware jumper override - V_FIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1
CORE section - Phase # programming . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2
CORE section - Current reading and current sharing loop . . . . . . . . . . . 24
6.3
CORE section - Load-line and load-indicator (Optional) . . . . . . . . . . . . . 25
6.4
CORE section - Offset (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.5
NB section - Current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.6
NB section - Load-line and load-indicator (Optional) . . . . . . . . . . . . . . . . 27
6.7
NB section - Offset (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
L6740L
Contents
6.8
NB section - Maximum Duty-Cycle limitation . . . . . . . . . . . . . . . . . . . . . . 28
6.9
On-The-Fly VID transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.10
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.10.1
7
LS-Less Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Output voltage monitoring and protections . . . . . . . . . . . . . . . . . . . . . 31
7.1
Programmable over voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.2
Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.3
PWRGOOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.4
Over-current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.4.1
CORE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.4.2
NB section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8
Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9
System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.1
Compensation network guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10
LTB technology™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11
Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
11.1
Power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
11.2
Small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . 41
12
TQFP48 mechanical data & package dimensions . . . . . . . . . . . . . . . . 42
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3/44
Typical application circuit and block diagram
L6740L
1
Typical application circuit and block diagram
1.1
Application circuit
Figure 1.
Typical 4+1 application circuit
LIN
CDEC
CBULK_IN
36 VID1
40 VID2/SVD
39 VID3/SVC
25 VID4
26 VID5
10 OVP / V_FIX
27 OSC / FLT
8 OS
29 NB_OS
RLTBG
11 LTB_GAIN
12 PSI_L
3
COMP
CF
RF
PWM4
NB_PWM
OC_PHASE
4
FB
9
LTB
RLTB
34
46
EN*
45
44
21
L6741/3
PWM
47
HS1
UGATE
L1
PHASE
LS1
LGATE
GND
R
ROC_TH
CS1- 14
CS2+
VCC PVCC*
BOOT
CHF
RG
19
CS4- 20
NB_ISEN
CDEC
RG
17
CS3- 18
CS4+
RG
15
CS2- 16
CS3+
C
PWM
RG
EN*
23
RISEN
FBG
VSEN
L2
PHASE
R
LS2
LGATE
GND
7
HS2
UGATE
6
31
C
NB_FBG 30
NB_COMP
DROOP
48
28 ROC_AVG
OC_AVG / LI
13
CS1+
NB_VSEN
5
CLTB
RFB
PWM3
32
NB_FB
ROVP
ROSC
NB_DROOP
PVI / SVID Bus
PWM1
PWM2
ST L6740L
Hybrid PVID / SVID Controller (**)
38 EN
35 VID0
CHF
VCC
GND
41 PWRGOOD
37 PWROK
VCC PVCC*
BOOT
1
L6741/3
2
ENDRV 43
NB_ENDRV 42
CDEC
VCC PVCC*
BOOT
33
RFB_NB
PWM
EN*
L6741/3
CHF
CF_NB RF_NB
UGATE
HS3
L3
PHASE
R
LS3
LGATE
GND
C
CDEC_NB
CBULK_NB
CDEC
VCC PVCC*
BOOT
VCC PVCC*
BOOT
CHF_NB
LNB
PHASE
LSNB
LGATE
PWM
PWM
EN*
EN*
GND
GND
L6741/3
UGATE
L6741/3
CHF
HSNB
UGATE
HS4
L4
PHASE
LS4
LGATE
R
C
PVI / SVID AM2 CPU
NB
CORE
COUT_NB
CMLCC_NB
CMLCC
SVID / PVID Interface
(*) PVCC Only applies to L6741; EN Only applies to L6743. See related DS for further details
(**) Pin not listed to be considered as Not Connected
ST L6740L (4+1) Reference Schematic
4/44
COUT
VIN
L6740L
Typical application circuit and block diagram
Figure 2.
Typical 3+1 application circuit
LIN
VIN
CDEC
CBULK_IN
36 VID1
40 VID2/SVD
39 VID3/SVC
25 VID4
26 VID5
10 OVP / V_FIX
ROSC
27 OSC / FLT
8
OS
29 NB_OS
RLTBG
11 LTB_GAIN
12 PSI_L
3 COMP
CF
RF
PWM4
NB_PWM
DROOP
4
FB
9
LTB
RLTB
34
47
46
EN*
45
44
L6741/3
PWM
GND
HS1
UGATE
L1
PHASE
R
LS1
LGATE
ROC_TH
OC_PHASE
28 ROC_AVG
OC_AVG / LI
13
CS1+
CS1- 14
CS2+
VCC PVCC*
BOOT
CHF
RG
19
CS4- 20
NB_ISEN
CDEC
RG
17
CS3- 18
CS4+
RG
15
CS2- 16
CS3+
C
PWM
RG
EN*
23
RISEN
FBG
VSEN
GND
7
HS2
UGATE
L2
PHASE
R
LS2
LGATE
6
31
C
NB_FBG 30
NB_COMP
5
48
21
NB_VSEN
CLTB
RFB
PWM3
32
NB_FB
ROVP
NB_DROOP
PVI / SVID Bus
PWM1
PWM2
ST L6740L
Hybrid PVID / SVID Controller (**)
38 EN
35 VID0
CHF
VCC
GND
41 PWRGOOD
37 PWROK
VCC PVCC*
BOOT
1
L6741/3
2
ENDRV 43
NB_ENDRV 42
CDEC
VCC PVCC*
BOOT
33
RFB_NB
PWM
EN*
GND
L6741/3
CHF
CF_NB RF_NB
UGATE
HS3
L3
PHASE
LS3
LGATE
R
C
CDEC_NB
CBULK_NB
VCC PVCC*
BOOT
HSNB
UGATE
LNB
PHASE
LSNB
LGATE
L6741/3
CHF_NB
PWM
EN*
GND
PVI / SVID AM2 CPU
NB
CORE
COUT_NB
CMLCC_NB
CMLCC
COUT
SVID / PVID Interface
(*) PVCC Only applies to L6741; EN Only applies to L6743. See related DS for further details
(**) Pin not listed to be considered as Not Connected
ST L6740L (3+1) Reference Schematic
5/44
Typical application circuit and block diagram
Figure 3.
L6740L
Typical 2+1 application circuit
LIN
CDEC
CBULK_IN
1
39 VID3/SVC
25 VID4
26 VID5
10 OVP / V_FIX
ROSC
27 OSC / FLT
8
OS
29 NB_OS
RLTBG
11 LTB_GAIN
12 PSI_L
3
COMP
CF
RF
PWM4
NB_PWM
DROOP
4
FB
9
LTB
RLTB
34
46
EN*
45
44
L6741/3
PWM
47
GND
HS1
UGATE
L1
PHASE
32
OC_PHASE
28 ROC_AVG
OC_AVG / LI
13
CS1+
CS1- 14
CS2+
CS3+
CDEC
RG
VCC PVCC*
BOOT
CHF
RG
19
CS4- 20
NB_ISEN
RG
17
CS3- 18
CS4+
C
15
CS2- 16
PWM
RG
EN*
23
RISEN
FBG
VSEN
GND
7
HS2
UGATE
L2
PHASE
LS2
LGATE
6
31
ENDRV 43
NB_ENDRV 42
RFB_NB
CDEC_NB
VCC PVCC*
BOOT
HSNB
UGATE
PHASE
LSNB
LGATE
L6741/3
CHF_NB
LNB
PWM
EN*
GND
PVI / SVID AM2 CPU
NB
CORE
COUT_NB
CMLCC_NB
CMLCC
SVID / PVID Interface
(*) PVCC Only applies to L6741; EN Only applies to L6743. See related DS for further details
(**) Pin not listed to be considered as Not Connected
ST L6740L (2+1) Reference Schematic
6/44
R
C
33
CF_NB RF_NB
CBULK_NB
R
LS1
LGATE
ROC_TH
NB_FBG 30
NB_COMP
5
48
21
NB_VSEN
CLTB
RFB
PWM3
NB_FB
ROVP
ST L6740L
Hybrid PVID / SVID Controller (**)
36 VID1
40 VID2/SVD
PWM2
NB_DROOP
PVI / SVID Bus
VCC
GND
38 EN
35 VID0
CHF
PWM1
L6741/3
2
41 PWRGOOD
37 PWROK
VCC PVCC*
BOOT
COUT
VIN
PWM4
IOS
OFFSET
IOS
64k
OSC
50µA +INB_OS
64k
OSC
VCC
1.24V
VCC
SGND
1.24V
NB_FBG
30µA
IDROOP
Σ
PWM4
INB_OS
CS1CORE - TOT CURRENT
REMOTE
BUFFER
ERROR
AMPLIFIER
OFFSET
64k
64k
Σ
INB_DROOP
REMOTE
BUFFER
PWM3
PWM3
OUTPUT VOLTAGE
MONITOR AND PROTECTION
MANAGEMENT
NB_VSEN
ENDRV
ENDRV
64k
Σ
64k
PWM2
NB_FB
NB_DROOP
64k
PWM2
DUAL CHANNEL
OSCILLATOR (4+1)
Σ
ERROR
AMPLIFIER
L6740L
CONTROL LOGIC
OSC
NB_OS
NB_COMP
INB_OS
CORE_REF
& NB_REF
ENDRV
PWM1
NB_PWM
NB CURR
SENSE
NB_ENDRV
PWM1
NB_PWM
AMD SVI / PVI FLEXIBLE
INTERFACE
NB - TOT CURRENT
CURRENT
BALANCE
NB_ISEN
VID0
VID1
VID2 / SVD
VID3 / SVC
VID4
VID5
11 µA
OC_PHASE
DIFFERENTIAL
CURRENT SENSE
CS1+
CS1CS2+
CS2CS3+
CS3CS4+
CS4-
LTB
LTB_GAIN
Block diagram
IDROOP
Figure 4.
PSI_L
Block diagram
V_FIX / OVP
1.2
OC_AVG / LI
Typical application circuit and block diagram
EN
PWROK
PWRGOOD
L6740L
NB_ENDRV
NB_ENDRV
64k
VCORE_REF NB_REF
(from SVI/PVI decoding)
VSEN
FBG
FB
DROOP
COMP
OS
SGND
7/44
Pins description and connection diagrams
Pins description and connection diagrams
VID4
VID5
OSC / FLT
OC_AVG / LI
NB_OS
NB_FBG
NB_VSEN
NB_DROOP
N.C.
EN
38
23
NB_ISEN
SVC
39
22
N.C.
SVD
40
21
OC_PHASE
PWRGOOD
41
20
CS4-
NB_ENDRV
42
19
CS4+
ENDRV
43
18
CS3-
NB_PWM
44
17
CS3+
PWM4
45
16
CS2-
PWM3
46
15
CS2+
PWM2
47
14
CS1-
PWM1
48
13
CS1+
4
5
6
7
8
9 10 11 12
VCC
COMP
FB
DROOP
VSEN
FBG
OS
LTB
PSI_L
3
LTB_GAIN
2
OVP/V_FIX
1
GND
L6740L
Pin descriptions
Table 2.
Pin description
Pin#
Name
1
VCC
2
SGND
All the internal references are referred to this pin. Connect to the PCB
Signal Ground.
COMP
Error amplifier output.
Connect with an RF - CF to FB. The CORE section or the device cannot
be disabled by grounding this pin.
FB
Error amplifier inverting input.
Connect with a resistor RFB to VSEN and with an RF - CF to COMP. Offset current programmed by OS is sunk through this pin.
4
5
6
CORE SECTION
3
8/44
NB_FB
36 35 34 33 32 31 30 29 28 27 26 25
37
24
PWROK
2.1
NB_COMP
Pins connection (Top View)
VID1
Figure 5.
VID0
2
L6740L
Function
Device power supply.
Operative voltage is 12V ±15%. Filter with 1µF MLCC to SGND.
DROOP
A current proportional to the total current read is sourced from this pin
according to the Current Reading Gain.
Short to FB to implement Droop Function, if not used, short to SGND.
VSEN
Output voltage monitor.
It manages OVP and UVP protections and PWRGOOD. Connect to the
positive side of the load for remote sensing. See Section 7 for details.
L6740L
Pins description and connection diagrams
Table 2.
Pin description (continued)
Pin#
Name
7
CORE SECTION
FBG
8
9
Remote ground sense.
Connect to the negative side of the load for remote sensing. See
Section 9 for proper layout of this connection.
OS
Offset programming pin.
Internally set to 1.24V. Connecting a ROS resistor to SGND allows to set
a current that is mirrored into FB pin in order to program a positive offset according to the selected RFB.
Short to SGND to disable the function. See Section 6.4 for details.
LTB
LTB TechnologyTM Input pin.
Connect through an RLTB - CLTB network to the regulated voltage
(CORE Section) to detect load transient. See Section 10 for details.
OVP. Over Voltage Programming Pin. Internally pulled-up to 3.3V by
11µA. Connect to SGND through a ROVP resistor and filter with 10nF
(typ) to set a fixed voltage according to the ROVP resistor. If floating it
will program 3.3V threshold. See Section 7 for details.
OVP / V_FIX
V_FIX - Hardware override. Short to SGND to enter VFIX mode
(WARNING: this condition overrides any code programmed on the VIDx
lines). In this case, the device will use SVI inputs as static VIDs and
OVP threshold will be set to 1.8V. See Section 5.4.5 for details.
CORE
SECTION
10
11
Function
LTB_GAIN
LTB TechnologyTM gain pin.
Connect to SGND through a resistor RLTBGAIN to program the LTB
Gain. See Section 10 for details.
PSI_L
Power Saving Indicator (SVI Mode).
Open-drain Input/Output pin. See Section 5.4.3 for details.
13
CS1+
Channel 1 Current Sense Positive Input. Connect through an R-C filter
to the phase-side of the channel 1 inductor.
See Section 9 for proper layout of this connection.
14
CS1-
Channel 1 Current Sense Negative Input. Connect through a RG resistor to the output-side of the channel inductor.
See Section 9 for proper layout of this connection.
15
CS2+
Channel 2 Current Sense Positive Input. Connect through an R-C filter
to the phase-side of the channel 2 inductor.
See Section 9 for proper layout of this connection.
CS2-
Channel 2 Current Sense Negative Input. Connect through a RG resistor to the output-side of the channel inductor.
See Section 9 for proper layout of this connection.
CS3+
Channel 3 Current Sense Positive Input. Connect through an R-C filter
to the phase-side of the channel 3 inductor. When working at 2 phase,
directly connect to Vout_CORE.
See Section 9 for proper layout of this connection.
CS3-
Channel 3 Current Sense Negative Input. Connect through a RG resistor to the output-side of the channel inductor. When working at 2 phase,
connect through RG to CS3+.
See Section 9 for proper layout of this connection.
16
17
18
CORE SECTION
12
9/44
Pins description and connection diagrams
Table 2.
Pin description (continued)
Pin#
CORE SECTION
19
20
30
10/44
NB SECTION
CORE SECTION
27
29
CS4+
Channel 4 Current Sense Positive Input. Connect through an R-C filter
to the phase-side of the channel 4 inductor. When working at 2 or 3
phase, directly connect to Vout_CORE.
See Section 9 for proper layout of this connection.
CS4-
Channel 4 Current Sense Negative Input. Connect through a RG resistor to the output-side of the channel inductor. When working at 2 or 3
phase, connect through RG to CS4+.
See Section 9 for proper layout of this connection.
NB_ISEN
NC
PVI
INTERFACE
24
28
Function
NC
NB
SECTION
22
25,
26
Name
Per-Phase Over Current (CORE Section).
OC_PHASE Internally set to 1.24V, connecting to SGND with a resistor ROC_TH it
programs the OC threshold per-phase. See Section 7.4.1 for details.
21
23
L6740L
Not internally connected.
NB Current Sense Pin.
Used for NB voltage positioning and NB_OCP. Connect through a resistor RISEN to the relative LS Drain. See Section 7.4 for details.
Not internally connected.
Voltage IDentification Pins.
VID4, VID5 Internally pulled-low by 10µA, they are used to program the output
voltage. Used only in PVI-Mode, ignored when in SVI-Mode.See
Section 5 for details.
OSC / FLT
OSC: It allows programming the switching frequency FSW of both Sections. Switching frequency can be increased according to the resistor
ROSC connected from the pin to. SGND with a gain of 6.8kHz/µA (see
Section 8 for details). If floating, the switching frequency is 150kHz per
phase.
FLT: The pin is forced high (3.3V) in case of an OV / UV fault. To
recover from this condition, cycle VCC or the EN pin. See Section 7 for
details.
OC_AVG /
LI
Average Over Current and Load Indicator Pin.
A current proportional to the current delivered by the CORE Section (a
copy of the DROOP current) is sourced through this pin.
The Average-OC threshold is programmed by connecting a resistor
ROC_AVG to SGND. When the generated voltage crosses the OC_AVG
threshold (VOC_AVGTH = 2.5V Typ) the device latches with all mosfets
OFF (to recover, cycle VCC or the EN pin).
A load indicator with 2.5V end-of-scale is then implemented.
See Section 7.4.1 for details.
NB_OS
Offset Programming Pin.
Internally set to 1.24V, connecting a ROS_NB resistor to SGND allows
setting a current that is mirrored into NB_FB pin in order to program a
positive offset according to the selected RFB_NB. Short to SGND to disable the function. See Section 6.7 for details.
NB_FBG
Remote Ground Sense.
Connect to the negative side of the load to perform remote sense. See
Section 9 for proper layout of this connection.
L6740L
Pins description and connection diagrams
Table 2.
Pin description (continued)
Pin#
NB SECTION
31
32
Name
Function
NB_VSEN
NB output voltage monitor.
It manages OVP and UVP protections and PWRGOOD. Connect to the
positive side of the NB load to perform remote sensing. See Section 9
for proper layout of this connection.
A current proportional to the total current read by the NB section is
sourced through this pin according to the Current Reading Gain
NB_DROOP (RISEN). Short to NB_FB to implement Droop Function or connect to
SGND through a resistor and filter with 1nF capacitor to implement NB
LOAD Indicator. If not used, short to SGND.
NB_FB
34
NB_COMP
Error amplifier output.
Connect with an RF_NB - CF_NB to NB_FB. The NB Section or the device
cannot be disabled by grounding this pin.
35,
36
Voltage IDentification Pins.
Internally pulled-low by 10µA, they are used to program the output
VID0, VID1 voltage. VID1 is monitored on the EN pin rising-edge to define the
operative mode of the controller (SVI or PVI). When in SVI Mode, VID0
is ignored. See Section 5 for details.
SVI / PVI INTERFACE
33
NB error amplifier inverting input.
Connect with a resistor RFB_NB to NB_VSEN and with an RF_NB - CF_NB
to NB_COMP. Offset current programmed by NB_OS is sunk through
this pin.
37
EN
SVI / PVI INTERFACE
38
39
40
41
PWROK
System-wide Power Good Input (SVI Mode).
Internally pulled-low by 10µA. When low, the device will decode the two
SVI bits (SVC, SVD) to determine the Pre-PWROK Metal VID (default
condition when pin is floating).
When high, the device will actively run the SVI protocol.
Pre-PWROK Metal VID are latched after EN is asserted and re-used in
case of PWROK de-assertion. Latch is reset by VCC or EN cycle.
VR Enable. Internally pulled-up to 3.3V by 10µA.
Pull-low to disable the device. When set free, the device immediately
checks for the VID1 status to determine the SVI / PVI protocol to be
adopted and configures itself accordingly. See Section 5 for details.
Voltage IDentification Pin - SVI Clock Pin.
SVC / VID3 Internally pulled-low by 10µA, it is used to program the output voltage.
When in SVI-Mode, it is considered as Serial-VID-Data (Input / Open
Drain Output). See Section 5 for details.
Voltage IDentification Pins - SVI Data Pin.
SVD / VID2 Internally pulled-low by 10µA, it is used to program the output voltage.
When in SVI-Mode, it is considered as Serial-VID-Data (Input / Open
Drain Output). See Section 5 for details.
VCORE and NB Power Good.
It is an open-drain output set free after SS as long as both the voltage
PWRGOOD planes are within specifications. Pull-up to 3.3V (typ) or lower, if not
used it can be left floating.
When in PVI Mode, it monitors the CORE Section only.
11/44
Pins description and connection diagrams
Table 2.
ENDRV
External Driver enable.
Open Drain output used to control CORE Section external driver status:
pulled-low to manage HiZ conditions or pulled-high to enable the driver.
Pull up to 3.3V (typ) or lower.
NB_PWM
PWM output.
Connect to external driver PWM input. The device is able to manage
HiZ status by setting the pin floating. When in PVI Mode, NB Section is
kept in HiZ. See Section 5.4.4 for details about HiZ management.
PWM1 to
PWM4
PWM outputs.
Connect to external drivers PWM inputs. The device is able to manage
HiZ status by setting the pins floating.
By shorting to SGND PWM4 or PWM3 and PWM4, it is possible to program the CORE section to work at 3 or 2 phase respectively.
See Section 5.4.4 for details about HiZ management.
45 to
48
CORE
SECTION
44
Thermal pad
2.2
Thermal pad connects the Silicon substrate and makes good thermal
contact with the PCB. Connect to the PGND plane.
Thermal data
Table 3.
Symbol
12/44
Function
External driver enable.
Open Drain output used to control NB Section external driver status:
NB_ENDRV pulled-low to manage HiZ conditions or pulled-high to enable the driver.
Pull up to 3.3V (typ) or lower.
When in PVI Mode, NB Section is always kept in HiZ.
NB
SECTION
43
Name
NB
SECTION
42
Pin description (continued)
CORE
SECTION
Pin#
L6740L
Thermal data
Parameter
Value
Unit
RthJA
Thermal resistance junction to ambient
(Device soldered on 2s2p PC Board)
40
°C/W
RthJC
Thermal resistance junction to case
1
°C/W
TMAX
Maximum junction temperature
150
°C
TSTG
Storage temperature range
-40 to 150
°C
TJ
Junction temperature range
0 to 125
°C
L6740L
Electrical specifications
3
Electrical specifications
3.1
Absolute maximum ratings
Table 4.
Absolute maximum ratings
Symbol
VCC
Parameter
Unit
15
V
-0.3 to 3.6
V
to PGND
All other Pins to PGNDx
3.2
Electrical characteristics
Table 5.
Electrical characteristics
(VCC=12V±15%, TJ = 0°C to 70°C unless otherwise specified).
Symbol
Value
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Supply current and power-ON
ICC
UVLOVCC
VCC supply current
20
VCC Turn-ON
VCC rising
VCC Turn-OFF
VCC falling
mA
9
7
V
V
Oscillator
Main oscillator accuracy
FSW
Oscillator adjustability
ROSC = 27kΩ
∆VOSC
PWM ramp amplitude
CORE and NB section
FAULT
Voltage at Pin OSC
OVP, UVP latch active
dMAX_NB
NB duty-cycle limit
135
150
165
kHz
380
465
550
kHz
2
3
V
3.6
V
INB_DROOP = 0µA
80
%
INB_DROOP = 35µA
40
%
PVI / SVI interface
Input high
EN,
PWROK
2
V
Input low
0.80
V
Pull-up current
EN Pin
10
µA
Pull-down current
PWORK Pin
10
µA
VID2,/SVD
VID3/SVC
Input high
(SVI Mode)
Input low
(SVI Mode)
0.65
V
SVD
Voltage low (ACK)
ISINK = -5mA
250
mV
Input high
(PVI mode)
Input low
(PVI mode)
VID0 to
VID5
Pull-down current
V_FIX
Entering V_FIX mode
0.95
V
1.3
V
0.80
V
µA
10
0.90
V
13/44
Electrical specifications
Table 5.
Symbol
PSI_L
L6740L
Electrical characteristics (continued)
(VCC=12V±15%, TJ = 0°C to 70°C unless otherwise specified).
Parameter
Voltage Low
Test conditions
Min.
Typ.
ISINK = -5mA
Max.
Unit
250
mV
Voltage positioning (CORE and NB Section)
CORE
Output voltage accuracy
NB
OFFSET bias voltage
VSEN to VCORE; FBG to GNDCORE
-8
8
mV
NBVSEN to VNB; NBFBG to GNDFB
-10
10
mV
1.290
V
0
250
µA
IOS = 0 to 250µA
-15
15
%
IDROOP = 0 to 140µA; OS = OFF
-9
9
µA
INB_DROOP = 0 to 35µA; OS = OFF
-4
4
µA
IOS = 0 to 250µA
OS, NB_OS OFFSET current range
OFFSET - IFB accuracy
DROOP
DROOP accuracy
NB_DROOP
A0
EA DC gain
SR
Slew rate
1.190
COMP, NB_COMP to SGND = 10pF
1.24
100
dB
20
V/µs
PWM outputs (CORE and NB Section)
PWMx,
NB_PWM
Output high
I = 1mA
Output low
I = -1mA
IPWMx
Test current
ENDRV,
Output low
NB_ENDRV
3
3.6
V
0.2
V
µA
10
I = -5mA
0.4
V
Protections
Over voltage protection
OVP
UVP
V_FIX Mode (V_FIX = SGND);
VSEN, NB_VSEN Rising
Bias current
1.720
1.800
1.880
V
7
11
15
µA
OV programmability
ROVP = 180kΩ
1.730
1.800
1.870
V
Under voltage protection
VSEN, NB_VSEN Falling; wrt Ref.
-470
-400
-330
mV
PGOOD threshold
VSEN, NB_VSEN Falling; wrt Ref
-300
-250
-200
mV
Voltage low
IPWRGOOD = -4mA
0.4
V
PWRGOOD
Sourced from NB_VSEN; OS = OFF
50
µA
Sunk from VSEN; OS = OFF
30
µA
IVSEN-DISC
VSEN disconnection
VFB-DISC
FB disconnection
CORE - VCS- Rising, above VSEN
500
600
700
mV
FBG DISC
FBG disconnection
EA NI input wrt VID
350
450
550
mV
OC_PHASE Per-phase OC
CORE section; bias voltage
1.200
1.240
1.280
V
kVOC_AVGTH
CORE section
2.430
2.500
2.570
V
11
µA
43
µA
Average OC
kIOC_AVGTH
IOCTH_NB
14/44
OC threshold
IDROOP = 0 to 140µA; OS = OFF
-11
NB section
32
37.5
L6740L
4
Device description and operation
Device description and operation
L6740L is a hybrid CPU Power Supply Controller compatible with both Parallel (PVI) and
Serial (SVI) protocols for AMD K8 - Second Generation Processors. The device provides
complete control logic and protections for a high-performance step-down DC-DC voltage
regulator, optimized for advanced microprocessor power supply supporting both PVI and
SVI communication. It embeds two independent controllers for CPU CORE and the
integrated NB, each one with its own set of protections.
L6740L is able to detect which kind of CPU is connected in order to configure itself to work
as a Single-Plane PVI controller or Dual-Plane SVI controller.
The Controller performs a single-phase control for the NB Section and a programmable 2-to4 phase control for the CORE Section featuring Dual-Edge non-Latched architecture: this
allows fast load-transient response optimizing the output filter consequently reducing the
total BOM cost. Further reduction can be achieved by enabling LTB Technology(TM). NB
phase (when enabled) will be automatically phase-shifted with respect to the CORE phases
in order to reduce the total input rms current amount.
PSI_L Flag is sent to the VR through the SVI bus. The controller monitors this flag and
selctively modifies the phase number in order to optimize the system efficiency when the
CPU enters low-power states. This causes the over-all efficiency to be maximized at light
loads so reducing losses and system power consumption.
Both sections feature programmable Over-Voltage protection and adjustable constant OverCurrent protection. Voltage positioning (LL) is possible thanks to an accurate fully-differential
current-sense across the main inductors for the CORE Section and thanks to the loss-less
current sense across Low-Side MOSFET RdsON for the NB section. In both cases, LL may
be disabled and the generated current information may be used to implement a Load Indicator function.
L6740L features dual remote sensing for the regulated outputs (CORE and NB) in order to
recover from PCB voltage drops also protecting the load from possible feedback network
disconnections.
LSLess start-up function allows the controller to manage pre-biased start-up avoiding dangerous current return through the main inductors as well as negative undershoot on the output voltage if the output filter is still charged before start-up.
L6740L also supports V_FIX mode for system debugging: in this particular configuration the
SVI bus is used as a static bus configuring 4 operative voltages for both the sections and
ignoring any serial-VID command.
When working in PVI mode, the device features On-the-Fly VID management: VID code is
continuously sampled and the reference update according to the variation detected,
L6740L is available in TQFP48 Package.
15/44
Hybrid CPU support and CPU_TYPE detection
5
L6740L
Hybrid CPU support and CPU_TYPE detection
L6740L is able to detect the type of the CPU-core connected and to configure itself
accordingly. At system Start-up, on the rising-edge of the EN signal, the device monitors the
status of VID1 and configures the PVI mode (VID1 = 1) or SVI mode (VID1 = 0).
When in PVI mode, L6740L uses the information available on the VID[0: 5] bus to address
the CORE Section output voltage according to Table 6. NB Section is kept in HiZ mode.
When in SVI mode, L6740L ignores the information available on VID0, VID4 and VID5 and
uses VID2 and VID3 as a SVI bus addressing the CORE and NB Sections according to the
SVI protocol.
Caution:
To avoid any risk of errors in CPU type detection (i.e. detecting SVI CPU when PVI CPU is
installed on the socket and viceversa), it is reccomended to carefully control the start-up
sequencing of the system hosting L6740L in order to ensure than on the EN rising-edge,
VID1 is in valid and correct state.
5.1
PVI - parallel interface
PVI is a 6-bit-wide parallel interface used to address the CORE Section reference.
According to the selected code, the device sets the CORE Section reference and regulates
its output voltage as reported into Table 6.
NB Section is always kept in HiZ; no activity is performed on this section. Furthermore,
PWROK information is ignored as well since the signal only applies to the SVI protocol.
5.2
PVI start-up
Once the PVI mode has been detected, the device uses the whole code available on the
VID[0:5] lines to define the reference for the CORE section. NB Section is kept in HiZ. SoftStart to the programmed reference is performed regardless of the state of PWROK.
See Section 6.10 for details about Soft-Start.
Figure 6.
16/44
System start-up: SVI (to Metal-VID; left) and PVI (right)
L6740L
Hybrid CPU support and CPU_TYPE detection
Table 6.
Voltage identifications (VID) codes for PVI mode
VID5 VID4 VID3 VID2 VID1 VID0
Output
Output
VID5 VID4 VID3 VID2 VID1 VID0
voltage
voltage
0
0
0
0
0
0
1.5500
1
0
0
0
0
0
0.7625
0
0
0
0
0
1
1.5250
1
0
0
0
0
1
0.7500
0
0
0
0
1
0
1.5000
1
0
0
0
1
0
0.7375
0
0
0
0
1
1
1.4750
1
0
0
0
1
1
0.7250
0
0
0
1
0
0
1.4500
1
0
0
1
0
0
0.7125
0
0
0
1
0
1
1.4250
1
0
0
1
0
1
0.7000
0
0
0
1
1
0
1.4000
1
0
0
1
1
0
0.6875
0
0
0
1
1
1
1.3750
1
0
0
1
1
1
0.6750
0
0
1
0
0
0
1.3500
1
0
1
0
0
0
0.6625
0
0
1
0
0
1
1.3250
1
0
1
0
0
1
0.6500
0
0
1
0
1
0
1.3000
1
0
1
0
1
0
0.6375
0
0
1
0
1
1
1.2750
1
0
1
0
1
1
0.6250
0
0
1
1
0
0
1.2500
1
0
1
1
0
0
0.6125
0
0
1
1
0
1
1.2250
1
0
1
1
0
1
0.6000
0
0
1
1
1
0
1.2000
1
0
1
1
1
0
0.5875
0
0
1
1
1
1
1.1750
1
0
1
1
1
1
0.5750
0
1
0
0
0
0
1.1500
1
1
0
0
0
0
0.5625
0
1
0
0
0
1
1.1250
1
1
0
0
0
1
0.5500
0
1
0
0
1
0
1.1000
1
1
0
0
1
0
0.5375
0
1
0
0
1
1
1.0750
1
1
0
0
1
1
0.5250
0
1
0
1
0
0
1.0500
1
1
0
1
0
0
0.5125
0
1
0
1
0
1
1.0250
1
1
0
1
0
1
0.5000
0
1
0
1
1
0
1.0000
1
1
0
1
1
0
0.4875
0
1
0
1
1
1
0.9750
1
1
0
1
1
1
0.4750
0
1
1
0
0
0
0.9500
1
1
1
0
0
0
0.4625
0
1
1
0
0
1
0.9250
1
1
1
0
0
1
0.4500
0
1
1
0
1
0
0.9000
1
1
1
0
1
0
0.4375
0
1
1
0
1
1
0.8750
1
1
1
0
1
1
0.4250
0
1
1
1
0
0
0.8500
1
1
1
1
0
0
0.4125
0
1
1
1
0
1
0.8250
1
1
1
1
0
1
0.4000
0
1
1
1
1
0
0.8000
1
1
1
1
1
0
0.3875
0
1
1
1
1
1
0.7750
1
1
1
1
1
1
0.3750
17/44
Hybrid CPU support and CPU_TYPE detection
5.3
L6740L
SVI - serial interface
SVI is a two wire, Clock and Data, bus that connects a single master (CPU) to one slave
(L6740L). The master initiates and terminates SVI transactions and drives the clock, SVC,
and the data, SVD, during a transaction. The slave receives the SVI transactions and acts
accordingly. SVI wire protocol is based on fast-mode I2C.
SVI interface also considers two additional signal needed to manage the system start-up.
These signals are EN and PWROK. The device return a PWRGOOD signal if the output
voltages are in regulation.
5.4
SVI start-up
Once the SVI mode has been detected on the EN rising-edge, L6740L checks for the status
of the two serial VID pins, SVC and SVD, and stores this value as the Pre-PWROK Metal
VID. The controller initiate a soft-start phase regulating both CORE and NB voltage planes
to the voltage level prescribed by the Pre-PWROK Metal VID. See Table 7 for details about
Pre-PWROK Metal VID codifications. The stored Pre-PWROK Metal VID value are re-used
in any case of PWROK de-assertion.
After bringing the output rails into regulation, the controller asserts the PWRGOOD signal
and waits for PWROK to be asserted. Until PWROK is asserted, the Controller regulates to
the Pre-PWROK Metal VID ignoring any commands coming from the SVI interface.
After PWROK is asserted, the processor has initialized the serial VID interface and L6740L
waits for commands from the CPU to move the voltage planes from the Pre-PWROK Metal
VID values to the operative VID values. As long as PWROK remains asserted, the controller
will react to any command issued through the SVI interface according to SVI Protocol.
See Section 6.10 for details about Soft-Start.
Table 7.
V_FIX mode and MetalVID
Output voltage [V]
SVC
5.4.1
SVD
Pre-PWROK Metal VID
V_FIX Mode
0
0
1.1V
1.4V
0
1
1.0V
1.2V
1
0
0.9V
1.0V
1
1
0.8V
0.8V
Set VID command
The Set VID Command is defined as the command sequence that the CPU issues on the
SVI bus to modify the voltage level of the CORE Section and/or the NB Section.
During a Set VID Command, the processor sends the start (START) sequence followed by
the address of the Section which the Set VID Command applies. The processor then sends
the write (WRITE) bit. After the write bit, the Voltage Regulator (VR) sends the acknowledge
(ACK) bit. The processor then sends the VID bits code during the data phase. The VR
sends the acknowledge (ACK) bit after the data phase. Finally, the processor sends the stop
(STOP) sequence. After the VR has detected the stop, it performs an On-the-Fly VID
18/44
L6740L
Hybrid CPU support and CPU_TYPE detection
transition for the addressed section(s) or, more in general, react to the sent command
accordingly. Refer to Figure 7, Table 8 and Table 9 for details about the Set VID Command.
L6740L is able to manage individual power OFF for both the Sections. The CPU may issue
a serial VID command to power OFF or power ON one Section while the other one remains
powered. In this case, the PWRGOOD signal remains asserted.
Figure 7.
SVI communications - Send byte
START
SLAVE ADDRESSING + W
6
SVC
5
4
3
ACK
7
0
ACK
DATA PHASE
6
0
ACK
SVD
STOP
ACK
110b
START
Slave Addressing
(7 Clocks)
BUS DRIVEN BY L6740L
Table 8.
WRITE ACK
(1Ck) (1Ck)
Data Phase
(8 Clocks)
ACK
(1Ck)
STOP
BUS DRIVEN BY MASTER (CPU)
SVI send byte - Address and data phase description
bits
Description
Address phase
6:4
Always 110b.
3
Not Applicable, ignored.
2
Not Applicable, ignored.
1
CORE Section(1).
If set then the following data byte contains the VID code for CORE Section.
0
NB Section(1).
If set then the following data byte contains the VID code for NB Section.
Data phase
7
6:0
PSI_L Flag (Active low).When asserted, the VR is allowed to enter Power-Saving
mode. See Section 5.4.3.
VID Code. See Table 9.
1. Assertion in both bit 1 and 0 will address the VID code to both CORE and NB simultaneously.
19/44
Hybrid CPU support and CPU_TYPE detection
Table 9.
20/44
L6740L
Data phase - Serial VID codes.
SVI [6:0]
Output
voltage
SVI [6:0]
Output
voltage
SVI [6:0]
Output
voltage
SVI [6:0]
Output
voltage
000_0000
1.5500
010_0000
1.1500
100_0000
0.7500
110_0000
0.3500
000_0001
1.5375
010_0001
1.1375
100_0001
0.7375
110_0001
0.3375
000_0010
1.5250
010_0010
1.1250
100_0010
0.7250
110_0010
0.3250
000_0011
1.5125
010_0011
1.1125
100_0011
0.7125
110_0011
0.3125
000_0100
1.5000
010_0100
1.1000
100_0100
0.7000
110_0100
0.3000
000_0101
1.4875
010_0101
1.0875
100_0101
0.6875
110_0101
0.2875
000_0110
1.4750
010_0110
1.0750
100_0110
0.6750
110_0110
0.2750
000_0111
1.4625
010_0111
1.0625
100_0111
0.6625
110_0111
0.2625
000_1000
1.4500
010_1000
1.0500
100_1000
0.6500
110_1000
0.2500
000_1001
1.4375
010_1001
1.0375
100_1001
0.6375
110_1001
0.2375
000_1010
1.4250
010_1010
1.0250
100_1010
0.6250
110_1010
0.2250
000_1011
1.4125
010_1011
1.0125
100_1011
0.6125
110_1011
0.2125
000_1100
1.4000
010_1100
1.0000
100_1100
0.6000
110_1100
0.2000
000_1101
1.3875
010_1101
0.9875
100_1101
0.5875
110_1101
0.1875
000_1110
1.3750
010_1110
0.9750
100_1110
0.5750
110_1110
0.1750
000_1111
1.3625
010_1111
0.9625
100_1111
0.5625
110_1111
0.1625
001_0000
1.3500
011_0000
0.9500
101_0000
0.5500
111_0000
0.1500
001_0001
1.3375
011_0001
0.9375
101_0001
0.5375
111_0001
0.1375
001_0010
1.3250
011_0010
0.9250
101_0010
0.5250
111_0010
0.1250
001_0011
1.3125
011_0011
0.9125
101_0011
0.5125
111_0011
0.1125
001_0100
1.3000
011_0100
0.9000
101_0100
0.5000
111_0100
0.1000
001_0101
1.2875
011_0101
0.8875
101_0101
0.4875
111_0101
0.0875
001_0110
1.2750
011_0110
0.8750
101_0110
0.4750
111_0110
0.0750
001_0111
1.2625
011_0111
0.8625
101_0111
0.4625
111_0111
0.0625
001_1000
1.2500
011_1000
0.8500
101_1000
0.4500
111_1000
0.0500
001_1001
1.2375
011_1001
0.8375
101_1001
0.4375
111_1001
0.0375
001_1010
1.2250
011_1010
0.8250
101_1010
0.4250
111_1010
0.0250
001_1011
1.2125
011_1011
0.8125
101_1011
0.4125
111_1011
0.0125
001_1100
1.2000
011_1100
0.8000
101_1100
0.4000
111_1100
OFF
001_1101
1.1875
011_1101
0.7875
101_1101
0.3875
111_1101
OFF
001_1110
1.1750
011_1110
0.7750
101_1110
0.3750
111_1110
OFF
001_1111
1.1625
011_1111
0.7625
101_1111
0.3625
111_1111
OFF
L6740L
5.4.2
Hybrid CPU support and CPU_TYPE detection
PWROK de-assertion
Anytime PWROK de-asserts while EN is asserted, the controller uses the previously stored
Pre-PWROK Metal VID and regulates all the planes to that level performing an On-the-Fly
transition to that level.
PWRGOOD is treated appropriately being de-asserted in case the Pre-PWROK Metal VID
voltage is out of the initial voltage specifications.
5.4.3
PSI_L and efficiency optimization at light-load.
PSI_L is an active-low flag (i.e. low logic level when asserted) that can be set by the CPU to
allow the VR to enter Power-Saving mode to maximize the system efficiency when in lightload conditions. The status of the flag is communicated to the controller through the SVI bus
and it is reported on the PSI_L pin (open-drain).
The controller monitors the PSI_L pin also to define the PSI Strategy, that is the action
performed by the controller when PSI_L is asserted. According to Table 10, by programming
different voltage divider on PSI_L, it is possible to configure the device to disable one or two
phases while PSI_L is asserted. The device can also be configured to take no action so
phase number will not change after PSI_L assertion.
In case the phase number is changed, the device will disable one or two phases starting
from the highest one (i.e. if working at 3 phases, phase 3 will be disabled in case of 1 phase
reduction; phase 2 and 3 in case of 2phase reduction). To disable Phases, the controller will
set HiZ on the related PWM and re-configure internal phase-shift to maintain the
interleaving. Furthermore, the internal current-sharing will be adjusted to consider the phase
number reduction. ENDRV will remain asserted.
When PSI_L is de-asserted, the device will return to the original configuration.
Start-up is performed with all the configured phases enabled. In case of On-the-Fly VID
transitions, the device will maintain the phase configuration set before.
PSI Strategy (i.e. the voltage across PSI_L) is read and stored when PWRGOOD is
asserted at the end of the Soft-Start phase.
The phase number management is affected by the external driver selected.
●
If the external driver features the EN function, PSI_L can be tied directly to the EN of
the drivers of the phases that will be disabled.
Furthermore, in case the desired strategy is to work in single phase when 4phases are
configured, PSI_L can be tied also to the EN of the driver connected to Phase2
(apparently, from 4phases the max reduction would be to 2phase min.) in order to
disable also this phase during low-power mode.
●
If the external driver manages HiZ through the PWM input, PSI_L will be connected
only to the external divider used to set the strategy. The system can be down-graded to
single-phase only if configured for three phases.
Since PSI_L can be used to enable some of the external drivers connected, the status of the
pin is the logic AND between the PSI_L Flag and the status of the ENDRV pin: if the
controller wants to disable the external drivers pulling low ENDRV (because of protections
or simply for start-up synchronization) also PSI_L will be tied low.
NB Section is not impacted by PSI_L status change. Figure 8 shows an example of the
efficiency improvement that can be achieved by enabling the PSI management.
21/44
Hybrid CPU support and CPU_TYPE detection
Table 10.
PSI strategy
PSI_L
PSI strategy
No Strategy.
PSI_L still reproduces the status of the PSI Flag
GND
Pull-Up to <3V
Phase number is cut by 1 while PSI_L is asserted.
Pull-Up to 3.3V
Phase number is cut by 2 while PSI_L is asserted.
Figure 8.
5.4.4
L6740L
System efficiency enhancement by PSI
HiZ management
L6740L is able to manage HiZ through both the PWMx and driver enable signals. When the
controller wants to set in high impedance the output of one Section, it set the relative PWM
floating and, at the same time, pulls-low the related ENDRV.
5.4.5
Hardware jumper override - V_FIX
Anytime the pin OVP/V_FIX is driven low, the controller enters V_FIX mode.
When in V_FIX mode, both NB and CORE Section voltages are governed by the information
shown in Table 7. Regardless of the state of PWROK, the device will work in SVI mode. SVC
and SVD are considered as static VID and the output voltage will change according to their
status. Dynamic SVC/SVD-change management is provided in this condition.
V_FIX mode is intended for system debug only.
Protection management differs in this case, see Section 7.1 for details.
22/44
L6740L
Output voltage positioning
Output voltage positioning is performed by selecting the controller operative-mode (SVI, PVI
and V_FIX) and by programming the Droop Function and Offset to the reference of both the
sections (See Figure 9). The controller reads the current delivered by each Section by
monitoring the voltage drop across the Low-Side MOSFET for NB Section or DCR Inductors
for CORE Section. The current (IDROOP / IDROOP_NB) sourced from the DROOP /
NB_DROOP pin, directly proportional to the read current, causes the related section output
voltage to vary according to the external RFB / RFB_NB resistor so implementing the desired
load-line effect. The current (IOS / IOS_NB) programmed through the OS / NB_OS pins is
sunk from the FB / NB_FB pins causing the output voltage to be offset according to the
resistance RFB / RFB_NB connected.
L6740L embeds a dual Remote-Sense Buffer to sense remotely the regulated voltage of
each Section without any additional external components. In this way, the output voltage
programmed is regulated compensating for board and socket losses. Keeping the sense
traces parallel and guarded by a power plane results in common mode coupling for any
picked-up noise.
Both DROOP and OFFSET function can be disabled: see Section 6.3 and Section 6.4 for
details about CORE Section and Section 6.6 and Section 6.7 for details about NB Section.
In case DROOP effect is not desired, the current information sourced from the DROOP pin
may be used to implement a Load Indicator as reported in Section 6.3 and Section 6.6.
1.2V
OS
from DAC...
CORE_REFERENCE
-IOS
IDROOP
Voltage positioning
CORE Protection
Monitor
IOS
CORE SECTION
VOLTAGE POSITIONING
Figure 9.
DROOP
ROS
FB
RFB_COMP
COMP
RF
VSEN
FBG
CF
To VDD_CORE
(Remote Sense)
IOS_NB
NB_OS
NB_DROOP
ROS_NB
IOS_NB
1.2V
IDROOP_NB
RFB
NB SECTION
VOLTAGE POSITIONING
6
Output voltage positioning
from DAC...
NB_REFERENCE
NB Protection
Monitor
NB_FB
RFB_COMP_NB
NB_COMP
RF_NB
CF_NB
NB_VSEN
NB_FBG
To VDD_NB
(Remote Sense)
RFB_NB
23/44
Output voltage positioning
6.1
L6740L
CORE section - Phase # programming
CORE Section implements a flexible 2 to 4 interleaved-phase converter. To program the
desired number of phase, simply short to SGND the PWMx signal that is not required to be
used according to Table 11. For three phase operation, short PWM4 to SGND while for two
phase operation, short PWM3 and PWM4 to SGND.
Caution:
For the disabled phase(s), the current reading pins need to be properly connected to avoid
errors in Current-Sharing and Voltage-Positioning: CSx+ needs to be connected to the
regulated output voltage while CSx- needs to be connected to CSx+ through the same Rg
resistor used for the active phases.
Table 11.
CORE section - Phase number programming
Phase number
PWM1
PWM2
1
PWM4
SGND
SGND
n/a
2
to Driver
3
to Driver
4
6.2
PWM3
SGND
to Driver
CORE section - Current reading and current sharing loop
L6740L embeds a flexible, fully-differential current sense circuitry for the CORE Section that
is able to read across inductor parasitic resistance or across a sense resistor placed in
series to the inductor element. The fully-differential current reading rejects noise and allows
placing sensing element in different locations without affecting the measurement's accuracy.
The trans-conductance ratio is issued by the external resistor Rg placed outside the chip
between CSx- pin toward the reading points. The current sense circuit always tracks the current information, the pin CSx+ is used as a reference keeping the CSx- pin to this voltage. To
correctly reproduce the inductor current an R-C filtering network must be introduced in parallel to the sensing element. The current that flows from the CSx- pin is then given by the following equation (See Figure 10):
DCR 1 + s ⋅ L ⁄ DCR
I CSx- = ------------- ⋅ -------------------------------------- ⋅ I
RG
1+s⋅R⋅C
PHASEx
Considering now to match the time constant between the inductor and the R-C filter applied
(Time constant mismatches cause the introduction of poles into the current reading network
causing instability. In addition, it is also important for the load transient response and to let
the system show resistive equivalent output impedance) it results:
L
------- = R ⋅ C
RL
⇒
RL
I CSx- = -------- ⋅ I PHASEx = I INFOx
RG
RG resistor is typically designed in order to have an information current IINFOx in the range of
about 35µA (IOCTH) at the OC Threshold.
24/44
L6740L
Output voltage positioning
Figure 10. Current reading - CORE section (left) and NB section (right)
Lx
ICSx-=IINFOx
DCRx
VOUT
INB_ISEN
R
C
CSx+
CSx-
RISEN
INB
From
ext Driver
RG
VDD Inductor DCR Current Sense
NB_ISEN
IPHASEx
NB Current Sense across LS Mosfet
The current read through the CSx+ / CSx- pairs is converted into a current IINFOx proportional to the current delivered by each phase and the information about the average current
IAVG = ΣIINFOx / N is internally built into the device (N is the number of working phases). The
error between the read current IINFOx and the reference IAVG is then converted into a voltage
that with a proper gain is used to adjust the duty cycle whose dominant value is set by the
voltage error amplifier in order to equalize the current carried by each phase.
6.3
CORE section - Load-line and load-indicator (Optional)
L6740L is able to introduce a dependence of the output voltage on the load current recovering part of the drop due to the output capacitor ESR in the load transient. Introducing a
dependence of the output voltage on the load current, a static error, proportional to the output current, causes the output voltage to vary according to the sensed current.
Figure 10 shows the Current Sense Circuit used to implement the Load-Line. The current
flowing across the inductor(s) is read through the R - C filter across CSx+ and CSx- pins. RG
programs a transconductance gain and generates a current ICSx proportional to the current
of the phase. The sum of the ICSx current is then sourced by the FB pin (IDROOP). RFB gives
the final gain to program the desired load-line slope (Figure 9).
Time constant matching between the inductor (L / DCR) and the current reading filter (RC)
is required to implement a real equivalent output impedance of the system so avoiding over
and/or under shoot of the output voltage as a consequence of a load transient. See
Section 6.2. The output characteristic vs. load current is then given by (Offset disabled):
DCR
V CORE = VID – R FB ⋅ I DROOP = VID – R FB ⋅ ------------- ⋅ I OUT = VID – R LL ⋅ I OUT
RG
Where RLL is the resulting load-line resistance implemented by the CORE Section.
The whole power supply can be then represented by a “real” voltage generator with an
equivalent output resistance RLL and a voltage value of VID.
RFB resistor can be then designed according to the RLL specifications as follow:
RG
R FB = R LL ⋅ ------------DCR
Caution:
Load-Line (DROOP) implementation is optional, in case it is not desired, the resulting current information may be employed for other purposes, such as an additional Load Indicator
25/44
Output voltage positioning
L6740L
(LI). In this case, simply connect a resistor RLI to SGND: the resulting voltage drop across
RLI will be proportional to the delivered current according to the following relationship:
DCR
V DROOP = R LI ⋅ ------------- ⋅ I OUT
RG
In case no additional information about the delivered current is requested, the DROOP pin
can be shorted to SGND.
Note:
Split between RFB_COMP and RFB_DROOP (Figure 9) is useful in custom designs where the
Droop effect is minimum (i.e. <50mV over 100A) to simplify the compensation network
design.
6.4
CORE section - Offset (Optional)
The OS pin allows programming a positive offset (VOS) for the CORE Section output voltage
by connecting a resistor ROS to SGND. The pin is internally fixed at 1.240V so a current is
programmed by connecting the resistor ROS between the pin and SGND: this current is mirrored and then properly sunk from the FB pin as shown in Figure 9. Output voltage is then
programmed as follow:
V CORE = VID – R FB ⋅ ( I DROOP – I OS )
Offset resistor can be designed by considering the following relationship (RFB is be fixed by
the Droop effect):
1.240V
R OS = ------------------- ⋅ R FB
V OS
Caution:
Offset implementation is optional, in case it is not desired, simply short the pin to SGND.
Note:
In the above formulas, RFB has to be considered being the total resistance connected
between FB pin and the regulated voltage.
6.5
NB section - Current reading
L6740L embeds a flexible, fully-differential current sense circuitry for the NB Section that is
able to read across Low-Side MOSFET RdsON or across a sense resistor placed in series to
the element. The trans-conductance ratio is issued by the external resistor RISEN placed
outside the chip between NB_ISEN pin and the Low-Side Drain. The current sense circuit
performs sample & hold of the current information. The current that flows from the NB_ISEN
pin is then given by the following equation (See Figure 10):
R dsON
I ISEN = ----------------- ⋅ I NB = I DROOP_NB
R ISEN
RISEN resistor is typically designed according to the OC Threshold. See Section 7.4 for
details.
26/44
L6740L
6.6
Output voltage positioning
NB section - Load-line and load-indicator (Optional)
This method introduces a dependence of the output voltage on the load current recovering
part of the drop due to the output capacitor ESR in the load transient. Introducing a dependence of the output voltage on the load current, a static error, proportional to the output current, causes the output voltage to vary according to the sensed current.
Figure 10 shows the Current Sense Circuit used to implement the Load-Line. The current
flowing across the Low-Side MOSFET is read through RISEN. RISEN programs a transconductance gain and generates a current IISEN proportional to the current delivered by the NB
Section that is then sourced by the NB_FB pin (IDROOP_NB). RFB_NB gives the final gain to
program the desired load-line slope (Figure 9).
The output characteristic vs. load current is then given by (Offset disabled):
R dsON
V OUT_NB = VID – R FB_NB ⋅ I DROOP_NB = VID – R FB_NB ⋅ ----------------- ⋅ I OUT = VID – R LL_NB ⋅ I OUT_NB
R ISEN
Where RLL_NB is the resulting Load-Line resistance implemented by the NB Section.
The whole power supply can be then represented by a “real” voltage generator with an
equivalent output resistance RLL_NB and a voltage value of VID.
RFB_NB resistor can be then designed according to the RLL_NB specifications as follow:
R ISEN
R FB_NB = R LL_NB ⋅ ----------------R dsON
Caution:
Load-Line (DROOP) implementation is optional, in case it is not desired, the resulting current information may be employed for other purposes, such as Load Indicator (LI). In this
case, simply connect a resistor RLI_NB to SGND: the resulting voltage drop across RLI_NB
will be proportional to the delivered current according to the following relationship:
R dsON
V NB_DROOP = R LI_NB ⋅ ----------------- ⋅ I OUT_NB
R ISEN
Note:
Split between RFB_COMP_NB and RFB_DROOP_NB (Figure 9) is useful in custom designs
where the Droop effect is minimum (i.e. <50mV over 100A) to simplify the compensation
network design.
6.7
NB section - Offset (Optional)
The NB_OS pin allows programming a positive offset (VOS_NB) for the NB Section output
voltage by connecting a resistor ROS_NB to SGND. The pin is internally fixed at 1.240V so a
current is programmed by connecting the resistor ROS_NB between the pin and SGND: this
current is mirrored and then properly sunk from the NB_FB pin as shown in Figure 9. Output
voltage is then programmed as follow:
V NB = VID – R FB_NB ⋅ ( I DROOP_NB – I OS_NB )
Offset resistor can be designed by considering the following relationship (RFB_NB may be
fixed by the Droop effect):
27/44
Output voltage positioning
L6740L
1.240V
R OS_NB = -------------------- ⋅ R FB_NB
V OS_NB
Caution:
Offset implementation is optional, in case it is not desired, simply short the pin to SGND.
Note:
In the above formulas, RFB_NB has to be considered being the total resistance connected
between NB_FB pin and the regulated voltage.
6.8
NB section - Maximum Duty-Cycle limitation
To provide proper time for current-reading across the Low-Side MOSFET, the device implements a duty-cycle limitation for the NB Section. This limitation is not fixed but it is linearly
variable with the current delivered to the load as follow:
⎧ 0.80 ⋅ T SW
T ON_NB(max) = ⎨
⎩ 0.40 ⋅ T SW
I NB_ISEN = 0µA
I NB_ISEN = 35µA
Duty Cycle limitation is variable with the delivered current to provide fast load transient
response at light load as well as assuring robust over-current protection.
6.9
On-The-Fly VID transitions
L6740L manages On-The-Fly VID Transitions that allow the Output Voltage of both sections
to modify during normal device operation for CPU power management purposes. OV, UV
and PWRGOOD signals are masked during every OTF-VID Transition and they are re-activated with a 16 clock cycle delay to prevent from false triggering.
When changing dynamically the regulated voltage (OTF-VID), the system needs to charge
or discharge the output capacitor accordingly. This means that an extra-current IOTF-VID
needs to be delivered (especially when increasing the output regulated voltage) and it must
be considered when setting the over current threshold of both the sections. This current
results:
dV OUT
I OTF-VID = C OUT ⋅ -----------------dT VID
where dVOUT / dTVID depends on the operative mode (3mV/µsec. in SVI or externally driven
in PVI).
Overcoming the OC threshold during the dynamic VID causes the device latch and disable.
Dynamic VID transition is managed in different ways according to the device operative
mode:
●
PVI mode.
L6740L checks for VID code modifications (See Figure 11) on the rising-edge of an
internal additional OTFVID-clock and waits for a confirmation on the following falling
edge. Once the new code is stable, on the next rising edge, the reference starts
stepping up or down in LSB increments every two OTFVID-clock cycle until the new
VID code is reached. During the transition, VID code changes are ignored; the device
28/44
L6740L
Output voltage positioning
re-starts monitoring VID after the transition has finished on the next rising-edge
available. OTFVID-clock frequency (FOTFVID) is 500kHz.
If the new VID code is more than 1 LSB different from the previous, the device will
execute the transition stepping the reference with the OTFVID-clock frequency FOTFVID
until the new code has reached. The output voltage rate of change will be of 12.5mV /
4µsec. = 3.125mV/µsec.
VID Sampled
VID Sampled
VID Sampled
VID Sampled
VID Stable
Ref Moved (1)
VID Sampled
VID Sampled
VID Stable
Ref Moved (1)
VID Sampled
VID Sampled
VID Stable
Ref Moved (1)
VID Sampled
VID Sampled
VID Stable
Ref Moved (1)
VID Sampled
VID Sampled
VID Sampled
VID Sampled
Ref Moved (4)
Ref Moved (3)
Ref Moved (2)
VID Sampled
VID Stable
Ref Moved (1)
VID Sampled
VID Sampled
Figure 11. PVI mode - On-The-Fly VID transitions
OTFVID Clock
t
VID [0:5]
t
Int. Reference
TOTFVID
Tsw
t
Vout
TVID
x 4 Step VID Transition
Vout Slope Controlled by internal
OTFVID-Clock Oscillator
●
4 x 1 Step VID Transition
Vout Slope Controlled by external
driving circuit (TVID)
t
SVI mode.
As soon as the controller receives a new valid command to set the VID level for one (or
both) of the two sections, the reference of the involved section steps up or down
according to the Target-VID with a 3mV/µsec. slope (Typ). until the new VID code is
reached.
If a new valid command is issued during the transition, the device updates the TargetVID level and performs the on-the-fly Transition up to the new code.Pre-PWROK Metal
VID
OTF-VID are not managed in this case because the Pre-PWROK Metal VID are stored
after EN is asserted.
●
V_FIX mode.
L6740L checks for SVC/SVD modifications and, once the new code is stable, it steps
the reference of both sections up or down according to the Target-VID with a
3mV/µsec. slope (Typ). until the new VID code is reached.
OV, UV and PWRGOOD are masked during the transition and re-activated with a 16 clock
cycle delay after the end of the transition to prevent from false triggering.
29/44
Output voltage positioning
6.10
L6740L
Soft-start
L6740L implements a soft-start to smoothly charge the output filter avoiding high in-rush
currents to be required to the input power supply. In SVI mode, Soft-Start Time is intended
as the time required by the device to set the output voltages to the Pre-PWROK Metal VID.
During this phase, the device increases the reference of the enabled section(s) from zero up
to the programmed reference in closed loop regulation. Soft-Start is implemented only when
VCC is above UVLO Threshold and the EN pin is set free. See Section 5 for details about
the SVI interface and how SVC/SVD are interpreted in this phase.
At the end of the digital Soft-Start, PWRGOOD signal is set free.
Protections are active during this phase as follow:
–
Under Voltage is enabled when the reference voltage reaches 0.5V.
–
Over Voltage is always enabled according to the programmed threshold (by ROVP).
–
FBDisconnection is enabled.
Reference is increased with fixed dV/dt; Soft-Start time depends on the programmed
voltage as follow:
T SS [ ms ] = Target_VID ⋅ 2.56
Figure 12. System Start-up: SVI (left) and PVI (right)
VDD_CORE
VDD_NB VDD_CORE
PWRGOOD
PWRGOOD
EN
EN
VDD_NB
6.10.1
LS-Less Start-up
In order to avoid any kind of negative undershoot on the load side during start-up, L6740L
performs a special sequence in enabling the drivers for both sections: during the soft-start
phase, the LS MOSFET is kept OFF (PWMx set to HiZ and ENDRVx = 0) until the first PWM
pulse. After the first PWM pulse, the PWMx outputs switches between logic “0” and logic “1”
and ENDRVx are set to logic “1”.
This particular sequence avoids the dangerous negative spike on the output voltage that
can happen if starting over a pre-biased output especially when exiting from a CORE-OFF
state.
Low-Side MOSFET turn-on is masked only from the control loop point of view: protections
are still allowed to turn-ON the Low-Side MOSFET in case of over voltage if needed.
30/44
L6740L
7
Output voltage monitoring and protections
Output voltage monitoring and protections
L6740L monitors the regulated voltage of both sections through pin VSEN and NB_VSEN in
order to manage OV, UV and PWRGOOD. The device shows different thresholds when in
different operative conditions but the behavior in response to a protection event is still the
same as described below.
Protections are active also during soft-start (See Section 6.10) while they are masked during OTF-VID transitions with an additional delay to avoid false triggering.
Table 12.
L6740L protection at a glance.
Section
Protection
CORE
Over voltage
(OV)
Under voltage
(UV)
PWRGOOD
SVI / PVI: Programmable threshold according to OVP pin.
V_FIX: Fixed to 1.8V; OVP pin is externally shorted to SGND.
Action: PWMx = 0 & ENDRVx = 1; Other Section (SVI only): PWMx = HiZ;
ENDRVx = 0; FLT driven High.
VSEN, NB_VSEN = VID -400mV. Active after Ref > 500mV
Action: All PWMx = HiZ; ENDRVx = 0; FLT Driven High.
PWRGOOD is the logic AND between internal CORE and NB PGOOD in SVI
mode while is the CORE section PGOOD in PVI mode.
Each PGOOD is set to zero when the related voltage falls below the
programmed reference -250mV.
Action: Section(s) continue switching, PWRGOOD driven low.
VSEN, NB_VSEN Set when VSEN > CS1- +600mV.
Disconnection Action: UV-Like
FBG, NB_FBG
Disconnection
7.1
30µA Pull-Up from NB_VSEN to set
OV (SVI Only).
Action: OV-Like
Internal Comparator across the opamp to recover from GND losses.
Action: UV-Like
Current Monitor across Inductor DCR.
Over current (OC) Dual Protection, per-phase and average.
Action: UV-Like
On-The-Fly VID
NORTH BRIDGE
Current Monitor across LS RdsON.
Constant Current, Valley CLimit.
Action: UV-Like
Masked with the exception of OC with additional 16 clock delay to prevent from
false triggering (both SVI and PVI).
Programmable over voltage
Once VCC crosses the turn-ON threshold and the device is enabled (EN = 1), L6740L provides an Over Voltage Protection for both the sections: when the voltage sensed by VSEN
and/or NB_VSEN overcomes the OV threshold, the controller:
–
Permanently sets the PWM of the involved section to zero keeping ENDRV of that
section high in order to keep all the Low-Side MOSFETs on to protect the load of
the Section in OV condition.
31/44
Output voltage monitoring and protections
L6740L
–
Permanently sets the PWM of the non-involved section to HiZ while keeping
ENDRV of the non-involved section low in order to realize an HiZ condition of the
non-involved section.
–
Drives the OSC/ FLT pin high.
–
Power supply or EN pin cycling is required to restart operations.
The OV threshold needs to be programmed through the OVP pin. Connecting the OVP pin
to SGND through a resistor ROVP, the OVP threshold becomes the voltage present at the
pin. Since the OVP pin sources a constant IOVP=11µA current, the programmed voltage
becomes:
OVP TH
OVP TH = R OVP ⋅ 11µA => R OVP = ------------------11µA
Filter OVP pin with 100pF(max) to SGND.
7.2
Feedback disconnection
L6740L provides both CORE and NB sections with FB Disconnection protection. This feature acts in order to stop the device from regulating dangerous voltages in case the remote
sense connections are left floating. The protection is available for both the sections and
operates for both the positive and negative sense.
According to Figure 13, the protection works as follow:
●
CORE Section:
Positive sense is performed monitoring the CORE output voltage through both VSEN
and CS1-. As soon as CS1- is more than 600mV higher than VSEN, the device latches
with all PWMx set to HiZ and ENDRVx set to zero. FLT pin is driven high. A 30µA pulldown current on the VSEN forces the device to detect this fault condition.
Negative sense is performed monitoring the internal opamp used to recover the SGND
losses by comparing its output and the internal reference generated by the DAC. As
soon as the difference between the output and the input of this opamp is higher than
500mV, the device latches with all PWMx set to HiZ and ENDRVx set to zero. FLT pin is
driven high.
●
NB Section (SVI Only)
Positive sense is performed sourcing a 50µA current that pulls-up the NB_VSEN pin in
order to force the device to detect an OV condition for the NB Section.
Negative sense is performed monitoring the internal opamp used to recover the SGND
losses by comparing its output and the internal reference generated by the DAC. As
soon as the difference between the output and the input of this opamp is higher than
500mV, the device latches with all PWMx set to HiZ and ENDRVx set to zero. FLT pin is
driven high.
To recover from a latch condition, cycle VCC or EN.
32/44
L6740L
Output voltage monitoring and protections
Figure 13. FB disconnection protection
500mV
500mV
FBG DISCONNECTED
FBG DISCONNECTED
CORE_REFERENCE
COMP
RF
VSEN
CF
CS1600mV
FBG
VSEN
DISCONNECTED
NB_FB
To VDD_CORE
NB_COMP
RF_NB
(Remote Sense)
RFB
CF_NB
NB_VSEN
NB_FBG
To VDD_NB
(Remote Sense)
RFB_NB
CORE SECTION - VSEN AND FBG DISCONNECTION
7.3
from DAC...
50µA
30µA
FB
NB_REFERENCE
from DAC...
NB SECTION - NB_VSEN AND NB_FBR DISCONNECTION
PWRGOOD
It is an open-drain signal set free after the soft-start sequence has finished; it is the logic
AND between the internal CORE and NB PGOOD (or just the CORE PGOOD in PVI mode).
It is pulled low when the output voltage of one of the two sections drops 250mV below the
programmed voltage. It is masked during On-The-Fly VID Transitions as well as when the
CORE section is set to OFF (from SVI bus) while the NB Section is still operative.
7.4
Over-current
The Over Current threshold has to be programmed to a safe value, in order to be sure that
each Section doesn't enter OC during normal operation of the device. This value must take
into consideration also the extra current needed during the OTF-VID Transition (IOTF-VID)
and the process spread and temperature variations of the sensing elements (DCR and
RdsON).
Moreover, since also the internal threshold spreads, the design has to consider the minimum/maximum values of the threshold. Considering the reading method, the two sections
will show different behaviors in OC.
7.4.1
CORE section
L6740L performs two different OC protections for the CORE Section: it monitors both the
average current and the per-phase current and allows to set an OC threshold for both.
–
OC_PHASE pin allows to define a maximum information current per-phase
(IINFOx). A ROC_TH resistor connected to SGND allows to define an end-of-scale
current (IOC_TH) that is compared with the information current generated for each
phase (IINFOx). If the current information for the single phase exceed the
programmed end-of-scale current (i.e. if IINFOx > IOC_TH), the device will turn-on
the LS mosfet until the threshold is re-crossed (i.e. until IINFOx < IOC_TH).
–
OC_AVG pin allows to define a maximum total output current for the system
(IOC_AVG). A copy of the DROOP current is sourced from the OC_AVG/LI pin. By
connecting a resistor ROC_AVG to SGND, a load indicator with 2.5V (VOC_AVGTH)
end-of-scale can be implemented. This means that when the voltage present at
the LI pin crosses VOC_AVGTH, the device detects an average OC (OC_AVG) and
immediately latches with all the mosfets of all the sections OFF (HiZ).
33/44
Output voltage monitoring and protections
L6740L
Typical design considers the intervention of the Average OC before the per-phase OC, leaving this last one as an extreme-protection in case of hardware failures in the external components. Typical design flow is the following:
–
Define the maximum total output current (IOC_AVGmax) according to system
requirements
–
Set IOC_TH to 35µA. This implies ROC_TH = 33kΩ (OC_PHASE pin is fixed to
1.24V and IOC_TH is the current programmed through ROC_TH).
–
Design RG resistor in order to have IINFOx = IOC_TH when IOUT is about 10% higher
than the IOC_AVGmax current. It results:
( 1.1 ⋅ I OC_AVGmax ) ⋅ DCR
R G = ----------------------------------------------------------------N ⋅ I OCTH
where N is the number of phases and DCR the DC resistance of the inductors. RG
should be designed in worst-case conditions.
–
Design ROC_AVG in order to have the OC_AVG/LI pin voltage to VOC_AVGTH at the
desired maximum current IOC_AVGmax. It results:
V OC_AVGTH ⋅ R G
R OC_AVG = ----------------------------------------------I OC_AVGmax ⋅ DCR
where VOC_AVGTH is typically 2.5V and IOC_AVGmax is the AVG_OC threshold
desired.
–
Adjust the defined values according to bench-test of the application.
–
An additional capacitor in parallel to ROC_AVG can be considered to add a delay in
the protection intervention.
Note:
What previoulsy listed is the typical design flow. In any case, custom design may require
different settings and ratios between the per-phase OC threshold and the AVG OC
threshold. Applications with huge ripple across inductors may required to set IOC_TH to
values higher than 35µA: in this case the threshold may be increased still keeping IOC_TH <
50µA.
7.4.2
NB section
Since the NB Section reads the current across Low-Side MOSFET, it limits the bottom of the
NB inductor current entering in Constant Current until UV. In particular, since the device limits the valley of the inductor current, the ripple entity, when not negligible, impacts on the real
OC threshold value and must be considered.
The device detects an Over Current condition when the current information IISEN overcomes
the fixed threshold of IOCTH_NB (35µA typ). When this happens, the device keeps the LowSide MOSFET on, also skipping clock cycles, until the threshold is crossed back and IISEN
results being lower than the IOCTH_NB threshold. After exiting the OC condition, the LowSide MOSFET is turned off and the High-Side is turned on with a duty cycle driven by the
PWM comparator.
The Section enters the Quasi-Constant-Current operation: the Low-Side MOSFET stays ON
until the current read becomes lower than IOCP_NB skipping clock cycles. The High-Side
MOSFET can be then turned ON with a TON imposed by the control loop after the Low-Side
MOSFET turn-off and the Section works in the usual way until another OC event is detected.
This means that the average current delivered can slightly increase in Quasi-Constant-Cur-
34/44
L6740L
Output voltage monitoring and protections
rent operation since the current ripple increases. In fact, the ON time increases due to the
OFF time rise because of the current has to reach the IOCP_NB bottom. The worst-case condition is when the ON time reaches its maximum value (see Section 6.8). When this happens, the Section works in Real Constant Current and the output voltage decrease as the
load increase. Crossing the UV threshold causes the device to latch accordingly.
It can be observed that the peak current (IPEAK_NB) is greater than IOCP_NB but it can be
determined as follow:
V IN – V OUT(min)
V IN – V OUT(min)
I PEAK_NB = I OCP_NB + --------------------------------------- ⋅ T ON(max) = I OCP_NB + --------------------------------------- ⋅ 0.40 ⋅ T SW
L NB
L NB
Where VOUT(min) is the UV threshold, (inductor saturation must be considered). When that
threshold is crossed, UV is detected. Cycle the power supply or the EN pin to restart operation.
The maximum average current during the Constant-Current behavior results (see
Figure 14):
I PEAK – I OCP_NB
I MAX_NB = I OCP_NB + ----------------------------------------2
in this particular situation, the switching frequency for the NB Section results reduced. The
ON time is the maximum allowed TON(max) while the OFF time depends on the application:
I PEAK – I OCP_NB
T OFF = L NB ⋅ -----------------------------------------V OUT
1
f = -----------------------------------------T ON(max) + T OFF
The transconductance resistor RISEN can be designed considering that the Section limits
the inductor current ripple valley. Moreover the additional current due to the output filter
charge during on-the-Fly VID transitions must be considered.
I OCP_NB(max) ⋅ R dsON(max)
R ISEN = ----------------------------------------------------------------I OCTH_NB(min)
where IOCP_NB is defined above.
Figure 14. NB Section - Constant current operation.
Constant Current (Exploded)
IPEAK_NB
VOUT
0.40 VIN
Voltage Positioning
IMAX_NB
TON(max) LS ON Skipping
Clock Cycles
TSW
TON(max)
UVP Threshold
TSW
IOCP_NB
(IDROOP_NB = 35µA)
Quasi-Const.
Current
Droop Effect
IOCP_NB
IOUT
IMAX_NB
35/44
Main oscillator
8
L6740L
Main oscillator
The controller embeds a dual-Oscillator: one section is used for the CORE and it is a
multiphase programmable oscillator managing equal phase-shift among all phases and the
other section is used for the NB section. Phase-Shift between the CORE and NB ramps is
automatically adjusted according to the CORE phase # programmed.
The internal oscillator generates the triangular waveform for the PWM charging and
discharging with a constant current an internal capacitor. The switching frequency for each
channel, FSW, is internally fixed at 150kHz: the resulting switching frequency for the CORE
section at the load side results in being multiplied by N (number of configured phases).
The current delivered to the oscillator is typically 22µA (corresponding to the free running
frequency FSW=150kHz) and it may be varied using an external resistor (ROSC) typically
connected between the OSC pin and SGND. Since the OSC pin is fixed at 1.240V, the
frequency is varied proportionally to the current sunk from the pin considering the internal
gain of 6.8KHz/µA (See Figure 15).
Connecting ROSC to SGND the frequency is increased (current is sunk from the pin),
according to the following relationships:
6
1.240V
kHz
8.432 ⋅ 10 F SW = 150kHz + ---------------------------- ⋅ 6.8 ----------- = 150kHz + ---------------------------R OSC ( kΩ )
µA
R OSC ( kΩ )
Figure 15. ROSC vs. switching frequency
1000
900
Switching Frequency [kHz]
800
700
600
500
400
300
200
100
10
100
Rosc Resistor [kOhms]
36/44
1000
L6740L
System control loop compensation
The device embeds two separate and independent control loops for CORE and NB section.
The control loop for NB section is a simple Voltage-Mode control loop with (optional) voltage
positioning featured when DROOP pin is shorted with FB. The control loop for the CORE
section also features a Current-Sharing loop to equalize the current carried by each of the
configured phases.
The CORE control system can be modeled with an equivalent Single-Phase converter
whose only difference is the equivalent inductor L/N (where each phase has an L inductor
and N is the number of the configured phases). See Figure 16.
Figure 16. Equivalent control loop for NB and CORE sections.
CO
ZF(s)
Ref
FBG
COMP
RF
VID_CORE
VSEN
NB_FBG
RF_NB CF-NB
NB_VSEN
IDROOP_NB
NB_FB
NB_COMP
VID_NB
VOUT
ESR
VCOMP
VNB_COMP
Ref
LCORE/N
RO
CO_NB
d VCOMP
PWM
RO_NB
ESR_NB
VOUT_NB
FB
LNB
IDROOP
d VNB_COMP
DROOP
PWM
NB_DROOP
9
System control loop compensation
CF
ZF(s)
ZFB(s)
RFB_NB
ZFB(s)
RFB
This means that the same analysis can be used for both the sections with the only exception
of the different equivalent inductor value (L=LNB for NB Section and L=LCORE/N for the
CORE section) and the current reading gain (RdsON/RISEN for NB Section and DCR/RG for
the CORE Section).
The Control Loop gain results (obtained opening the loop after the COMP pin):
PWM ⋅ Z F ( s ) ⋅ ( R LL + Z P ( s ) )
G LOOP ( s ) = – ------------------------------------------------------------------------------------------------------------------ZF ( s ) ⎛
1
[ Z P ( s ) + Z L ( s ) ] ⋅ -------------+ 1 + ------------⎞ ⋅ R FB
A(s) ⎝
A ( s )⎠
Where:
●
RLL is the equivalent output resistance determined by the droop function;
●
ZP(s) is the impedance resulting by the parallel of the output capacitor (and its ESR)
and the applied load RO;
●
ZF(s) is the compensation network impedance;
●
ZL(s) is the equivalent inductor impedance;
●
A(s) is the error amplifier gain;
●
V IN
9
PWM = ------ ⋅ ------------------- is the PWM transfer function.
10 ∆V OSC
The Control Loop gain for each section is designed in order to obtain a high DC gain to
minimize static error and to cross the 0dB axes with a constant -20dB/Dec. slope with the
desired crossover frequency ωT. Neglecting the effect of ZF(s), the transfer function has one
zero and two poles; both the poles are fixed once the output filter is designed (LC filter
resonance ωLC) and the zero (ωESR) is fixed by ESR and the Droop resistance.
37/44
System control loop compensation
L6740L
Figure 17. Control loop bode diagram and fine tuning (not in scale).
dB
dB
CF
GLOOP(s)
GLOOP(s)
K
K
ZF(s)
RF[dB]
ZF(s)
RF[dB]
RF
ωLC = ωF
ωESR
ωT
ω
ωLC = ωF
ωESR
ωT
ω
To obtain the desired shape an RF-CF series network is considered for the ZF(s)
implementation. A zero at ωF=1/RFCF is then introduced together with an integrator. This
integrator minimizes the static error while placing the zero ωF in correspondence with the LC resonance assures a simple -20dB/Dec. shape of the gain.
In fact, considering the usual value for the output filter, the LC resonance results to be at
frequency lower than the above reported zero.
Compensation network can be simply designed placing ωF=ωLC and imposing the crossover frequency ωT as desired obtaining (always considering that ωT might be not higher than
1/10th of the switching frequency FSW):
R FB ⋅ ∆V OSC 9
L
R F = ---------------------------------- ⋅ ------ ⋅ ω T ⋅ ------------------------------------------V IN
10
N ⋅ ( R LL + ESR )
CO ⋅ L
C F = ------------------RF
9.1
Compensation network guidelines
The Compensation Network design assures to having system response according to the
cross-over frequency selected and to the output filter considered: it is anyway possible to
further fine-tune the compensation network modifying the bandwidth in order to get the best
response of the system as follow (See Figure 17):
–
Increase RF to increase the system bandwidth accordingly;
–
Decrease RF to decrease the system bandwidth accordingly;
–
Increase CF to move ωF to low frequencies increasing as a consequence the
system phase margin.
Having the fastest compensation network gives not the confidence to satisfy the
requirements of the load: the inductor still limits the maximum dI/dt that the system can
afford. In fact, when a load transient is applied, the best that the controller can do is to
“saturate” the duty cycle to its maximum (dMAX) or minimum (0) value. The output voltage
dV/dt is then limited by the inductor charge / discharge time and by the output capacitance.
In particular, the most limiting transition corresponds to the load removal since the inductor
results being discharged only by VOUT (while it is charged by dMAXVIN-VOUT during a load
appliance).
38/44
L6740L
LTB technology™
LTB Technology™ further enhances the performances of Dual-Edge Asynchronous
Systems by reducing the system latencies and immediately turning ON all the phases to
provide the correct amount of energy to the load. By properly designing the LTB network as
well as the LTB Gain, the undershoot and the ring-back can be minimized also optimizing
the output capacitors count. LTB Technology™ applies only to the CORE Section.
LTB Technology™ monitors the output voltage through a dedicated pin detecting LoadTransients with selected dV/dt, it cancels the interleaved phase-shift, turning-on
simultaneously all phases. it then implements a parallel, independent loop that reacts to
Load-Transients bypassing E/A latencies.
LTB Technology™ Control Loop is reported in Figure 18.
Figure 18. LTB technology™ control loop (CORE section).
LTB Ramp
LTB
LT Detect
PWM_BOOST
L/N
VOUT
ESR
d VCOMP
VSEN
RFB
CH
ZF(s)
LTB
DROOP
FBG
FB
LT Detect
CF
COMP
VID
Monitor
CFB
Ref
IDROOP
VCOMP
CO
RO
PWM
RF
10
LTB technology™
ZFB(s)
RLTB
CLTB
The LTB detector is able to detect output load transients by coupling the output voltage
through an RLTB - CLTB network. After detecting a load transient, the LTB Ramp is reset and
then compared with the COMP pin level. The resulting duty-cycle programmed is then ORed with the PWMx signal of each phase by-passing the main control loop. All the phases will
then be turned-on together and the EA latencies results bypassed as well.
Sensitivity of the Load Transient Detector and the Gain of the LTB Ramp can be
programmed in order to control precisely both the undershoot and the ring-back.
●
Detector Design. RLTB - CLTB is design according to the output voltage deviation dVOUT
which is desired the controller to be sensitive as follow:
dV OUT
R LTB = ----------------25µA
1
C LTB = ------------------------------------------------2π ⋅ N ⋅ R LTB ⋅ F SW
39/44
LTB technology™
●
L6740L
Gain Design. Through the LTBGAIN pin it is possible to modify the slope of the LTB
Ramp in order to modulate the entity of the LTB response once the LT has been
detected. In fact, the response depends on the board design and its parasitics requiring
different actions from the controller.
Leaving the LTBGAIN pin floating, the maximum pulse-width is programmed. The slope
of the LTB ramp will be equal to 1/2 of the OSC ramp slope.
Connecting RLTBGAIN to GND, the LTB Ramp slope can be modified as follow:
I LTBGAIN⎞
LTBRamp Slope = OSC Slope ⋅ ⎛⎝ 1 + ----------------------I OSC ⎠
Where ILTBGAIN is the current sunk from LTBGAIN pin and IOSC is the OSC current
(20µA plus the current sunk from the OSC pin).
LTB TechnologyTM Design Tips.
40/44
–
Decrease RLTB to increase the system sensitivity making the system sensitive to
smaller dVOUT.
–
Increase CLTB to increase the system sensitivity making the system sensitive to
higher dV/dt.
–
Increase RLTBGAIN to increase the width of the LTB pulse reducing the system
ring-back.
L6740L
11
Layout guidelines
Layout guidelines
Layout is one of the most important things to consider when designing high current
applications. A good layout solution can generate a benefit in lowering power dissipation on
the power paths, reducing radiation and a proper connection between signal and power
ground can optimize the performance of the control loops.
Two kind of critical components and connections have to be considered when laying-out a
VRM based on L6740L: power components and connections and small signal components
connections.
11.1
Power components and connections
These are the components and connections where switching and high continuous current
flows from the input to the load. The first priority when placing components has to be
reserved to this power section, minimizing the length of each connection and loop as much
as possible. To minimize noise and voltage spikes (EMI and losses) these interconnections
must be a part of a power plane and anyway realized by wide and thick copper traces: loop
must be anyway minimized. The critical components, i.e. the power transistors, must be
close one to the other. The use of multi-layer printed circuit board is recommended.
Since L6740L uses external drivers to switch the power MOSFETs, check the selected
driver documentation for informations related to proper layout for this part.
11.2
Small signal components and connections
These are small signal components and connections to critical nodes of the application as
well as bypass capacitors for the device supply. Locate the bypass capacitor close to the
device and refer sensible components such as frequency set-up resistor ROSC, offset
resistor (both Sections) and OVP resistor ROVP to SGND. Star grounding is suggested:
connect SGND to PGND plane in a single point to avoid that drops due to the high current
delivered causes errors in the device behavior.
VSEN pin filtered vs. SGND helps in reducing noise injection into device and EN pin filtered
vs. SGND helps in reducing false trip due to coupled noise: take care in routing driving net
for this pin in order to minimize coupled noise.
Remote Buffer Connection must be routed as parallel nets from the FBG/FBR pins to the
load in order to avoid the pick-up of any common mode noise. Connecting these pins in
points far from the load will cause a non-optimum load regulation, increasing output
tolerance.
Locate current reading components close to the device. The PCB traces connecting the
reading point must use dedicated nets, routed as parallel traces in order to avoid the pick-up
of any common mode noise. It's also important to avoid any offset in the measurement and,
to get a better precision, to connect the traces as close as possible to the sensing elements.
Symmetrical layout is also suggested. Small filtering capacitor can be added, near the
controller, between VOUT and SGND, on the CSx- line when reading across inductor to allow
higher layout flexibility.
41/44
TQFP48 mechanical data & package dimensions
12
L6740L
TQFP48 mechanical data & package dimensions
Figure 19. TQFP48 mechanical data & package dimensions
mm
inch
DIM.
MIN.
TYP.
A
MAX.
MIN.
TYP.
1.20
A1
0.05
0.15
0.002
A2
0.95
1.00
1.05
0.037
0.039
b
0.17
0.22
0.27
0.006
0.008
c
0.09
0.20
0.004
D
8.80
9.00
9.20
0.346
0.354
D1
6.80
7.00
7.20
0.268
0.276
D2
2.00
4.25
0.079
D3
5.50
e
0.50
E
8.80
9.00
E1
6.80
7.00
E2
2.00
E3
L
L1
k
ccc
0.60
0.006
0.041
0.010
0.008
0.362
0.283
0.167
0.020
9.20
0.346
0.354
7.20
0.268
0.276
4.25
0.079
0.362
0.283
0.167
Body: 7 x 7 x 1.0mm
0.217
0.50
0.45
OUTLINE AND
MECHANICAL DATA
0.217
5.50
e
MAX.
0.047
0.019
0.75
1.00
0.018
0.024
0.030
0.039
TQFP48 - EXPOSED PAD
0˚(min.), 3.5˚(typ.), 7˚(max.)
0.08
0.0031
7222746 B
42/44
L6740L
13
Revision history
Revision history
Table 13.
Document revision history
Date
Revision
Changes
07-Jun-2007
1
First release
01-Aug-2007
2
Databrief updated to datasheet
43/44
L6740L
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44/44