UCC3588 PRELIMINARY 5-Bit Programmable Output BiCMOS Power Supply Controller FEATURES DESCRIPTION • 5-Bit Digital-to-Analog Converter (DAC) supports Intel Pentium II The UCC3588 synchronous step-down (Buck) regulator provides accurate high efficiency power conversion. Using few external components, the UCC1588 converts 5V to an adjustable output ranging from 3.5VDC to 2.1VDC in 100mV steps and 2.05VDC to 1.3VDC in 50mV steps with 1% DC system accuracy. A high level of integration and novel design allow this 16-pin controller to provide a complete control solution for today’s demanding microcontroller power requirements. Typical applications include on board or VRM based power conversion for Intel Pentium II microprocessors, as well as other processors from a variety of manufacturers. High efficiency is obtained through the use of synchronous rectification. • Microprocessor VID Codes • Compatible with 5V or 12V Systems • 1% Output Voltage Accuracy Guaranteed • Drives 2 N-Channel MOSFETs • Programmable Frequency to 800kHz • Power Good OV / UV / OVP Voltage Monitor The softstart function provides a controlled ramp up of the system output voltage. Overcurrent circuitry detects a hard (or soft) short on the system output voltage and invokes a timed softstart/shutdown cycle to reduce the PWM controller on time to 5%. • Undervoltage Lockout and Softstart Functions • Short Circuit Protection The oscillator frequency is externally programmed with RT and operates over a range of 50kHz to 800kHz. The gate drivers are low impedance totem pole output stages capable of driving large external MOSFETs. Cross conduction is eliminated by fixed delay times between turn off and turn on of the external high side and synchronous MOSFETs. The chip includes undervoltage lockout circuitry which assures the correct logic states at the outputs during power up and power down. • Low Impedance MOSFET Drivers • Chip Disable (continued) APPLICATION DIAGRAM 12V IN 5V IN + C15 150µF C16 10µF R1 10K R4 3Ω UCC3588 + C1 D0 + C2 + C3 15 VCC DRVHI 13 11 PWRGOOD DRVLO 14 L1 1.6µH + C4 C1-C4 1500µF D1 D2 D3 D4 4 D0 ISNS 2 5 D1 VSENSE 1 6 D2 VFB 10 7 D3 COMP 9 8 D4 3 SS/ENBL RT RTN R5 3Ω R3 200k R6 0.003Ω C8-C12 1500µF Q2 IRL3103 + C6 220pF VOUT C8 + C9 + + + + C10 C11 C12 C14 150µF C7 22pF GND D1 12 R7 15k 16 C5 33nF Q1 IRL3103 R2 47k D2 R8 20k C13 1nF RTN UDG-98158 SLUS311 - JULY 1999 UCC3588 CONNECTION DIAGRAMS ABSOLUTE MAXIMUM RATINGS Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V Gate Drive Current, 50% Duty Cycle. . . . . . . . . . . . . . . . . . 1A Input Voltage, VSENSE, VFB, SS, COMMAND, COMP . . . . . 5V Input Voltage, D0, D1, D2, D3, D4 . . . . . . . . . . . . . . . . . . . 6V Input Current, RT, COMP . . . . . . . . . . . . . . . . . . . . . . . . . 5mA DIP-16, SOIC-16, TSSOP-16 (TOP VIEW) N, J, D and PW Packages Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. All voltages are referenced to GND. THERMAL DATA Plastic DIP Package Thermal Resistance Junction to Leads, θjc . . . . . . . . 45°C/W Thermal Resistance Junction to Ambient, θja . . . . . . 90°C/W Ceramic DIP Package Thermal Resistance Junction to Leads, θjc . . . . . . . . 28°C/W Thermal Resistance Junction to Ambient, θja . . . . . 120°C/W Standard Surface Mount Package Thermal Resistance Junction to Leads, θjc . . . . . . . . 35°C/W Thermal Resistance Junction to Ambient, θja . . . . . 120°C/W VSENSE 1 16 RT ISNS 2 15 VCC SS/ENBL 3 14 DRVLO D0 4 13 DRVHI D1 5 12 GND D2 6 11 PWRGOOD D3 7 10 VFB D4 8 9 COMP SOIC-20 (TOP VIEW) DW Package Note: The above numbers for ja and jc are maximums for the limiting thermal resistance of the package in a standard mounting configuration. The ja numbers are meant to be guidelines for the thermal performance of the device and PC-board system. All of the above numbers assume no ambient airflow, see the packaging section of Unitrode Product Data Handbook for more details. DESCRIPTION (cont.) This device is available in 16- pin surface mount, plastic and ceramic DIP, TSSOP packages, and 20 pin surface mount. The UCC3588 is specified for operation from 0°C to +70°C. VSENSE 1 20 RT ISNS 2 19 VCC SS/ENBL 3 18 PVCC N/C 4 17 DRVLO D0 5 16 DRVHI D1 6 15 PGND D2 7 14 GND N/C 8 13 PWRGOOD D3 9 12 VFB D4 10 11 COMP ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications hold for TA = 0°C to 70°C. TA = TJ. VCC = 12V, RT = 49k. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Supply Current Section Supply Current, On VCC = 12V, VRT = 2V 4.5 5.5 mA 10.05 10.50 10.85 V 350 450 550 mV UVLO Section VCC UVLO Turn-On Threshold UVLO Threshold Hysteresis Voltage Error Amplifier Section Input Bias Current VCM = 2.0V Open Loop Gain (Note 5) Output Voltage High ICOMP = –500µA Output Voltage Low ICOMP = +500µA Output Source Current Output Sink Current –0.025 –0.050 µA 77 dB 3.5 3.6 V VVFB = 2V, VCOMMAND = VCOMP = 2.5V –400 –500 µA VVFB = 3V, VCOMMAND = VCOMP = 2.5V 5 10 mA 0.2 2 0.5 V UCC3588 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications hold for TA = 0°C to 70°C. TA = TJ. VCC = 12V, RT = 49k. PARAMETER TEST CONDITIONS MIN TYP 250 270 MAX UNITS Oscillator/PWM Section Initial Accuracy 0°C <TA < 70°C 290 kHz Ramp Amplitude (p–p) 1.85 V Ramp Valley Voltage 0.65 V PWM Max Duty Cycle COMP = 3V (Note 5) 100 % PWM Min Duty Cycle COMP = 0. 3V (Note 5) 0 % PWM Delay to Outputs (High to Low) COMP = 1.5V (Note 5) 150 ns PWM Delay to Outputs (Low to High) COMP = 1.5V (Note 5) 150 ns 3 % Transient Window Comparator Section Detection Range High (Duty Cycle = 0) % Over VCOMMAND, (Note 1) Detection Range Low (Duty Cycle = 1) % Under VCOMMAND, (Note 1) –3 Propagation Delay (VSENSE to Outputs) 150 % 200 nS –12 µA Soft Start/ Shutdown Section SS Charge Current (Normal Start Up) Measured on SS –6 SS Charge Current (Short Circuit Fault Condition) Measured on SS –60 –100 –120 µA SS Discharge Current (During Timeout Sequence) Measured on SS 1 2.5 5 µA Shutdown Threshold Measured on SS 4.1 4.2 4.3 V Restart Threshold Measured on SS 0.4 0.5 0.6 V Soft Start Complete Threshold (Normal Start-Up) Measured on SS 3.5 3.7 3.9 V 10.8V < VCC < 13.2V, measured on COMP, 0°C < TA < +70°C, (Note 2) –1.0 1.0 % DAC / Reference Section COMMAND Voltage Accuracy D0–D4 Voltage High 5.5 6 6.5 V D0–D4 Voltage Threshold 2.5 3.0 3.5 V –80 –100 D0–D4 Voltage Input Bias Current V(D4,...,D0) < 0.5V µA Overvoltage Comparator Section Trip Point % Over VCOMMAND, (Note 1) Hysteresis 8 10 20 12 % 35 mV –12.0 % 35 mV 470 Ω Undervoltage Comparator Section Trip Point % Under VCOMMAND, (Note 1) Hysteresis –8.0 10 20 PWRGOOD Signal Section Output Impedance VCC = 12V, IPWRGOOD = 1mA Overvoltage Protection Section Trip Point % Over VCOMMAND, (Note 1) 15 Hysteresis VSENSE Input Bias Current OV, OVP, UV Combined 3 –8 17.5 20 % 20 35 mV –12 –16 µA UCC3588 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications hold for TA = 0°C to 70°C. TA = TJ. VCC = 12V, RT = 49k. PARAMETER TEST CONDITIONS MIN TYP 10.8 11.5 MAX UNITS Gate Drivers (DRVHI, DRVLO) Section Output High Voltage IGATE = 100mA, VCC = 12V Output Low Voltage IGATE =– 100mA, VCC = 12V Driver Non-overlap Time (DRVHI– to DRVLO+) (Note 3) Driver Non-overlap Time (DRVLO– to DRVHI+) (Note 3) Driver Rise Time Driver Fall Time V 0.5 0.8 V 90 120 150 ns 50 80 120 ns 3nF Capacitive Load 80 100 ns 3nF Capacitive Load 80 100 ns Start of Quick Charge to Shutdown Threshold VISNS = VSENSE + 75mV, CSS = 10nF, (Note 4) (Note 5) 50 Current Limit Threshold Voltage VTHRESHOLD = VISNS – VVSENSE Current Limit Section ISNS Input Bias Current µs 40 54 70 mV –8 –12 –16 µA Note 1: This percentage is measured with respect to the ideal command voltage programmed by the VID (D0,....,D4) pins and applies to all DAC codes from 1.3 to 3.5V. Note 2: Reference and error amplifier offset trimmed while the voltage amp is set in unity gain mode. Note 3: Deadtime delay is measured from the 50% point of DRVHI falling to the 50% point of DRVLO rising, and vice-verse. Note 4: This time is dependent on the value of CSS. Note 5: Guaranteed by design. Not 100% tested in production. BLOCK DIAGRAM COMP 9 VOLTAGE AMPLIFIER VFB 10 D4 8 D3 7 D2 6 D1 5 PWM COMP. – + S COMMAND R Q TURN ON DELAY OVP TURN ON DELAY 4 SHUTDOWN DUTY=1 SS/ENBL 3 SOFTSTART 13 DRVHI ANTI CROSSCONDUCTION SHUTDOWN D0 DRVLO SHUTDOWN OV/UV DAC 14 TO VREF COMMAND –3% VSENSE DUTY=0 OVERCURRENT OSC VBIAS CURRENT LIMIT BLOCK COMMAND +3% VCC – + + 2 1 ISNS VSENSE 11 PWRGOOD UVLO + 10.5V – VREF 15 VCC 12 GND 16 RT UDG-98152 4 UCC3588 PIN DESCRIPTION COMP: (Voltage Amplifier Output) The system voltage compensation network is applied between COMP and VFB. on resistance of the open-drain switch is no higher than 470Ω. This output should be pulled up to a logic level voltage and should be programmed to sink 1mA or less. D0, D1, D2, D3, D4: These are the digital input control codes for the DAC. The DAC is comprised of two ranges set by D4, with D0 representing the least significant bit (LSB) and D3, the most significant bit (MSB). A bit is set low by being connected the pin to GND; a bit is set high by floating the pin. Each control pin is pulled up to approximately 6V by an internal pull-up. If one of the low voltage codes is commanded on the DAC inputs, the outputs will be disabled. The outputs will also be disabled for all 1’s, the NO CPU command. RT: (Oscillator Charging Current) This pin is a low impedance voltage source set at ~1.25V. A resistor from RT to GND is used to program the internal PWM oscillator frequency. The equation for RT follows: 1 − 800 RT = (f • 67. 2pF ) (1) SS/ENBL: (Soft Start/Shut Down) A low leakage capacitor connected between SS and GND will provide a softstart function for the converter. The voltage on this capacitor will slowly charge on start-up via an internal current source (10µA typ.) and ultimately clamp at approximately 3.7V. The output of the voltage error amplifier (COMP) tracks this voltage thereby limiting the controller duty ratio. If a short circuit is detected, the clamp is released and the cap on SS charges with a 100µA (typ) current source. If the SS voltage exceeds 4.2V, the converter shuts down, and the 100µA current source is switched off. The SS cap will then be discharged with a 2.5µA (typ) current sink. When the voltage on SS falls below 0.5V, a new SS cycle is started. The equation for softstart time follows: DRVHI: (PWM Output, MOSFET Driver) This output provides a low Impedance totem pole driver. Use a series resistor between this pin and the gate of the external MOSFET to prevent excessive overshoot. Minimize circuit trace length to prevent DRVHI from ringing below GND. DRVHI is disabled during UVLO conditions. DRVHI has a typical output impedance of 5Ω for a VCC voltage of 12V. DRVLO: (synchronous rectifier output, MOSFET driver) This output provides a low Impedance totem pole driver to drive the low-side synchronous external MOSFET. Use a series resistor between this pin and the gate of the external MOSFET to prevent excessive overshoot. Minimize circuit trace length to prevent DRVLO from ringing below GND. DRVLO is disabled during UVLO conditions. DRVLO has a typical output impedance of 5Ω for a VCC voltage of 12V. C SS . TSS = 3 .7 10 µA (2) Shutdown is accomplished by pulling SS/SD below 0.5V. GND: (Ground) All voltages measured with respect to ground. Vcc should be bypassed directly to GND with a 0.1µF or larger ceramic capacitor. The timing capacitor discharge current also returns to this pin, so the lead from the oscillator timing to GND should be as short and direct as possible. VCC: (Positive Supply Voltage) This pin is normally connected to a 12V ±10% system voltage. The UCC1588 will commence normal operation when the voltage on VCC exceeds 10.5V (typ). Bypass VCC directly to GND with a 0.1µF (minimum) ceramic capacitor to supply current spikes required to charge external MOSFET gate capacitances. ISNS: (Current Limit Sense Input) A resistance connected between this sense connection and Vsense sets up the current limit threshold (54mV typical voltage threshold). VFB: (Voltage Amplifier Inverting Input) This is normally connected to a compensation network and to the power converter output through a divider network. PWRGOOD: This pin is an open drain output which is driven low to reset the microprocessor when VSNS rises above or falls below its nominal value by 8.5%(typ). The VSENSE: (Direct Output Voltage Connection) This pin is a direct kelvin connection to the output voltage used for over voltage, under voltage, and current sensing. 5 UCC3588 APPLICATION DIAGRAM 12V IN 5V IN + C15 150µF C16 10µF R1 10K R4 3Ω UCC3588 + + + + C1 C2 C3 C4 D0 C1-C4 1500µF D1 D2 D3 D4 15 VCC DRVHI 13 11 PWRGOOD DRVLO 14 4 D0 ISNS 5 D1 VSENSE 1 6 D2 VFB 10 7 D3 COMP 9 8 D4 3 SS/ENBL RT Q1 IRL3103 L1 1.6µH R5 3Ω 2 R3 200k R6 0.003Ω C8-C12 1500µF VOUT Q2 IRL3103 + + C6 220pF C8 C9 + + + + C10 C11 C12 C14 150µF C7 22pF GND R7 15k 16 C5 33nF D1 12 R2 47k D2 R8 20k C13 1nF RTN RTN UDG-98158 APPLICATION INFORMATION 2) To properly approximate the full load duty cycle operating range, assumptions are made regarding the MOSFETs’ RdsON, and the output inductor’s DC resistance. Q1 and Q2 are IRF3103s, each with an RdsON of 0.014Ω. The output inductor is allowed to dissipate one watt under full load, giving a DC resistance of 6.9mΩ, and R6 is 3mΩ. The resulting duty cycle at the operating extremes is then: Figure 1 shows a synchronous regulator using the UCC3588. It accepts +5V and +12V as input, and delivers a regulated DC output voltage. The value of the output voltage is programmable via a 5-bit DAC code to a value between 1.3V and 3.5V. The example given here is for a 12A regulator, running from a 10% tolerance source, and operating at 300kHz. The design of the power stage is straightforward buck regulator design. Assuming an output noise requirement of 50mV, and an output ripple current of 20% of full load, the value of the output inductor should be calculated at the highest input voltage and lowest output voltage that the regulator is likely to see. This insures that the ripple current will decrease as the input voltage and output voltage differential decreases. The minimum duty cycle, δmin, should also be calculated under this condition. δ min = = δ max = 1) The current sense resistor is chosen to allow current limit to occur at 1.4 times the full load current. R6 = VTRIP (1. 4 • IOUT ) = 50 mV = 3mΩ 16 .8 A VOUT (lo ) + IOUT • (R 6 + Rds ON + R (4) ) (5) VIN(hi ) 1.8 + (12 • 0.024) = 0 .379 5 .5 VOUT (hi ) + IOUT • (R 6 + Rds ON + R = (3) ) VIN(lo ) 3 .5 + (12 • 0.024) = 0 .842 4 .5 3) The value of the output inductor is chosen at the worst case ripple current point. 6 UCC3588 APPLICATION INFORMATION (cont.) L= = (V IN( hi ) ) − VOUT (lo ) • δ minTS (6) And the Turn OFF losses are estimated as PT (OFF )Q1 = 12 VIN(hi ) • ID (pk ) • tf • FS = 0.56 W ∆ IOUT (5 .5 − 1.8) • 0 .379 • 3 .333 µ 2. 4 =1.9 µ H The total loss in Q1is the sum of the three components, or about 2.1 watts. The gate drive losses in Q2 will be the same as in Q1, but the turn OFF losses will be associated with the reverse recovery of the body diode, instead of the turn OFF of the channel. This is due to the UCC3588’s delay built into the switching of the upper and lower MOSFET’s drive. For example, when Q1 is turned OFF, the turn ON of Q2 is delayed for about 100ns, insuring that the circuit has time to commutate and that current has begun to flow in the body diode of Q2. When Q2 is turned OFF, current is diverted from the channel of Q2 into the body diode of Q2, resulting in virtually no power dissipation. When Q1 is turned ON 100ns later however, the circuit is forced to commutate again. This time causing reverse recovery loss in the body diode of Q2 as its polarity is reversed. The loss in the diode is expressed as: Four turns of #16 on a micrometals T51-52C core has an inductance of 1.9µH, has a DC resistance of 6.6mΩ, and will dissipate about 1W under full load conditions. With an output inductor value of 1.9µH, the ripple current will be 1750mA under the low-input-high-output condition. 4) To meet the output noise voltage requirement, the output capacitor(s) must be chosen so that the ripple voltage induced across the ESR of the capacitors by the output ripple current is less than 50mv. ESR < 50 mV = 42 mΩ ∆ IOUT (7) Additionally, to meet output load transient response requirements, the capacitors’ ESL and ESR must be low enough to avoid excessive voltage transient spikes. (See Application Note U-157 for a discussion of how to determine the amount and type of load capacitance.) For this example, four Sanyo MV-GX 1500µf, 6.3V capacitors will be used. The ESR of each capacitor is approximately 44mΩ so the parallel combination of four results in an equivalent ESR of 11mΩ. PRR Q 2 = 12 • QRR • VIN(hi ) • FS = 0. 26 W 100ns before the turn ON of Q2, and 100ns after the turn OFF of Q2, current flows through Q2’s intrinsic body diode. The power dissipation during this interval is: PCOM Q 2DIODE = IOUT • VDIODE • To calculate the losses in the upper MOSFET, Q1, first calculate the RMS current it will be conducting. ∆ IOUT 2 δ IOUT 2 + 12 (8) ) 2 • RdsON =1.5W (14) ∆ IOUT 2 200 ns = 8 .7 A • IOUT 2 + 1 − δ min − 3 .33 µs 12 PCONQ 2 = I (Q 2RMS 2 ) • Rds ON = 1.06 W (15) The worst case loss in Q2 comes to about 2.4 watts. (9) 6) Repeating the preceding procedure for various input and output voltage combinations yields a table of operating conditions. Next, the gate drive losses are found. PGATE Q1 = QG • VIN(hi ) • FS = 0.0 8 W 200 ns = 12 • 1 .4 • 0 .0 6 = 1W 3 .33 µs I(Q 2RMS ) = With the highest programmable output voltage of 3.5 volts and the lowest possible input voltage of 4.5V, the RMS current Q1 will conduct is 10.5 amps, and the conduction loss is ( (13) During the ON period of Q2, current flows through the RdsON of the device. Where the highest RMS current in Q1 was at the low-input-and-high-output condition, the highest RMS current in Q2 is found when the input is at its highest, and the output is at its lowest. The equation for the RMS current in Q2 is: Notice that with a higher output voltage, the duty cycle increases, and therefore so does the RMS current. Any heat sink design should take into account the worst case power dissipation the device will experience. PCON Q1 = IQ1RMS (12) Where QRR, the reverse recovery of the body diode, is 310nC. 5) Q1 and Q2 are chosen to be IRF3103 N-Channel MOSFETs. Each MOSFET has an RdsON of approximately 0.014Ω, a gate charge requirement of 50nC, and a turn OFF time of approximately 54ns. I (Q1RMS ) = (11) (10) 7 UCC3588 APPLICATION INFORMATION (cont.) Table 1. Regulator Operating Conditions VOUT=3.5 Pd Q1 Pd Q2 Pd L Pd Total Average Input Duty Cycle VOUT=1.8 Pd Q1 Pd Q2 Pd L Pd Total Average Input Duty Cycle VIN = 4.5V VIN = 5.5V 20 4.5 VIN= 5.0 5.5 2.2 1.5 0.95 5.1 10.50 0.84 2.1 1.6 0.95 5.2 9.5 0.76 2 1.8 0.95 5.4 8.70 0.69 10 GAIN (dB) 0 -10 -20 -30 -40 -50 -60 1.4 2.5 0.95 5.4 4.96 0.38 1.4 2.4 0.95 5.3 5.40 0.42 1.5 2.3 0.95 5.2 6.00 0.46 0.1 1 10 100 1000 10 100 FREQUENCY (kHz) 1000 FREQUENCY (kHz) 180 7) Assuming the converter’s input current is DC, the remaining switching current drawn by Q1 must come from the input capacitors. The next step then, is to find the worst case RMS current the capacitors will experience. (Equation 16). Where IIN(avg) is the average input current. PHASE (°) 90 0 -90 Repeating the above calculation over the operating range of the regulator (see Table 2.) reveals that the worst case capacitor ripple current is found at low input, and at low output voltage. A Sanyo MV-GX, 1500µF, 6.3V capacitor is rated to handle 1.25 amps at 105°C. Derating the de- -180 0.1 1 Figure 1. Modulator Frequency Response Table 2. Regulator Operating Conditions VOUT= 3.5 Total Input Cap RMS Current Total Input Cap Power Dissipation Total Power Dissipation Power Train Efficiency VOUT=1.8 Total Input Cap RMS Current Total Input Cap Power Dissipation Total Power Dissipation Power Train Efficiency ICAPRMS = δ IOUT − IIN avg ( K PWM (f ) = VIN VRAMP = ) 2 + sign to 70°C allows the use of four capacitors, each one experiencing one fourth of the total ripple current. 4.5 VIN= 5.0 5.5 4.4 0.21 5.1 0.89 5.2 0.29 5.3 0.88 5.6 0.34 5.4 0.87 6 0.39 5.2 0.81 5.9 0.39 5.3 0.8 5.8 0.37 5.4 0.8 8) The voltage feedback loop is next. The gain and frequency response of the PWM and LC filter is shown in Equation 17. To compensate the loop with as high a bandwidth as practical, additional gain is added to the loop with the voltage error amplifier. ∆ IOUT 2 + (1 − δ) • IIN avg 12 ( ) 2 1 + 2πf • RESR • COUT ( 1 − 4π 2 • f 2 • LCOUT ) L + (R 6 + R + RESR ) • COUT + RLOAD 8 (16) (17) UCC3588 APPLICATION INFORMATION (cont.) C SS = 10 µ • C2 R2 t SS 3 .7 V (20) Where tSS is the desired soft start time. C3 C1 RF To insure that soft start is long enough so that the converter does not enter current limit during startup, the minimum value of soft start may be determined by: RI VIN – VREF VOUT + C SS ≥ Figure 3. Voltage error amplifier configuration. (1+ s (C1Rf )) • (1+ s (C3 ( RI + R 2))) RI (s 2C1C 2 Rf + s (C1 + C 2)) • (1 + s (C 3 R 2)) (18) For good transient response, select the RF-C1 zero at 5kHz. Add additional phase margin by placing the RI-C3 zero also at 5kHz. To roll off the gain at high frequency, selece the R2-C3 pole to be at 10kHz, and the final C2RF pole at 40kHz. Results are RI=20k, RF=200k, R2=15k, C1=220pF, C2=20pF, C3=1000pF. The GainPhase plots of the voltage error amplifier and the overall loop are plotted below. VIN (21) VRAMP 11) The output of the regulator is adjustable by programming the following codes into the D0 - D4 pins according to the table below. To program a logic zero, ground the pin. To program a logic 1, then leave the pin floating. Do not tie the pin to an external voltage source. 12) A series resistor should be placed in series with the gate of each MOSFET to prevent excessive ringing due to parasitic effects. A value of 3Ω to 5Ω is usually sufficient in most cases. Additionally, to prevent pins 13 and 14 from ringing more than 0.5V below ground, a clamp schottky rectifier placed as close as possible to the IC is also recommended. 9) The value of RT is given by: 1 − 800 = 48 k Ω RT = 67 . 2 F • pF S VLIM − IOUT R SENSE • Where COUT is the output capacitance, Ich is the soft start charging current (10µA typ), VLIM is the current limit trip voltage (54mV typ), IOUT is the load current, VIN is the 5V supply, and VRAMP is the internal oscillator ramp voltage (1.85V typ). For this example, CSS must be greater than 35nF, and the resulting soft start time will be 13ms. The equation for the gain of the voltage amplifier in this configuration is: K EA = COUT • ICH (19) 10) The value of the soft start capacitor is given by: Error Amp VIN = 4.5V Error Amp VIN = 5.5V VIN = 4.5V VIN = 5.5V 180 60 160 140 PHASE (deg) GAIN (dB) 40 20 0 120 100 80 60 40 -20 20 -40 0 0.1 1 10 100 FREQUENCY (kHz) 1000 0.1 Figure 4. Error amplifier and loop frequency response. 1 10 100 FREQUENCY (kHz) Figure 5. Error amplifier and loop frequency response. 9 1000 UCC3588 APPLICATION INFORMATION (cont.) Table 3. VID Codes and Resulting Regulator Output Voltage D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 D2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 D1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VOUT 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95 2 2.05 No outputs 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. 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