STMICROELECTRONICS QST104

QST104
Capacitive touch sensor device
4 keys with individual key state outputs or I2C interface
Features
■
Patented charge-transfer design
■
Up to 4 independent QTouch™ keys supported
■
Individual key state outputs or I2C interface
■
Fully “debounced” results
■
Patented AKS™ Adjacent Key Suppression
■
Self-calibration and auto drift compensation
■
Spread-spectrum bursts to reduce EMI
■
Up to 13 general-purpose outputs
■
ECOPACK® (RoHS compliant) package
Applications
This device specifically targets human interfaces
and front panels for a wide range of applications
such as PC peripherals, home entertainment
systems, gaming devices, lighting and appliance
controls, remote controls, etc.
QST devices are designed to replace mechanical
switching/control devices and the reduced
number of moving parts in the end product
provides the following advantages:
■
Lower customer service costs
■
Reduced manufacturing costs
■
Increased product lifetime
LQFP32 (7x7 mm)
Description
The QST104 is the ideal solution for the design of
capacitive touch sensing user interfaces.
Touch-sensitive controls are increasingly
replacing electromechanical switches in home
appliances, consumer and mobile electronics,
and in computers and peripherals. Capacitive
touch controls allow designers to create stylish,
functional, and economical designs which are
highly valued by consumers, often at lower cost
than the electromechanical solutions they
replace.
The QST104 QTouch™ sensor IC is a pure digital
solution based on Quantum's patented chargetransfer (QProx™) capacitive technology.
QTouch™ and QProx™ are trademarks of the
Quantum Research Group.
Table 1.
Device summary
Order code
Feature
QST104KT6
Operating supply voltage 2.4 to 5.5 V
February 2008
Supported interfaces
Individual key state outputs
or I2C Interface
Operating temperature
-40° to +85° C
Package
LQFP32 (7x7 mm)
Rev 2
1/45
www.st.com
1
Contents
QST104
Contents
1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
QST touch sensing technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
3.1
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2
Spread-spectrum operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3
Faulty and unused keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4
Detection threshold levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.5
Detection integrator filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.6
Self-calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.7
Fast positive recalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.8
Forced key recalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.9
Max On-Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.10
Drift compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.11
Adjacent key suppression (AKS™) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
Reset and power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2
Burst operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3
Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4
Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5
Stand-alone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5.1
4.5.2
4.5.3
4.6
I2C mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.7
2/45
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
KOUT outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Option descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
General-purpose outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
IRQ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Communication packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
I2C address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Supported commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
QST104
5
Contents
Design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1
CS sense capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2
Sensitivity tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2.1
5.2.2
5.2.3
6
Increasing sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Decreasing sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Key balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.5
Crosstalk precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.6
PCB layout and construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.5
Capacitive sensing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.6
KOUTn/OPTn/GPOn pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.6.1
6.6.2
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Output pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.7
RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.8
I2C control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9
Device revision information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1
Device revision identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.2
Device revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.2.1
10
Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3/45
Device overview
1
QST104
Device overview
The QST104 capacitive touch sensor IC is a pure digital solution based on Quantum's
patented charge-transfer (QProx™) capacitive technology.
This technology allows users to create simple touch panel sensing electrode interfaces for
conventional or flexible printed circuit boards (PCB/FPCB). Sensing electrodes are part of
the PCB layout (copper pattern or printed conductive ink) and may be used in various
shapes (circle, rectangular, etc.).
By implementing the QProx™ charge-transfer algorithm, the QST104 detects finger
presence (human touch) near electrodes behind a dielectric (glass, plastic, wood, etc.). Only
one external sampling capacitor by channel is used in the measuring circuitry to control the
detection.
QST technology also incorporates advanced processing techniques such as drift
compensation, auto-calibration, noise filtering, and Quantum's patented Adjacent Key
Suppression™ (AKS™) to ensure maximum usability and control integrity.
In order to meet environmental requirements, ST offers this device in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
4/45
QST104
2
Pin description
Pin description
32-pin package pinout
GPO3/OPT3/KOUT3 (HS)
GPO2/OPT2/KOUT2 (HS)
GPO1/OPT1/KOUT1 (HS)
GPO13
GPO12
GPO11
GPO10
GPO9
Figure 1.
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
21
QST104KT6
20
19
18
17
9 10 11 12 13 14 15 16
GPO8
GPO7
GPO6
SNSK_SCK4
SNS_SCK4
SNSK_SCK3
SNS_SCK3
SNSK_SCK2
VSS_1
VSS_2
VSS_3
VSS_4
VDD_2
SNS_SCK1
SNSK_SCK1
SNS_SCK2
GPO4/KOUT4/OPT4 (HS)
GPO5/OPT5 (HS)
IRQ/OPT6 (HS)
I2C_SDA1) (HS)
I2C_SCL1) (HS)
RESET
NC
VDD_1
(HS) 20 mA high sink capability (on N-buffer only)
1. An external pull-up is required on these pins.
Table 2.
Device pin description
Pin
Pin name
Type (1)
1
GPO4/OPT4/KOUT4 (2)
PP (HS)
2
GPO5/OPT5 (2)
PP (HS) MOD_1 option resistor
Open or
General-purpose output 5 option
resistor
3
OPT6/IRQ (2)
PP/OD
(HS)
Interrupt line (active low)
Open or
option
resistor
4
I2C_SDA(3)
TOD
(HS)
I2C serial data
Open
5
I2C_SCL(3)
TOD
(HS)
I2C serial clock
Open
Stand-alone mode function
Key 4 output / BCD output 4
and MOD_0 option resistor
OM_0 option resistor
I2C mode function
If unused
General-purpose output 4
Option
and I²C address bit 2
resistor
option resistor
5/45
Pin description
Table 2.
Pin
QST104
Device pin description (continued)
Pin name
Type (1)
BD
Stand-alone mode function
I2C mode function
If unused
10nF
capacitor to
ground
6
RESET
Reset (active low)
7
NC
8
VDD_1
S
Supply voltage
9
VSS_1
S
Ground voltage
10
VSS_2
S
Ground voltage
11
VSS_3
S
Ground voltage
12
VSS_4
S
Ground voltage
13
VDD_2
S
Supply voltage
14
SNS_SCK1
SNS
Key 1 sense pin to Cs
Open
15
SNSK_SCK1
SNS
Key 1 sense pin to Cs/Rs
Open
16
SNS_SCK2
SNS
Key 2 sense pin to Cs
Open
17
SNSK_SCK2
SNS
Key 2 sense pin to Cs/Rs
Open
18
SNS_SCK3
SNS
Key 3 sense pin to Cs
Open
19
SNSK_SCK3
SNS
Key 3 sense pin to Cs/Rs
Open
20
SNS_SCK4
SNS
Key 4 sense pin to Cs
Open
21
SNSK_SCK4
SNS
Key 4 sense pin to Cs/Rs
Open
22
GPO6
PP
General-purpose output 6
Open
23
GPO7
PP
General-purpose output 7
Open
24
GPO8
PP
General-purpose output 8
Open
25
GPO9
PP
General-purpose output 9
Open
26
GPO10
PP
General-purpose output 10
Open
27
GPO11
PP
General-purpose output 11
Open
28
GPO12
PP
General-purpose output 12
Open
29
GPO13
PP
General-purpose output 13
Open
30
GPO1/OPT1/KOUT1 (2)
PP (HS)
Key 1 output / BCD output 1
and MODE option resistor
General-purpose output 1 Option
and MODE option resistor resistor
31
GPO2/OPT2/KOUT2 (2)
PP (HS)
Key 2 output / BCD output 2
and AKS option resistor
General-purpose output 2
Option
and I2C address bit 0
resistor
option resistor
32
GPO3/OPT3/KOUT3 (2)
PP (HS)
Key 3 output / BCD output 3
and LP option resistor
General-purpose output 3
Option
and I2C address bit 1
resistor
option resistor
Not connected
1. S: supply pin, BD: bidirectional pin, SNS: capacitive sensing pin, PP: Output push-pull, OD: Output open-drain,
TOD: Output true open-drain and HS: 20mA high sink (on N-buffer only)
2. During the reset phase, these pins are floating and the state depends on the option resistor.
3. An external pull-up is required on these pins.
6/45
QST104
QST touch sensing technology
3
QST touch sensing technology
3.1
Functional description
QST devices employ bursts of charge-transfer cycles to acquire signals. Burst mode permits
low power operation, dramatically reduces RF emissions, lowers susceptibility to RF fields,
and yet permits excellent speed. Signals are processed using algorithms pioneered by
Quantum which are specifically designed to provide reliable, trouble-free operation over the
life of the product.
The QST switches and charge measurement hardware functions are all internal to the
device. An external CS capacitor accumulates the charge from sense-plate CX, which is
then measured. Larger values of CX cause the charge transferred into CS to rise more
rapidly, reducing available resolution. As a minimum resolution is required for proper
operation, this can result in dramatically reduced gain. Larger values of CS reduce the rise
of differential voltage across it, increasing available resolution by permitting longer QST
bursts. The value of CS can thus be increased to allow larger values of CX to be tolerated.
The device is responsive to both CX and CS, and changes in either can result in substantial
changes in sensor gain.
Figure 2.
QTouch™ measuring circuitry
CT (~5 pF)
Earth
SNSK_SCKn
SNS_SCKn
Sense capacitor
CS (a few nF)
Cx (~20 pF)
Ai12569
3.2
Spread-spectrum operation
The bursts operate over a spread of frequencies, so that external fields will have minimal
effect on key operation and emissions are very weak. Spread-spectrum operation works
with the Detection Integrator mechanism (DI) to dramatically reduce the probability of false
detection due to noise.
7/45
QST touch sensing technology
3.3
QST104
Faulty and unused keys
Any sensing channel that does not have its sense capacitor (CS) fitted is assumed to be
either faulty or unused. This channel takes no further part in operation unless a Mastercommanded recalibration operation shows it to have an in-range burst count again. Faulty,
unused or disabled keys are still bursted but not processed to avoid modifying the sensitivity
of active keys.
This is important for sensing channels that have an open or short circuit fault across CS.
Such channels would otherwise cause very long acquire bursts, and in consequence would
slow the operation of the entire QST device.
To optimize touch response time and device power consumption, if some keys are not used,
we recommend to try suppressing the ones which belong to the same burst. Bursts which
do not have any keys implemented will then not be processed.
3.4
Detection threshold levels
The key capacitance change induced by the presence of a finger is sensed by the variation
in the number of charge transfer pulses to load the capacitor. The difference in the pulse
count number is compared to a threshold in order to detect the key as pressed or not.
Two different thresholds, one for detection and one for the end of detection, create an
hysteresis in order to prevent erratic behavior.
The default threshold levels and hysteresis values are described inSection 6.5: Capacitive
sensing characteristics on page 33.
3.5
Detection integrator filter
Detect Integrator (DI) filter mechanism works together with spread spectrum operation to
dramatically reduce the effects of noise on key states. The DI mechanism requires a
specified number of measurements that qualify as detections (and these must occur in a
row) or the detection will not be reported.
In a similar manner, the end of a touch (loss of signal) also has to be confirmed over several
measurements. This process acts as a type of “debounce” mechanism against noise.
The default DI value for confirming start of touch and end of touch is described in
Section 6.5: Capacitive sensing characteristics on page 33.
3.6
Self-calibration
On power-up, all keys are self-calibrated to provide reliable operation under almost any
conditions. The calibration phase is used to compute a reference value per key which is then
used by the process determining if a key is touched or not. The reference is an average of 8
single acquisitions. As a result, the calibration time of the system can be simply calculated
using the following formula: tCAL = 8 * Burst_Period. The methodology used to measure the
burst period is described in application note AN2547. For a maximum calibration duration
(tCAL), please refer to Section 6.5: Capacitive sensing characteristics on page 33.
8/45
QST104
3.7
QST touch sensing technology
Fast positive recalibration
The device autorecalibrates a key when its signal reflects a decrease in capacitance higher
than a fixed threshold (PosRecalTh) for a defined number of acquisitions (PoseRecalI).
3.8
Forced key recalibration
A recalibration of the device may be issued at any time by sending to the QST device the
appropriate I2C command or by tying the RESET pin to ground.
It is possible to recalibrate independently any individual key using an I2C command.
3.9
Max On-Duration
The device can time out and automatically recalibrate each key independently after a fixed
duration of continuous touch detection. This prevents the keys from becoming ‘stuck on’ due
to foreign objects or other sudden influences. This is known as the Max On-Duration feature.
After recalibration, the key will continue to operate normally, even if partially or fully
obstructed. Max On-Duration works independently per channel: a timeout on one channel
has no effect on another channel.
Infinite timeout is useful in applications where a prolonged detection can occur and where
the output must reflect the detection no matter how long. In infinite timeout mode, the
designer should take care to ensure that drift in CS, CX, and VDD do not cause the device to
remain “stuck on” inadvertently even when the touching object is removed from the sense
field. Timeout durations are not accurate and can vary substantially depending on VDD and
temperature values, and should not be relied upon for critical functions.
3.10
Drift compensation
Signal drift can occur because of changes in CX, CS, and VDD over time. Depending on the
CS type and quality, the signal may vary substantially with temperature and veiling. If keys
are subject to extremes of temperature or humidity, the signal can also drift. It is crucial that
drift be compensated, otherwise false detections, non detections, and sensitivity shifts will
follow.
Drift compensation slowly corrects the reference level of each key while no detection is in
effect. The rate of reference adjustment must be performed slowly or else legitimate
detections can also be ignored. The device compensates drift on each channel
independently using a maximum compensation rate to the reference level.
Once a touch is sensed, the drift compensation mechanism ceases since the signal is
legitimately high, and therefore should not cause the reference level to change.
The signal drift compensation is “asymmetric”: the reference level compensates drift in one
direction faster than it does in the other. Specifically, it compensates faster for increasing
signals than for decreasing signals. Decreasing signals should not be compensated for
quickly, since an approaching finger could be compensated for partially or entirely while
approaching the sense electrode. However, an obstruction over the sense pad, for which the
sensor has already made full allowance, could suddenly be removed leaving the sensor with
an artificially elevated reference level and thus become insensitive to touch. In this latter
case, the sensor will compensate for the object's removal very quickly, usually in only a few
seconds.
9/45
QST touch sensing technology
QST104
Caution:
When only one key is enabled or if keys are very close together, the common drift
compensation must be disabled or its rate must be reduced to ensure correct device
operation.
3.11
Adjacent key suppression (AKS™)
Adjacent key suppression (AKS™) is a Quantum-patented feature which prevents multiple
keys from responding to a single touch. This can happen with closely spaced keys, or a
scroll wheel that has buttons very near it.
The QST104 supports two AKS modes:
●
Locking AKS
Once a key is considered as “touched”, all other keys are locked in an untouched state.
To unlock these keys, the touched key must return to an untouched state. Then, the key
having the lowest key ID number is declared as the “touched” one.
●
Unlocking AKS
On each acquisition, the signal strengths from each key are compared and the key with
the highest signal level is declared as the “touched” one.
In I2C mode, up to 8 AKS groups can be specified.
Note:
10/45
All keys belonging to the same AKS group must have the same AKS mode.
QST104
Device operating modes
4
Device operating modes
4.1
Reset and power-up
At power-up, the device configures itself according to the pull-up or pull-down option
resistors present on pins OPT1 to OPT6. The device start-up and configuration may take up
to tSetup.
When the power is established, it is possible to force a new device configuration by applying
a negative pulse on the RESET pin.
The RESET pin is a bidirectional pin with an internal pull-up. The line is forced low when the
device resets itself (through an I²C command, for example).
A 10nF capacitor is recommended on the RESET pin to ensure reliable start-up and noise
immunity.
4.2
Burst operation
The device operates in “Burst” mode. Each key touch is acquired using a burst of chargetransfer sensing pulses whose count varies depending on the value of the sense capacitor
CS and the load capacitance CX.
In Low Power mode, the device sleeps in an ultra-low current state between bursts to
conserve power.
4.3
Low power mode
In order to reduce the device power consumption, the QST family include scalable low
power modes.
●
Standard low power mode
When the device is in standard low power mode, a window with very low power
consumption is inserted between the acquisition of the last active key and the following
acquisition of the first active key.
This window duration is programmable as the 'sleep duration time'.
Note that the sleep window insertion is cancelled in the following conditions:
●
–
If a change is detected on a key, in order to speed up the DI process, the sleep
window insertion is skipped until the end of the DI process.
–
In I2C mode, when a key change is actually detected and reported with a negative
pulse on the IRQ pin. In this case, the low power mode is disabled until a
command is received from the host.
–
Inside an I2C command, between the Write and the Read I2C frames, the sleep
period is skipped.
Free run in detect
The behavior in this mode is the same as in the standard low power mode except that
the sleep window insertion is always skipped if any of the active keys is detected as
touched.
This is useful to improve the wheel response time.
11/45
Device operating modes
●
QST104
Deep Sleep mode
In Deep Sleep mode, the device enters a very low power mode indefinitely. The device
resumes its operations after receiving an I2C frame with any address or a reset.
Caution:
If an I2C frame is received while in Sleep or Deep Sleep mode, the device wakes up but
does not acknowledge the frame (even if it has an I2C frame with the device address). The
host must therefore send again the frame until it is taken in account and acknowledged.
4.4
Mode selection
The device options are configured by connecting pull-up or pull-down resistors on OPTn
pins. The device operating mode is selected using option pin 1 (OPT1) while the device
settings are configured using option pins OPT2 to OPT6 (Table 3). Option pins are sampled
at power-up and after a reset.
To fit most applications, the QST104 device offers two different operating modes:
●
Stand-alone mode
This mode allows the user to simply replace existing mechanical switches with a
capacitive sensing solution. It is designed for maximum flexibility and can
accommodate most popular sensing requirements via option resistors (AKS, Low
power, Max On-Duration and output modes).
In this mode, the 4 output pins reflect the status of the 4 sensing channels.
●
I2C mode
In this mode, which is the most open one, the device is driven using the I2C interface.
To avoid polling, the QST device features an output interrupt pin (IRQ). The IRQ line
reports all key changes to the Master device. The QST (Slave) device can drive up to
13 general-purpose outputs.
Table 3.
Operating modes
Option resistor function
OPT1: Mode selection
Pin OPT1 is high at start-up Stand-alone mode
Pin OPT1 is low at start-up
4.5
I2C mode
OPT2
OPT3
AKS
LP
ADD0
ADD1
OPT4
OPT5
MOD_0 MOD_1
ADD2
OPT6
OM
Unused Unused
Stand-alone mode
This mode allows the user to simply replace existing mechanical switch interface with a
capacitive sensing solution. It is designed for maximum flexibility and can accommodate
most popular sensing requirements via option resistors (see Figure 3).
4.5.1
12/45
Main features
●
Pins KOUT1 to KOUT4 directly reflect the state of keys
●
Selectable global adjacent key suppression (AKS™)
●
Selectable sleep duration
●
Selectable Max On-Duration values
●
Selectable BCD mode
QST104
Device operating modes
Figure 3.
Stand-alone mode typical schematic
VDD
VUNREG
2.4~5.5V
Volt. Reg.
4.7µF
4.7µF
100nF
100nF
8
VDD_1
Keep these parts close to IC
RS4
21
Key4
10kΩ
CS4
RS3
19
Key3
10kΩ
CS3
18
VDD_2
RESET
17
Key2
10kΩ
CS2
RS1
16
15
10kΩ
CS1
14
6
SNSK_SCK4
To Host
10nF
SNS_SCK4
OM
SNSK_SCK3
SNS_SCK3
MOD_1
RS2
Key1
20
13
3
MOD_0/KOUT4
VDD
VSS
1MΩ
VDD
VSS
2
SNSK_SCK2
SNS_SCK2
1MΩ
1
1MΩ
SNSK_SCK1
LP/KOUT3
32
AKS/KOUT2
31
MODE/KOUT1
30
SNS_SCK1
1MΩ
1MΩ
1MΩ
VSS_1
9
VSS_2
VSS_3
VSS_4
10
11
12
KOUT4
VDD
VSS
KOUT3
VDD
VSS
Binary-
KOUT2 coded
Output
VDD
Mode
VSS
KOUT1
VDD
Ai12572
4.5.2
KOUT outputs
KOUTn outputs directly reflect the state of keys. These pins are push-pull outputs. Under
RESET, these pins are floating and their state depends on the option resistors. Pins KOUTn
are active high meaning that when a key is “touched”, the corresponding KOUT pin outputs
a ‘1’.
13/45
Device operating modes
4.5.3
QST104
Option descriptions
Adjacent key suppression (AKS™)
The QST104 features an adjacent key suppression (AKS™) function.
This function is enabled using the AKS option resistor (OPT2) in standard output mode as
described in Table 4. In BCD output mode, the AKS function is always enabled, regardless
of the option resistor configuration.
Table 4.
AKS truth table
OPT2/AKS
Description
VSS
Disabled
VDD
Global locking AKS on all available keys
Low Power mode option
This option resistor (OPT3) selects whether the device is always sensing the keys or if a low
power consumption phase is introduced between bursts as described in Table 5.
In Low Power mode, a very low consumption (sleep) phase of 100ms is inserted between
two consecutive bursts. This significantly reduces the overall consumption of the device.
Sleep duration is not accurate and can vary substantially depending on VDD and
temperature values.
Note:
In Low Power mode, the response time is increased.
Table 5.
Low power (LP) mode truth table
OPT3/LP
Description
VSS
Free running mode
VDD
100ms sleep duration
Max On-Duration
There are four recalibration timing options (“Max On-Duration”). The recalibration option
resistors (OPT4 and OPT5) control how long it takes for a continuous detection to trigger a
recalibration on a key as described in Table 6. When such an event occurs, only the “stuck”
key is recalibrated.
Table 6.
Max On-Duration (MOD) truth table
OPT4/MOD_0 OPT5/MOD_1
14/45
Description
VSS
VSS
Infinite
VSS
VDD
60s
VDD
VSS
20s
VDD
VDD
10s
QST104
Device operating modes
Output mode option
The QST104 offers several outputs mode to fit any existing application.
Table 7.
Output mode (OM) truth table
OPT6/OM
Description
VSS
Individual key state output mode: One output per sensing channel
VDD
BCD output mode: Binary-coded touched key number (see Table 8)(1)
1. In BCD mode, the AKS function is always active.
Table 8.
Binary code truth table
KOUT4 KOUT3 KOUT2 KOUT1
Description
0
0
0
0
All released
0
0
0
1
Key 1 pressed
0
0
1
0
Key 2 pressed
0
0
1
1
Key 3 pressed
0
1
0
0
Key 4 pressed
Other
Not used
15/45
Device operating modes
4.6
I2C mode
The I2C mode offers the largest configurability and functionality of the QST104.
4.6.1
16/45
Main features
●
13 general-purpose outputs
●
Configuration of up to 8 AKS groups
●
Additional low power modes
●
Accessible internal capacitive sensing parameters
●
Continuous range of Max On-Duration
QST104
QST104
Device operating modes
Figure 4.
I2C mode typical schematic
VDD
2.4~5.5V
Volt. Reg.
VUNREG
VDD
100nF
100nF
13
VDD_2
Keep these parts close to IC
RS4
21
Key4
10kΩ
CS4
RS3
19
Key3
10kΩ
CS3
RS2
CS2
RS1
16
15
Key1
10kΩ
18
17
Key2
10kΩ
20
CS1
14
10kΩ
8
VDD_1
I2C_SCL
I2C_SDA
IRQ
SNSK_SCK4
SNS_SCK4
RESET
5
To
Host
MCU
4
3
6
To Host
10nF
SNSK_SCK3
SNS_SCK3
GPO13
SNSK_SCK2
GPO12
SNS_SCK2
GPO11
SNSK_SCK1
SNS_SCK1
GPO10
GPO9
GPO8
GPO7
GPO6
GPO5
ADD2/GPO4
29
GPO13
28
GPO12
27
GPO11
26
GPO10
25
GPO9
24
GPO8
23
GPO7
22
GPO6
2
GPO5
1
1MΩ
ADD1/GPO3
32
1MΩ
ADD0/GPO2
31
1MΩ
MODE/GPO1
VSS_1
9
VSS_2
10
2.7kΩ
4.7µF
2.7kΩ
4.7µF
VSS_3
11
VSS_4
30
1MΩ
GPO4
VDD
VSS
GPO3
VDD
VSS
GPO2
VDD
VSS
GPO1
VSS
12
Ai12573
4.6.2
General-purpose outputs
I2C mode allows to drive up to 13 general-purpose outputs. These output pins are
configured in output push pull mode 0 by default. Their state can be changed using the
SET_GPIO_STATE I2C command.
17/45
Device operating modes
Figure 5.
QST104
Optional LED schematic
VUNREG
R
GPOn
C (10 nF)
Ai12570
4.6.3
IRQ pin
The IRQ pin is an open drain output with an internal pull-up. It can be used to inform the
Master device about any change in the key status. The IRQ line is pulled low every time the
state of any of the enabled keys changes. This includes any change in the touch state of the
key, a faulty key or a new calibration of one or more keys. The reported changes may then
be accessed by the Master device by using the GET_KEY_STATE command.
To improve communication response time, this signal suspends Low Power mode until the
Master device has issued a communication with the QST device.
4.6.4
Communication packet
The communication between the Master device and the QST104 (Slave) consists of two
standard I2C frames.
The first frame is sent by the Master device using the QST104 device address with the write
bit set. The data bytes consist of the command byte which is eventually followed by the
parameters and a checksum byte.
The second one is sent by the Master device using the QST104 device address with the
write bit reset. The QST104 completes the frame with data according to the command
previously sent by the Master device. The device finishes the frame by sending a checksum
byte for communication integrity verification.
If the read frame is omitted, the command may not be taken into account.
To initiate the communicate with the QST104, the Master device must send the
GET_DEVICE_INFO command in order to unlock access to all the other commands.
18/45
QST104
4.6.5
Device operating modes
I2C address selection
The QST104 slave address is programmable using the option resistors mapped on pins
OPT2 to OPT4 (see Table 9).
Table 9.
I²C address versus option resistor
I2C Address
Option configuration
4.7
OPT4
OPT3
OPT2
VSS
VSS
VSS
ADD[6:3]
ADD2
ADD1
ADD0
Hex value
VSS
0
0
0
0x28
VSS
VDD
0
0
1
0x29
VSS
VDD
VSS
0
1
0
0x2A
VSS
VDD
VDD
0
1
1
0x2B
VDD
VSS
VSS
1
0
0
0x2C
VDD
VSS
VDD
1
0
1
0x2D
VDD
VDD
VSS
1
1
0
0x2E
VDD
VDD
VDD
1
1
1
0x2F
0101
Supported commands
Table 10 lists the supported I²C commands and available arguments.
Note:
For more information on the supported commands and I2C protocol, please refer to the QST
standard communication protocol reference manual.
Table 10.
Supported commands
I2C commands
Description
CALIBRATE_KEY (All keys)
Write
0x98
Read
ErrCode
Forces the recalibration of all keys.
ErrCode: Standard Error code (see Table 11)
CALIBRATE_KEY (Single key)
Write
0x9B KeyID Checksum
Read
ErrCode
Forces the recalibration of a single key.
KeyId: Binary-coded key number (see Table 14)
ErrCode: Standard Error code (see Table 11)
GET_DEBUG_INFO
Write
0xF7 KeyID Checksum
Read
0x0B KeyDbgState
RefMSB RefLSB
BCMSB BCLSB
Checksum
Returns the debug info of the single KeyID channel.
KeyDbgState: Current Key Debug state (see Table 19)
RefMSB: Reference Count MSB
RefLSB: Reference Count LSB
BCMSB: Burst Count MSB
BCLSB: Burst Count LSB
19/45
Device operating modes
Table 10.
QST104
Supported commands (continued)
I2C commands
Description
GET_DEVICE_INFO
Write
Read
0x85
Returns the QST104 device version and ASCII-coded device
name. This command must be sent first to enable the
communication flow.
0x15 MainVers SubVers
MainVers: Device main version
NbSCkey NbMCkey
SubVer: Device sub-version
‘Q’ ’S’ ‘T’ ‘1’ ‘0’ ‘4’
NbSCkey: 0x04 single-channel keys
Checksum
NbMCkey: 0x00 multi-channel keys
Q S T 1 0 4: ASCII-coded device name
GET_KEY_ERROR
Write
0xC4
Read
0x11 KeyError1
KeyError2 ... KeyError4
CheckSum
Returns the error information on each key.
KeyErrorN: KeyError byte description (see Table 12)
GET_KEY_STATE
Write
0xC1
Read
0x03 AllKeyState
KeyError Checksum
Returns the state of all keys.
AllKeyState: Touched/untouched state for all 4 keys. Refer to
Table 13: AllKeyState.
KeyError: Refer to Table 12: KeyError byte description
GET_PROTOCOL_VERSION
Write
0x80
Read
0x07 MainVers SubVer
I2CSpeed Checksum
Returns the QST104 protocol version.
MainVers: Protocol main version
SubVer: Protocol sub-version
I2CSpeed: 0x00 (100 kHz maximum)
RESET_DEVICE
Write
0xFD
Read
ErrCode
Restarts the device (options Read and Calibration) after
reading the ErrCode (see Table 11).
SET_DETECT_INTEGRATORS
Write
0x03 0x04 0x00 DI EDI
PosRecaII CheckSum
Read
ErrCode
Sets the detection, End Of Detection and Positive Recalibration
Integrators for all keys.
DI: Detection Integrator 1) 3)
EDI: End of Detection Integrator 1) 3)
PosRecaII: Positive Recalibration Integrator 1) 3)
ErrCode: Standard Error code (see Table 11)
SET_GPIO_STATE
20/45
Write
0x08 0x02 GPOState1
GPOState2 Checksum
Read
ErrCode
Controls the state of the general-purpose outputs.
GPOStateN: State of general-purpose outputs (see Table 16)
ErrCode: Standard Error code (see Table 11)
QST104
Device operating modes
Table 10.
Supported commands (continued)
I2C commands
Description
SET_KEY_ACTIVATION (see Note 4)
Write
0x97 KeyActivation
Checksum
Read
ErrCode
Enables or disables a single key.
KeyActivation: Byte containing the key number selection and
requested state.
ErrCode: Standard Error code (see Table 11)
SET_KEY_GROUP
Write
0x00 0x09
AKSGrpMode Key1Grp
Key2Grp ...Key8Grp
CheckSum
Read
ErrCode
Defines the AKS groups for each key.
AKSGrpMode: AKS mode selection of each group (see
Table 17)
KeynGrp: AKS group selection for key n (see Table 18)
ErrCode: Standard Error code (see Table 11)
SET_LOW_POWER_MODE
Write
0x92 LowPowerMode
Checksum
Read
ErrCode
Selects standard or Low Power mode.
LowPowerMode: Configure Low Power mode (see Table 15)
ErrCode: Standard Error code (see Table 11)
SET_MAX_ON_DURATION
Write
0x8A MaxOnDuration
Checksum
Read
ErrCode
Sets the maximum detected ON time before triggering an
automatic recalibration.
MaxOnDuration: Time, in second (0 for infinite)
ErrCode: Standard Error code (see Table 11)
SET_SCKEY_PARAMETERS
Note:
Write
0x01 0x04 0x00 DeTh
EofDeTh PosRecalTh
Checksum
Read
ErrCode
Sets the Detection, End Of Detection and Positive
Recalibration Thresholds for a single key.
DeTh: Detection Threshold 1) 2)
EofDeTh: End of Detection Threshold 1) 2)
PosRecalTh: Positive Recalibration Threshold 1) 2)
ErrCode: Standard Error code (see Table 11)
1
See Section 6.5: Capacitive sensing characteristics on page 33 for default values.
2
The value is a signed character (0x80...0x7F <=> -128 ... +128).
3
The value is an unsigned number (0x00..0xFF <=> 0 ... 255).
4
Enabling or disabling keys triggers a new calibration of all enabled keys.
21/45
Device operating modes
QST104
Error codes
Table 11 lists the I2C error codes.
Table 11.
ErrCode
ErrCode
Description
0x01
No Error
0x83
Command not supported
0x85
Parameter not supported
0xA1
Parity Error
0xA3
Checksum Error
0xE0
Initialization process (GET_FIRMWARE_INFO command not received)
KeyError byte description
Table 12.
KeyError byte description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Key State
0
0
0
0
Bit 2
Bit 1
Bit 0
Key error codes
Key state (Bit 7)
When set to ‘1’, the corresponding key is touched. This bit is always cleared for the
GET_KEY_STATE command.
Key error codes (Bits 2:0)
When answering the GET_KEY_STATE command, the key error code corresponds to
the error codes of all the keys ORed toghether. When answering the
GET_KEY_ERROR command, each key error code describes the errors of one defined
key.
Bit 0: When set to ‘1’, calibration in progress
Bit 1: When set to ‘1’, maximum count reached
Bit 2: When set to ‘1’, minimum count not reached
All key state description
Table 13.
AllKeyState
Bit 7
Bit 6
Bit 5
Bit 4
0
0
0
0
Bit 3
Bit 1
Bit 0
Key 4 State Key 3 State Key 2 State Key 1 State
Key n state
When set to ‘1’, the corresponding key is touched.
22/45
Bit 2
QST104
Device operating modes
Key activation description
Table 14.
KeyActivation
Bit 7
Bit 6
Bit 5
Bit 4
Key
Activation
0
0
0
Bit 3
Bit 2
Bit 1
Bit 0
Key ID (binary coded)
Key activation (Bit 7)
0: Key enabled
1: Key disabled
Key identifier (Bits 3:0)
0000: All keys
0001: Key 1
0010: Key 2
0011: Key 3
0100: Key 4
Low power mode description
Table 15.
SetLowPower
Bit 7
Bit 6
0
Free Run
in Detect
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sleep Duration Factor
Free Run in Detect (Bit 6)
0: Low Power mode is always enabled, whatever the state of the keys.
1: Low Power mode is automatically suspended when any key is in Detect state.
Low Power mode is automatically resumed when no key is in Detect state.
Sleep Duration Factor (Bits 5 to 0)
0x00 or 0x20 to 0x3E: Low power mode is disabled.
0x01 to 0x19: Low Power mode. The sleep duration is ‘Sleep Duration Factor’ x 20
milliseconds (20 ms to 500 ms)
0x3F: Deep Sleep mode is entered immediately. Only a reset or an I2C frame with
the correct device address allows exiting Deep Sleep mode.
Note:
1
When the device is in Sleep or Deep Sleep, any I2C bus activity will wake-up the device.
2
The I2C QST device address is not acknowledged but forces the QST device to exit from
Low Power mode. The Master device will have to repeat the command to ensure that it is
taken in account.
23/45
Device operating modes
QST104
GPO state description
Table 16.
GPOState
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GPOState1
GPO 8
state
GPO 7
state
GPO 6
state
GPO 5
state
GPO 4
state
GPO 3
state
GPO 2
state
GPO 1
state
GPOState2
0
0
0
GPO 13
state
GPO 12
state
GPO 11
state
GPO 10
state
GPO 8
state
GPOState
Defines the state of the selected general-purpose output pin. For more information, see
Section 4.6.2: General-purpose outputs on page 17.
0: GPO state is ‘0’
1: GPO state is ‘1’
AKS group mode description
Table 17.
AKSGrpnMode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AKSGrp8
Mode
AKSGrp7
Mode
AKSGrp6
Mode
AKSGrp5
Mode
AKSGrp4
Mode
AKSGrp3
Mode
AKSGrp2
Mode
AKSGrp1
Mode
AKSGrpnMode
Defines the type of AKS for the Group n:
0: Locking AKS
First key pressed within the group locks out all other keys.
1: Unlocking AKS
Most heavily pressed key (highest signal level) is selected over all other
keys in the group.
AKS group selection description
Table 18.
KeynGrp
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Grp8
Grp7
Grp6
Grp5
Grp4
Grp3
Grp2
Grp1
Grpx
The selected key is a member of AKS Group x.
24/45
QST104
Device operating modes
Key debug state description
Table 19.
KeyDbgState
Value
Description
0x01
On-going calibration
0x02
Key released
0x04
Key touched
0x08
Key in error
0x11
Key calibration filter triggered (PosRecalI)
0x14
Key detection filter triggered (DI)
0x24
Key end of detection filter triggered (EDI)
25/45
Design guidelines
5
Design guidelines
5.1
CS sense capacitor
QST104
The CS sense capacitors accumulate the charge from the key electrodes and determine
sensitivity. Higher values of CS make the corresponding sensing channel more sensitive.
The values of CS can differ for each channel, permitting differences in sensitivity from key to
key or to balance unequal sensitivities. Unequal sensitivities can occur due to key size and
placement differences and stray wiring capacitances. More stray capacitance on a sense
trace will desensitize the corresponding key. Increasing the CS for that key will compensate
for the loss of sensitivity.
The CS capacitors can be virtually any plastic film or low- to medium-K ceramic capacitor.
The normal CS range is 1nF to 50nF depending on the sensitivity required: larger values of
CS require better quality to ensure reliable sensing. In certain circumstances the normal CS
range may be exceeded. Acceptable capacitor types for most uses include PPS film,
polypropylene film, and NP0 and X5R / X7R ceramics. Lower grades than X5R or X7R are
not recommended.
5.2
Sensitivity tuning
Sensitivity can be altered to suit various applications and situations on a channel-bychannel basis. The easiest and most direct way to impact sensitivity is to alter the value of
each CS: more CS yields higher sensitivity. Each channel has its own CS value and can
therefore be independently adjusted.
5.2.1
Increasing sensitivity
Sensitivity can also be increased by using larger electrode areas, reducing panel thickness,
or using a panel material with a higher dielectric constant.
5.2.2
Decreasing sensitivity
In some cases the circuit may be too sensitive. Gain can be lowered further by a number of
strategies:
●
●
●
5.2.3
making the electrode smaller
making the electrode into a sparse mesh using a high space-to-conductor ratio
decreasing the CS capacitors
Key balance
A number of factors can cause sensitivity imbalances. Notably, SNS wiring to electrodes can
have differing stray amounts of capacitance to ground. Increasing load capacitance will
cause a decrease in gain. Key size differences, and proximity to other metal surfaces can
also impact gain.
The keys may thus require “balancing” to achieve similar sensitivity levels. This can be best
accomplished by trimming the values of the CS capacitors to achieve equilibrium. The RS
resistors have no effect on sensitivity and should not be altered. Load capacitances to
ground can also be added to overly sensitive channels to reduce their gain.
These should be in the order of a few picofarads.
26/45
QST104
5.3
Design guidelines
Power supply
If the power supply fluctuates slowly with temperature, the QST device compensates
automatically for these changes with only minor changes in sensitivity. However, if the
supply voltage drifts or shifts quickly, the drift compensation mechanism is not able to keep
up, causing sensitivity anomalies or false detections.
The power supply should be locally regulated, using a three-terminal regulator. If the supply
is shared with another electronic system, care should be taken to ensure that the supply is
free of digital spikes, sags and surges which can cause adverse effects. It is not
recommended to include a series inductor in the power supply to the QST device.
For proper operation, a 0.1 µF or greater bypass capacitor must be used between VDD and
VSS. The bypass capacitor should be routed with very short tracks to the device’s VDD and
VSS pins.
The PCB should, if possible, include a copper pour under and around the device, but not
extensively under the SNS lines.
5.4
ESD protection
In normal environmental conditions, only one series resistor is required for ESD
suppression. A 10 kOhm RS resistor in series with the sense trace is sufficient in most
cases. The dielectric panel (glass or plastic) usually provides a high degree of isolation to
prevent ESD discharge from reaching the circuit. RS should be placed close to the chip. If
the CX load is high, RS can prevent total charge and transfer and as a result gain can
deteriorate. If a reduction in RS increases gain noticeably, the lower value should be used.
Conversely, increasing the RS can result in added ESD and EMC benefits, provided that the
increase does not decrease sensitivity.
5.5
Crosstalk precautions
Adjacent sense traces might require intervening ground traces in order to reduce capacitive
cross bleed if high sensitivity is required or high values of delta-CX are anticipated (for
example, from direct human touch to an electrode connection). In normal touch applications
behind plastic panels, this is rarely a problem regardless of how the electrodes are wired.
Higher values of RS will make crosstalk problems worse; try to keep RS to 22 kOhm or less
if possible. In general try to keep the QST device close to the electrodes and reduce the
adjacency of the sense wiring to ground planes and other signal traces; this will reduce the
Cx load, reduce interference effects, and increase signal gain. The one and only valid
reason to run ground near SNS traces is to provide crosstalk isolation between traces, and
then only on an as-needed basis.
5.6
PCB layout and construction
The PCB traces, wiring, and any components associated with or in contact with either SNS
pin will become touch sensitive and should be treated with caution to limit the touch area to
the desired location.
Multiple touch electrodes connected to any sensing channel can be used, for example, to
create control surfaces on both sides of an object.
27/45
Design guidelines
QST104
It is important to limit the amount of stray capacitance on the SNS terminals, for example by
minimizing trace lengths and widths to allow for higher gain without requiring higher values
of CS. Under heavy delta-CX loading of one key, cross coupling to another key’s trace can
cause the other key to trigger. Therefore, electrode traces from adjacent keys should not be
run close to each other over long runs in order to minimize cross-coupling if large values of
delta-CX are expected, for example when an electrode is directly touched. This is not a
problem when the electrodes are working through a plastic panel with normal touch
sensitivity.
For additional information on PCB layout and construction, please contact your local ST
Sales Office for a list of available application notes.
28/45
QST104
Electrical characteristics
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25°C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25°C, VDD = 5 V (for the 4.5V ≤
VDD ≤ 5.5 V voltage range) and VDD = 3.3 V (for the 3.0 V ≤ VDD ≤ 3.6 V voltage range).
They are given only as design guidelines and are not tested.
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 6.
Figure 6.
Pin loading conditions
Output pin
29/45
Electrical characteristics
6.1.5
QST104
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 7.
Figure 7.
Pin input voltage
Input pin
VIN
6.2
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 20.
Thermal characteristics
Symbol
TSTG
TJ
Table 21.
Ratings
Storage temperature range
−65 to +150
Unit
°C
Maximum junction temperature
Voltage characteristics
Symbol
Ratings
VDD − VSS Supply voltage
VIN
Value
Input voltage on any pin
Maximum value
Unit
7.0
(1)(2)
VSS−0.3 to VDD+0.3
VESD(HBM) Electrostatic discharge voltage (Human Body Model)
2000
VESD(CDM) Electrostatic discharge voltage (Charge Device Model)
500
V
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional
internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a
corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up
or pull-down resistor (typical: 4.7kΩ for RESET, 10kΩ for I/Os).
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be
respected.
30/45
QST104
Electrical characteristics
Table 22.
Current characteristics
Symbol
Ratings
Maximum value
IVDD
Total current into VDD power lines (source)(1)
IVSS
(1)
IIO
IINJ(PIN)(2)
(3)
Total current out of VSS ground lines (sink)
75
150
Output current sunk by RESET pin
20
Output current sunk by output pin
40
Output current source by output pin
− 25
Injected current on RESET pin
±5
Injected current output pin
±5
ΣIINJ(PIN)(2) Total injected current (sum of all I/O and control pins)
Unit
mA
± 20
1. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
2. IINJ(PIN) must never be exceeded. This is implicitly ensured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be
respected.
3. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterisation with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
6.3
Operating conditions
Table 23.
Operating conditions
Symbol
VDD
TA
Feature
Operating supply voltage
Operating temperature
Value
Unit
2.4 to 5.5
V
-40° to +85°
C
31/45
Electrical characteristics
6.4
QST104
Supply current characteristics
Table 24.
Symbol
Supply current characteristics
Parameter
Average suppy current
IDD (FR)
Free Run mode
IDD
Average suppy current
(Sleep
100ms Sleep mode
100ms)
IDD
Average suppy current
(Sleep
500ms Sleep mode
500ms)
IDD Halt
Conditions
32/45
Typ. (1)
VDD = 2.4 V
1.71
VDD = 3.3 V
2.17
VDD = 5 V
3.35
VDD = 2.4 V
158
VDD = 3.3 V
215
VDD = 5 V
355
VDD = 2.4 V
75
VDD = 3.3 V
99
VDD = 5 V
156
Average suppy current
Halt mode
1. The results are based on CS = 2.7nF and CX = 12.5pF
Figure 8.
Min.
IDD Sleep mode current characteristics
Max.
Unit
mA
µA
µA
1
µA
QST104
6.5
Electrical characteristics
Capacitive sensing characteristics
Table 25.
External sensing components
Symbol
Parameter
Min.
Typ.
Max.
Unit
CS
Sense capacitor
100
nF
CX
Equivalent electrode capacitor
100
pF
CT
Equivalent touch capacitor
RS
Serial resistance
Table 26.
5
10
pF
22
kOhm
Capacitive sensing parameters
Symbol
Parameter
tCAL
Calibration duration
tSetup
Setup duration
Min.
Default
Max.
Unit
TBD
ms
100
ms
DI
Detection integrator
0
2
255
Counts
DeTh
Detection threshold
-128
-10
-1
Counts
EDI
End of detection integrator
0
2
255
Counts
EofDeTh
End of detection threshold
-128
-8
-1
Counts
PosRecalI
Positive recalibration integrator
0
2
255
Counts
PosRecalTh
Positive recalibration threshold
1
6
128
Counts
1
Infinite
255
s
MaxOnDuration Max on-duration delay
PosDiffDrift
Positive differential drift compensation rate
0.1
1
25.5
s/level
NegDiffDrift
Negative differential drift compensation rate
0.1
1
25.5
s/level
PosComDrift
Positive common drift compensation rate
0.1
0.2
25.5
s/level
NegComDrift
Negative common drift compensation rate
0.1
0.2
25.5
s/level
PosDriftI
Positive drift integrator
0
10
255
NegDriftI
Negative drift integrator
0
10
255
ComFact
Common time step factor
0
10
255
Differential time step factor
0
2
255
Burst length
20
DiffFact
BurstCount
2000
Counts
33/45
Electrical characteristics
QST104
6.6
KOUTn/OPTn/GPOn pin characteristics
6.6.1
General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 27.
Symbol
General characteristics
Parameter
Conditions
Min.
Typ.
Max.
VIL
Input low level voltage (1)
VSS −0.3
0.3x VDD
VIH
Input high level voltage (1)
0.7x VDD
VDD +
0.3
VHys
Schmitt trigger voltage hysteresis(2)
IL
CIO
Input leakage current
Output high to low level fall time (2)
tr(IO)out
Output low to high level rise time (2)
V
400
VSS ≤ VIN ≤ VDD
I/O pin capacitance
tf(IO)out
Unit
mV
μA
±1
5
CL = 50 pF
Between 10%
and 90%
pF
25
ns
25
1. Not tested in production, guaranteed by characterization.
2. Data based on validation/design results.
6.6.2
Output pin characteristics
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
VOL
(1)
VOH(2)
Parameter
Conditions
Output low level voltage for a high sink I/O
pin when 4 pins are sunk at same time (see
Figure 14)
IIO =
+20mA
1.3
IIO = +8mA
0.75
Output high level voltage for an I/O pin when
4 pins are sourced at same time (see
Figure 19)
VOL(1)(3)
Output low level voltage for a high sink I/O
pin when 4 pins are sunk at same time
VOH(2)(3)
Output high level voltage for an I/O pin when
4 pins are sourced at same time (Figure 17)
VOL(1)(3)
Output low level voltage for a high sink I/O
pin when 4 pins are sunk at same time
VOH(2)(3)
Output high level voltage for an I/O pin when
4 pins are sourced at same time
VDD = 5V
Symbol
Output pin current
VDD = 2.4V VDD = 3.3V
Table 28.
Min.
IIO = -5mA
VDD−1.5
IIO = -2mA
VDD−0.8
IIO = +8mA
IIO = -2mA
Unit
0.5
V
VDD−0.8
IIO = +8mA
IIO = -2mA
Max.
0.6
VDD−0.9
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 22 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Table 22 and the
sum of IIO (output and RESET pins) must not exceed IVDD..
3. Not tested in production, based on characterization results.
34/45
QST104
Electrical characteristics
Figure 9.
Typical VOL at VDD = 2.4 V
Figure 10.
Typical VOL vs VDD at Iload = 2 mA
V OLvs VDD @Iload=2 mA HS Pins
VOL vs I load @ VDD = 2.4 V HS pins
120
1000
VOL [V]
110
25°C
25°C
100
85°C
85°C
90
125°C
125°C
800
-40°C
-40°C
V OL[mV]
1200
600
80
70
60
50
400
40
2.4 2.6 2.8 3 3.2 3.4 3.6 3.8
200
4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6
VDD [V]
0
0
2
4
6
8
10
12
14
16
I load [mA]
Figure 11.
Typical VOL at VDD = 3 V
Figure 12.
VOL vs VDD@Iload = 8 mA HS Pins
VOLvs I load @ VDD = 3 V HS pins
1600
-40°C
1400
25°C
85°C
540
-40°C
490
25°C
440
85°C
125°C
VOL [mV]
VOL [V]
1200
Typical VOL vs VDD at Iload = 8 mA
125°C
1000
800
390
340
290
240
600
190
400
140
2.4 2.6 2.8 3 3.2 3.4 3.6 3.8
200
4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6
VDD [V]
0
0
2
4
6
8
10
12
14
16
18
20
I load [mA]
Figure 13.
Typical VOL at VDD = 5 V
Figure 14.
VOL vs VDD @Iload = 12 mA HS Pins
VOL vs I load @ VDD = 5 V HS pins
1040
940
-40°C
800
25°C
700
85°C
600
125°C
-40°C
25°C
840
740
VOL [mV]
VOL [V]
900
Typical VOL vs VDD at Iload = 12 mA
500
85°C
125°C
640
540
440
340
400
240
140
300
200
2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6
100
VDD [V]
0
0
2
4
6
8
10
12
14
16
18
20
I load [mA]
35/45
Electrical characteristics
Figure 15.
QST104
Typical VDD-VOH vs. Iload at VDD = 2.4 V
Figure 16.
Typical VDD-VOH vs. VDD at Iload = 2 mA
VDD-VOH vs Iload @ VDD = 2.4 V HS Pins
300
0
2.
4
100
100
0
2
4
5.
2
200
200
4.
8
300
125°C
400
4
400
85°C
4.
4
125°C
500
25°C
500
3.
6
85°C
600
3.
2
600
-40°C
700
2.
8
25°C
5.
6
-40°C
700
VDD -VOH [mV]
VDD -VOH [mV]
VDD-VOH vs VDD @Iload = 2 mA HS Pins
800
800
VDD [V]
Iload [mA]
Figure 17.
Typical VDD-VOH vs. Iload at VDD = 3 V
Figure 18.
Typical VDD-VOH vs. VDD at Iload = 4 mA
VDD-VOH vs Iload @ VDD = 3 V HS Pins
-40°C
1600
-40°C
1600
25°C
1400
25°C
1400
85°C
1200
85°C
1200
125°C
1000
125°C
VDD -VOH [mV]
1000
800
200
400
0
2
4
Typical VDD-VOH vs. Iload at VDD = 5 V
V DD-V OH vs Iload @ V DD = 5 V HS Pins
VDD-VOH [mV]
-40°C
4000
25°C
3500
85°C
3000
125°C
2500
2000
1500
1000
500
0
0
2
4
6
8
Iload[mA]
10
12
14
5.
4
5
4.
6
4.
2
VDD [V]
6
Iload[mA]
4500
3.
8
2.
6
0
3.
4
0
200
36/45
600
400
600
Figure 19.
800
3
VDD-VOH [mV]
VDD-VOH vs VDD @Iload = 4 mA HS Pins
1800
1800
QST104
6.7
Electrical characteristics
RESET pin
TA = -40°C to 125°C, unless otherwise specified.
Table 29.
Symbol
RESET pin characteristics
Parameter
Conditions
Min.
Typ.
Max.
VIL
Input low level voltage
VSS − 0.3
0.3x VDD
VIH
Input high level voltage
0.7 x VDD
VDD + 0.3
Vhys
Schmitt trigger voltage
hysteresis(1)
VOL
Output low level
voltage(2)
VDD = 5V
RON
Pull-up equivalent
resistor(3)
VIN = VSS
tw(RSTL)out
Generated reset pulse
duration
th(RSTL)in
External reset pulse
hold time(4)
tg(RSTL)in
Filtered glitch duration
IIO = +2mA
VDD = 5V
30
V
200
mV
50
70
90(1)
Internal reset sources
V
2
90(1)
VDD = 3V
Unit
kΩ
μs
μs
20
200
ns
1. Data based on characterization results, not tested in production.
2. The IIO current sunk must always respect the absolute maximum rating specified in Table 22: Current
characteristics on page 31 and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin
between VILmax and VDD.
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses
applied on RESET pin with a duration below th(RSTL)in can be ignored.
37/45
Electrical characteristics
6.8
QST104
I2C control interface
Subject to general operating conditions for VDD, and TA unless otherwise specified.
The QST104 I2C interface meets the requirements of the Standard I2C communication
protocol described in the following table with the restriction mentioned below:
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDA and SCL).
Table 30.
I²C characteristics
100 kHz speed
Symbol
Parameter
Min. (1)
Max. (1)
tw(SCLL)
SCL clock low time
4.7
tw(SCLH)
SCL clock high time
4.0
tsu(SDA)
SDA setup time
250
th(SDA)
SDA data hold time
0 (2)
tr(SDA)
tr(SCL)
SDA and SCL rise time
1000
tf(SDA)
tf(SCL)
SDA and SCL fall time
300
th(STA)
START condition hold time
4.0
tsu(STA)
Repeated START condition setup time
4.7
tsu(STO)
STOP condition setup time
µs
ns
ns
tw(STO:STA) STOP to START condition time (bus free)
Cb
Unit
µs
4.0
μs
4.7
µs
Capacitive load for each bus line
400
pF
1. Data based on standard I2C protocol requirement, not tested in production.
2. The maximum hold time of the START condition has only to be met if the interface does not stretch the low
period of the SCL signal.
Table 31.
Symbol
tW(IRQ)
RIRQ
IRQ specific pin characteristics (1)
Parameter
Conditions
IRQ pulse width
IRQ internal pull-up (2)
Min.
Typ.
10
VDD = 5V
VDD = 3V
100
120
Max.
Unit
15
µs
140
kΩ
300
1. For additional pin parameters, please use the pin description in Section 6.6: KOUTn/OPTn/GPOn pin
characteristics on page 34.
2. The IRQ pull-up equivalent resistor is based on a resistive transistor.
38/45
QST104
Electrical characteristics
Figure 20. Typical application with I2C bus and timing diagram
VDD
4.7kΩ
2C
I
VDD
4.7kΩ
BUS
100Ω
SDA
100Ω
SCL
QST device
REPEATED START
START
tsu(STA)
tw(STO:STA)
START
SDA
tr(SDA)
tf(SDA)
tsu(SDA)
STOP
th(SDA)
SCL
th(STA)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
tsu(STO)
39/45
Package mechanical data
7
QST104
Package mechanical data
Figure 21. 32-pin low profile quad flat package (7x7) outline
Seating
plane
C
A A2
A1
c
b
ccc
0.25 mm
Gage plane
C
D
D1
L
A1
L1
D3
24
17
16
25
E3
32
Pin 1
identification
E1
E
9
1
8
e
40/45
K
5V_ME
QST104
Package mechanical data
Table 32.
32-pin low profile quad flat package mechanical data
inches(1)
mm
Dim.
Min.
Typ.
A
Max.
Min.
Typ.
1.600
Max.
0.0630
A1
0.050
0.150
0.0020
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.300
0.370
0.450
0.0118
0.0146
0.0177
c
0.090
0.200
0.0035
D
8.800
9.000
9.200
0.3465
0.3543
0.3622
D1
6.800
7.000
7.200
0.2677
0.2756
0.2835
D3
5.600
0.0059
0.0079
0.2205
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
5.600
0.2205
e
0.800
0.0315
L
0.450
L1
K
ccc
0.600
0.750
0.0177
7.0°
0.0°
1.000
0.0°
3.5°
0.0236
0.0295
0.0394
3.5°
Tolerance (mm)
Tolerance (inches)
0.10
0.0039
7.0°
1. Values in inches are converted from mm and rounded to 4 decimal digits.
41/45
Part numbering
8
QST104
Part numbering
Table 33.
Ordering information scheme
Example:
QST
1
04
K
T
6
Device type
QST = Capacitive touch sensor
Device sub-family
1:
QTouch (3 to 5 V)
Channel count
Number of channels
Pin count
K: 32 pins
Package
T:
LQFP (thin quad flat)
Temperature range
6: –40°C to +85°C
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST Sales Office.
The category of second Level Interconnect is marked on the package and on the inner box
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to
soldering conditions are also marked on the inner box label.
42/45
QST104
Device revision information
9
Device revision information
9.1
Device revision identification
The marking on the right side of the second line (Line B) of the package top face identifies
the device revision.
Figure 22. Device revision identification (TQFP package)
A
B
QST104
QRG
C
H00
D
F
a
Table 34.
E
G
J
I
H
K
Device revision identification
Marking
Device revision
H00
V 1.0
The device revision can also be obtained using the GET_DEVICE_INFO I2C command. For
more information, refer to Section 4.9: Supported commands on page 16.
9.2
Device revision history
This section identifies the device deviations from the present specification for each device
revision.
9.2.1
Revision 1.0
When the device enters low power mode, an additional sleep time is inserted after each
burst, instead of once after every complete burst cycle. As a result, if only one burst is
required, the sleep duration during low power mode is doubled. And if two bursts are
required, the sleep duration is tripled.
In standalone mode, the 100ms sleep duration low power becomes either a 200ms or
300ms sleep duration depending on the number of bursts required.
In I2C mode, it is required to program a sleep duration for one half or a third of the desired
sleep duration depending on the number of bursts required.
GET_PROTOCOL_VERSION returns 0x01 as I2CSpeed byte while it should return 0x00
(maximum speed is 100 kHz).
43/45
Revision history
10
QST104
Revision history
Table 35.
44/45
Document revision history
Date
Revision
Changes
26-Nov-2007
1
Initial release.
5-Feb-2008
2
Upgraded document status to datasheet.
QST104
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