STD55NH2LL STD55NH2LL-1 N-channel 24V - 0.010Ω - 40A - DPAK/IPAK Ultra low gate charge STripFET™ Power MOSFET General features Type VDSS RDS(on) ID STD55NH2LL-1 24V <0.011Ω 40A(1) STD55NH2LL 24V <0.011Ω 40A(1) 1. Value limited by wire bonding ■ RDS(ON) * Qg industry’s benchmark ■ Conduction losses reduced ■ Switching losses reduced ■ Low threshold device 3 3 2 1 iPAK 1 DPAK Description The STD55NH2LL is based on the latest generation of ST's proprietary STripFET™ technology. An innovative layout enables the device to also exhibit extremely low gate charge for the most demanding requirements as highside switch in high-frequency DC-DC converters. It's therefore ideal for high-density converters in Telecom and Computer applications. Internal schematic diagram Applications ■ Switching application Order codes Part number Marking Package Packaging STD55NH2LL-1 D55NH2LL IPAK Tube STD55NH2LLT4 D55NH2LL DPAK Tape & reel July 2006 Rev 5 1/16 www.st.com 16 Contents STD55NH2LL - STD55NH2LL-1 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 6 3 Test circuit 4 Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 Packing mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2/16 ................................................ 8 STD55NH2LL - STD55NH2LL-1 1 Electrical ratings Electrical ratings Table 1. Absolute maximum ratings Symbol Vspike (1) VDS VDGR Parameter Value Unit Drain-source voltage rating 30 V Drain-source voltage (VGS = 0) 24 V Drain-gate voltage (RGS = 20 kΩ) 24 V ± 16 V VGS Gate- source voltage ID(2) Drain current (continuous) at TC = 25°C 40 A ID(2) Drain current (continuous) at TC = 100°C 28 A Drain current (pulsed) 160 A Total dissipation at TC = 25°C 60 W Derating Factor 0.4 W/°C Single pulse avalanche energy 600 mJ -55 to 175 °C IDM (3) Ptot EAS (4) Tstg Tj Storage temperature Max. operating junction temperature 1. Garanted when external Rg=4.7 Ω and tf < tfmax. 2. Value limited by wire bonding 3. Pulse width limited by safe operating area. 4. Starting Tj = 25 °C, ID = 20A, VDD = 15V Table 2. Thermal data Rthj-case Thermal resistance junction-case max 2.5 °C/W Rthj-amb Thermal resistance junction-ambient max 100 °C/W Maximum lead temperature for soldering purpose 275 °C TJ 3/16 Electrical characteristics 2 STD55NH2LL - STD55NH2LL-1 Electrical characteristics (TCASE=25°C unless otherwise specified) Table 3. On/off states Symbol Parameter V(BR)DSS Drain-source breakdown voltage ID = 25mA, VGS =0 IDSS Zero gate voltage drain current (VGS = 0) VDS = max rating VDS = max rating TC = 125°C IGSS Gate-body leakage current (VDS = 0) VGS = ± 16V VGS(th) Gate threshold voltage VDS = VGS, ID = 250µA RDS(on) Static drain-source on resistance VGS = 10V, ID = 20A VGS = 4.5V, ID = 20A Table 4. Symbol Test conditions Typ. Max. 24 Unit V 1 10 µA µA ±100 nA 1 V 0.010 0.012 0.011 0.0135 Ω Ω Typ. Max. Unit Dynamic Parameter Test conditions Min. gfs (1) Forward transconductance VDS = 10V, ID = 10A 18 S Ciss Coss Crss Input capacitance Output capacitance Reverse transfer capacitance VDS = 25V, f = 1MHz, VGS = 0 990 385 40 pF pF pF Gate Input Resistance f = 1 MHz Gate DC Bias = 0 Test Signal Level = 20 mV Open Drain 1.3 Ω td(on) tr td(off) tf Turn-on delay time Rise time Turn-off delay time Fall time VDD = 10V, ID = 20A RG = 4.7Ω VGS = 4.5V (see Figure 13) 15 56 13 10 ns ns ns ns Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge 0.44V ≤VDD ≤10V, ID = 40A, VGS = 4.5V, RG = 4.7Ω (see Figure 14) 8.7 4.2 2.4 Output charge VDS= 16 V, VGS= 0 V 7.6 RG Qoss(2) 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Qoss = Coss*∆ Vin , Coss = Cgd + Cds . See Chapter 4: Appendix A 4/16 Min. 11 nC nC nC nC STD55NH2LL - STD55NH2LL-1 Table 5. Symbol Source drain diode Parameter ISDM (1) Source-drain current Source-drain current (pulsed) VSD (2) Forward on voltage ISD trr Qrr IRRM Electrical characteristics Test conditions Min. Typ. ISD = 20A, VGS = 0 Reverse recovery time ISD = 40A, di/dt = 100A/µs, Reverse recovery charge VDD = 15V, Tj = 150°C Reverse recovery current (see Figure 15) 32.5 28 1.7 Max. Unit 40 160 A A 1.3 V ns nC A 1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % 5/16 Electrical characteristics STD55NH2LL - STD55NH2LL-1 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance 6/16 STD55NH2LL - STD55NH2LL-1 Electrical characteristics Figure 7. Gate charge vs gate-source voltage Figure 8. Figure 9. Normalized gate threshold voltage vs temperature Figure 11. Source-drain diode forward characteristics Capacitance variations Figure 10. Normalized on resistance vs temperature Figure 12. Normalized breakdown voltage vs temperature 7/16 Test circuit 3 STD55NH2LL - STD55NH2LL-1 Test circuit Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit Figure 17. Unclamped inductive waveform 8/16 Figure 18. Switching time waveform STD55NH2LL - STD55NH2LL-1 4 Appendix A Appendix A Figure 19. Buck converter: power losses estimation The power losses associated with the FETs in a synchronous buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature. ● The low side (SW2) device requires: ● Very low RDS(on) to reduce conduction losses ● Small Qgls to reduce the gate charge losses ● Small Coss to reduce losses due to output capacitance ● Small Qrr to reduce losses on SW1 during its turn-on ● The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source ● voltage to avoid the cross conduction phenomenon; ● The high side (SW1) device requires: ● Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the gate ● Small Qg to have a faster commutation and to reduce gate charge losses ● Low RDS(on) to reduce the conduction losses. 9/16 Appendix A STD55NH2LL - STD55NH2LL-1 Table 6. Power losses calculation High side switching (SW1) Low side switch (SW2) R DS(on)SW1 * I 2L * δ R DS(on)SW2 * I 2L * (1 − δ ) Pconduction Vin * (Q gsth(SW1) + Q gd(SW1) ) * f * Pswitching Recovery IL Ig Zero Voltage Switching (1) Not applicable Vin * Q rr(SW2) * f Conductio n Not applicable Vf(SW2) * I L * t deadtime * f Pgate(QG) Q g(SW1) * Vgg * f Q gls(SW2) * Vgg * f PQoss Vin * Q oss(SW1) * f Vin * Q oss(SW2) * f 2 2 Pdiode 1. Dissipated by SW1 during turn-on Table 7. Paramiters meaning Parameter d Duty-cycle Qgsth Post threshold gate charge Qgls Third quadrant gate charge Pconduction Pswitching 10/16 Meaning On state losses On-off transition losses Pdiode Conduction and reverse recovery diode losses Pgate Gate drive losses PQoss Output capacitance losses STD55NH2LL - STD55NH2LL-1 5 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 11/16 Package mechanical data STD55NH2LL - STD55NH2LL-1 TO-251 (IPAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A3 0.7 1.3 0.027 0.051 B 0.64 0.9 0.025 0.031 B2 5.2 5.4 0.204 0.212 B3 0.85 B5 0.033 0.3 0.012 B6 0.95 C 0.45 C2 0.48 D 6 E 6.4 6.6 0.037 0.6 0.017 0.023 0.6 0.019 0.023 6.2 0.236 0.244 0.252 0.260 G 4.4 4.6 0.173 0.181 H 15.9 16.3 0.626 0.641 L 9 9.4 0.354 0.370 L1 0.8 1.2 0.031 0.047 L2 0.8 1 0.031 0.039 A1 C2 A3 A C H B B3 = 1 = 2 G = = = E B2 = 3 B5 L D B6 L2 L1 0068771-E 12/16 STD55NH2LL - STD55NH2LL-1 Package mechanical data DPAK MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A A1 A2 B b4 2.2 0.9 0.03 0.64 5.2 2.4 1.1 0.23 0.9 5.4 0.086 0.035 0.001 0.025 0.204 0.094 0.043 0.009 0.035 0.212 C C2 D D1 E E1 e e1 H L (L1) L2 L4 R V2 0.45 0.48 6 0.6 0.6 6.2 0.017 0.019 0.236 0.023 0.023 0.244 6.6 0.252 5.1 6.4 0.200 4.7 2.28 4.4 9.35 1 4.6 10.1 0.173 0.368 0.039 2.8 0.8 0.6 0.181 0.397 0.110 0.031 1 0.023 0.2 0° 0.260 0.185 0.090 0.039 0.008 8° 0° 8° 0068772-F 13/16 Packing mechanical data 6 STD55NH2LL - STD55NH2LL-1 Packing mechanical data DPAK FOOTPRINT All dimensions are in millimeters TAPE AND REEL SHIPMENT REEL MECHANICAL DATA DIM. mm MIN. A B 1.5 C 12.8 D 20.2 G 16.4 N 50 T TAPE MECHANICAL DATA DIM. mm MIN. MAX. A0 6.8 7 0.267 0.275 B0 10.4 10.6 0.409 0.417 B1 D 14/16 inch 1.5 D1 1.5 E 1.65 MIN. MAX. 12.1 0.476 1.6 0.059 0.063 1.85 0.065 0.073 0.059 F 7.4 7.6 0.291 0.299 K0 2.55 2.75 0.100 0.108 0.153 0.161 P0 3.9 4.1 P1 7.9 8.1 0.311 0.319 P2 1.9 2.1 0.075 0.082 R 40 W 15.7 1.574 16.3 0.618 0.641 inch MAX. MIN. MAX. 330 12.992 13.2 0.504 0.520 18.4 0.645 0.724 0.059 0.795 1.968 22.4 0.881 BASE QTY BULK QTY 2500 2500 STD55NH2LL - STD55NH2LL-1 7 Revision history Revision history Table 8. Revision history Date Revision Changes 22-Jun-2004 2 Preliminary datasheet 21-Jul-2005 3 Complete version 13-Jun-2006 4 Packing mechanical data inserted 16-Jul-2006 5 New template, no content change 15/16 STD55NH2LL - STD55NH2LL-1 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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