STD40NF03L N-channel 30V - 0.0090Ω - 40A - DPAK Low gate charge STripFET™ II Power MOSFET General features Type VDSS RDS(on) ID STD40NF03L 30V <0.011Ω 40A ■ Logic level device ■ Optimal RDS(on) x Qg trade-off ■ Conduction losses reduced ■ Switching losses reduced ■ Low threshold drive 3 1 DPAK Description This application specific Power MOSFET is the third generation of STMicroelectronics unique "Single Feature Size™" strip-based process. The resulting transistor shows the best trade-off between on-resistance and gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high efficiency are of paramount importance. Internal schematic diagram Applications ■ Switching application Order codes Part number Marking Package Packaging STD40NF03LT4 D40NF03L DPAK Tape & reel February 2007 Rev 11 1/13 www.st.com 13 Contents STD40NF03L Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 6 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Packing mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/13 ................................................ 8 STD40NF03L 1 Electrical ratings Electrical ratings Table 1. Absolute maximum ratings Symbol VDS VDGR Parameter Value Unit Drain-source voltage (VGS = 0) 30 V Drain-gate voltage (RGS = 20 kΩ) 30 V ± 20 V VGS Gate- source voltage ID(1) Drain current (continuous) at TC = 25°C 40 A ID Drain current (continuous) at TC = 100°C 28 A Drain current (pulsed) 160 A Total dissipation at TC = 25°C 80 W Derating Factor 0.53 W/°C Peak diode recovery voltage slope 5.5 V/ns Single pulse avalanche energy 850 mJ -55 to 175 °C IDM (2) Ptot (3) dv/dt EAS (4) Tstg Tj Storage temperature Max. operating junction temperature 1. Current limited by package 2. Pulse width limited by safe operating area. 3. ISD ≤40A, di/dt ≤350A/µs, VDD ≤V(BR)DSS, Tj ≤TJMAX 4. Starting Tj = 25 °C, ID = 20A, VDD = 25V Table 2. Thermal data Rthj-case Thermal resistance junction-case max 1.88 °C/W Rthj-amb Thermal resistance junction-ambient max 100 °C/W Maximum lead temperature for soldering purpose 300 °C TJ 3/13 Electrical characteristics 2 STD40NF03L Electrical characteristics (TCASE=25°C unless otherwise specified) Table 3. On/off states Symbol Parameter V(BR)DSS Drain-source breakdown voltage ID = 250µA, VGS =0 IDSS Zero gate voltage drain current (VGS = 0) VDS = max rating VDS = max rating, TC = 125°C IGSS Gate-body leakage current (VDS = 0) VGS = ± 20V VGS(th) Gate threshold voltage VDS = VGS, ID = 250µA RDS(on) Static drain-source on resistance VGS = 10V, ID = 20A VGS = 5V, ID = 10A Table 4. Symbol Test conditions Typ. Max. 30 Unit V 1 10 µA µA ±100 nA 1 V 0.0090 0.0150 0.0110 0.0195 Ω Ω Typ. Max. Unit Dynamic Parameter Test conditions gfs (1) Forward transconductance VDS = 15V, ID = 20A Ciss Coss Crss Input capacitance Output capacitance Reverse transfer capacitance td(on) tr td(off) tf Qg Qgs Qgd Min. 23 S VDS = 25V, f = 1MHz, VGS = 0 1440 560 135 pF pF pF Turn-on delay time Rise time Turn-off delay time Fall time VDD = 15V, ID = 20A RG = 4.7Ω VGS = 5V (see Figure 13) 22 165 21 25 ns ns ns ns Total gate charge Gate-source charge Gate-drain charge VDD = 15V, ID = 40A, VGS = 5V, RG = 4.7Ω (see Figure 14) 22.5 9 12 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%. 4/13 Min. 30 nC nC nC STD40NF03L Electrical characteristics Table 5. Symbol Source drain diode Parameter ISDM (1) Source-drain current Source-drain current (pulsed) VSD (2) Forward on voltage ISD trr Qrr IRRM Test conditions Min. Typ. ISD = 20A, VGS = 0 Reverse recovery time ISD = 40A, di/dt = 100A/µs, Reverse recovery charge VDD = 20V, Tj = 150°C Reverse recovery current (see Figure 15) 42 52 2.5 Max. Unit 40 160 A A 1.3 V ns nC A 1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5% 5/13 Electrical characteristics STD40NF03L 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characteristics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance 6/13 STD40NF03L Electrical characteristics Figure 7. Gate charge vs. gate-source voltage Figure 8. Figure 9. Normalized gate threshold voltage vs. temperature Figure 11. Source-drain diode forward characteristics Capacitance variations Figure 10. Normalized on resistance vs. temperature Figure 12. Normalized breakdown voltage vs. temperature 7/13 Test circuit 3 STD40NF03L Test circuit Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit Figure 17. Unclamped inductive waveform 8/13 Figure 18. Switching time waveform STD40NF03L 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 9/13 Package mechanical data STD40NF03L DPAK MECHANICAL DATA mm. inch DIM. MAX. MIN. A A1 A2 B b4 MIN. 2.2 0.9 0.03 0.64 5.2 TYP 2.4 1.1 0.23 0.9 5.4 0.086 0.035 0.001 0.025 0.204 0.094 0.043 0.009 0.035 0.212 C C2 D D1 E E1 e e1 H L (L1) L2 L4 R V2 0.45 0.48 6 0.6 0.6 6.2 0.017 0.019 0.236 0.023 0.023 0.244 6.6 0.252 5.1 6.4 0.173 0.368 0.039 2.8 0.8 0.181 0.397 0.110 0.031 1 0.023 0.2 0° 0.260 0.185 0.090 4.6 10.1 0.6 MAX. 0.200 4.7 2.28 4.4 9.35 1 TYP. 0.039 0.008 8° 0° 8° 0068772-F 10/13 STD40NF03L 5 Packing mechanical data Packing mechanical data DPAK FOOTPRINT All dimensions are in millimeters TAPE AND REEL SHIPMENT REEL MECHANICAL DATA DIM. mm MIN. A B 1.5 C 12.8 D 20.2 G 16.4 N 50 T TAPE MECHANICAL DATA DIM. mm inch MIN. MAX. A0 6.8 7 0.267 0.275 B0 10.4 10.6 0.409 0.417 B1 D 1.5 D1 1.5 E 1.65 MIN. 12.1 0.476 1.6 0.059 0.063 1.85 0.065 0.073 7.4 7.6 0.291 0.299 2.55 2.75 0.100 0.108 0.153 0.161 P0 3.9 4.1 P1 7.9 8.1 0.311 0.319 P2 1.9 2.1 0.075 0.082 40 15.7 MAX. 330 12.992 13.2 0.504 0.520 18.4 0.645 0.724 0.059 0.795 1.968 22.4 0.881 BASE QTY BULK QTY 2500 2500 0.059 F R MIN. MAX. K0 W inch MAX. 1.574 16.3 0.618 0.641 11/13 Revision history 6 STD40NF03L Revision history Table 6. 12/13 Revision history Date Revision Changes 21-Jun-2004 9 Preliminary data 11-Jul-2006 10 New template, no content change 20-Feb-2007 11 Typo mistake on page 1 STD40NF03L Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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