STL150N3LLH5 N-channel 30 V, 0.0014 Ω, 35 A - PowerFLAT™ (6x5) STripFET™ V Power MOSFET Features Type VDSS STL150N3LLH5 30 V RDS(on) max ID <0.00175 Ω 35 A (1) 1. The value is rated according Rthj-pcb ■ RDS(on) * Qg industry benchmark ■ Extremely low on-resistance RDS(on) ■ High avalanche ruggedness ■ Low gate drive power losses PowerFLAT™ ( 6x5 ) Application ■ Switching applications Figure 1. Internal schematic diagram Description This product utilizes the 5th generation of design rules of ST’s proprietary STripFET™ technology. The lowest available RDS(on)*Qg, in this chip scale package, makes this device suitable for the most demanding DC-DC converter applications, where high power density is to be achieved. Table 1. Device summary Order code Marking Package Packaging STL150N3LLH5 150N3LLH5 PowerFLAT™ (6x5) Tape and reel September 2008 Rev 3 1/12 www.st.com 12 Contents STL150N3LLH5 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/12 .............................................. 8 STL150N3LLH5 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit 30 V VDS Drain-source voltage (VGS = 0) VGS Gate-source voltage ± 22 V ID(1) Drain current (continuous) at TC = 25 °C 150 A ID (1) Drain current (continuous) at TC = 100 °C 94 A ID(2) Drain current (continuous) at TC = 25 °C 35 A (3) Drain current (continuous) at TC=100 °C 21.8 A (3) Drain current (pulsed) 140 A PTOT (1) Total dissipation at TC = 25 °C 80 W (3) Total dissipation at TC = 25 °C 4 W 0.03 W/°C -55 to 150 °C ID IDM PTOT Derating factor TJ Operating junction temperature Storage temperature Tstg 1. The value is rated according Rthj-c 2. The value is rated according Rthj-pcb 3. Pulse width limited by safe operating area Table 3. Thermal resistance Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case (drain) (steady state) 1.56 °C/W Thermal resistance junction-ambient 31.3 °C/W Value Unit Rthj-pcb (1) 1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec Table 4. Symbol Avalanche data Parameter IAV Not-repetitive avalanche current, (pulse width limited by Tj Max) 17 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID = IAV , VDD = 24 V) 300 mJ 3/12 Electrical characteristics 2 STL150N3LLH5 Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 5. Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions ID = 250 µA, VGS= 0 Zero gate voltage drain current (VGS = 0) IGSS Gate body leakage current (VDS = 0) VGS = ±22 V VGS(th) Gate threshold voltage VDS= VGS, ID = 250 µA RDS(on) Static drain-source on resistance VGS= 10 V, ID= 17.5 A Symbol Ciss Coss Crss Qg Typ. Max. 30 V VDS = Max rating @125 °C 1 10 µA µA ±100 nA 1 V 0.0014 0.00175 0.0019 0.0024 VGS= 4.5 V, ID= 17.5 A Unit Ω Ω Dynamic Parameter Input capacitance Output capacitance Reverse transfer capacitance Qgd Total gate charge Gate-source charge Gate-drain charge RG Gate input resistance Qgs Min. VDS = Max rating, IDSS Table 6. 4/12 On/off states Test conditions VDS = 25 V, f=1 MHz, VGS=0 VDD=15 V, ID = 35 A VGS =4.5 V (see Figure 14) f=1 MHz Gate DC Bias = 0 Test signal level = 20 mV open drain Min. Typ. Max. Unit 5800 1147 127 pF pF pF 40 13.4 14.9 nC nC nC 1.1 Ω STL150N3LLH5 Electrical characteristics Table 7. Symbol td(on) tr td(off) tf Table 8. Symbol Switching times Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. 17.2 30.8 65.8 47.8 VDD=15 V, ID= 17.5 A, RG=4.7 Ω, VGS=10 V (see Figure 13) Unit ns ns ns ns Source drain diode Max Unit Source-drain current 35 A ISDM(1) Source-drain current (pulsed) 140 A VSD(2) Forward on voltage ISD = 35 A, VGS=0 1.1 V Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 35 A, ISD trr Qrr IRRM Parameter Test conditions di/dt = 100 A/µs, VDD=25 V Min Typ. 43.8 46 2.1 ns nC A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300µs, duty cycle 1.5% 5/12 Electrical characteristics STL150N3LLH5 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Thermal impedance HV42710 ID(A) a is are n) his S(o n t RD n o ax io m t era by Op ited lim 100 Figure 3. TJ = 150 °C TC = 25 °C Single pulse 10 ms 10 100 ms 1 1s 0.1 0.01 0.1 1 VDS(V) 10 Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Normalized BVDSS vs temperature Figure 7. Static drain-source on resistance HV42790 BVDSS HV42770 RDS(on) (mΩ) (norm) 1.1 2.5 1.05 2.0 1 1.5 0.95 1.0 0.9 0.5 0.85 -55 6/12 -30 -5 20 45 70 95 120 145 TJ(°C) 0 10 20 30 ID(A) STL150N3LLH5 Figure 8. Electrical characteristics Gate charge vs gate-source voltage Figure 9. HV42730 VGS(V) Capacitance variations HV42760 C(pF) f=1MHz VDD=15 V VGS=5 V ID=34 A 12 10 10000 8000 8 Ciss 6000 6 4 4000 2 2000 Coss Crss 0 0 20 0 40 60 Qg(nC) Figure 10. Normalized gate threshold voltage vs temperature HV42740 VGS(th) (norm) 10 0 20 VDS(V) Figure 11. Normalized on resistance vs temperature HV42750 RDS(on) (norm) ID=250µA 1.2 1.6 1 1.4 0.8 1.2 0.6 1 0.4 0.8 0.2 -55 -30 -5 20 45 70 95 120 145 TJ (°C) 0.6 -55 ID=17 A VGS=10 V -30 -5 20 45 70 95 120 145 TJ(°C) Figure 12. Source-drain diode forward characteristics HV42780 VSD(V) 0.8 TJ=-55°C 0.7 TJ=25°C 0.6 0.5 TJ=175°C 0.4 0.3 0 10 20 30 ID(A) 7/12 Test circuits 3 STL150N3LLH5 Test circuits Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit Figure 15. Test circuit for inductive load Figure 16. Unclamped inductive load test switching and diode recovery times circuit Figure 17. Unclamped inductive waveform 8/12 Figure 18. Switching time waveform STL150N3LLH5 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 9/12 Package mechanical data STL150N3LLH5 Pow erFLA T™ (6x5)m echanicaldata mm. inch D IM . M in. A 0.83 0.93 0.02 0.05 A3 0.20 0.35 D D2 0.40 M in. 0.031 0.47 0.013 4.20 0.32 0.036 0.0007 0.0019 0.015 0.163 0.165 E 6.00 0.236 5.75 0.226 E2 3.43 3.48 3.53 E4 2.58 2.63 2.68 0.70 0.80 L 0.018 0.187 4.25 E1 e M ax. 0.196 4.75 4.15 Typ. 0.007 5.00 D1 10/12 M ax. A1 b 0.80 Typ. 0.135 1.27 0.167 0.137 0.139 0.103 0.105 0.050 0.90 0.027 0.031 0.035 STL150N3LLH5 5 Revision history Revision history Table 9. Document revision history Date Revision Changes 22-Oct-2007 1 First release 01-Apr-2008 2 Document status promoted from preliminary data to datasheet 23-Sep-2008 3 VGS value has been changed on Table 2 and Table 5 11/12 STL150N3LLH5 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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