STOD1412 Step-up and inverting DC-DC converter Features ■ 2.7 V to 5.5 V input voltage range ■ 120 mA max output current for each converter ■ Output voltages: – Step-up from 4.3 V to 6.0 V – Inverting from -8.0 V to -2.0 V ■ Synchronous rectification for both DC-DC converters ■ Efficiency: – 80% IO = 10 mA - 30 mA – 85% IO = 30 mA - 120 mA ■ 1.3 MHz PWM mode control ■ Shutdown mode with Enable pin ■ Inrush current protection ■ Adjustable output voltages ■ True shutdown mode ■ Less than 1 µA current consumption in shutdown mode ■ Over-temperature protection ■ Package: 16 pin - QFN 3X3 ■ Temperature range: -40°C to 85°C Description The STOD1412 is a dual DC-DC converter capable of providing a positive and negative voltage from a positive input voltage ranging from 2.7 V to 5.5 V. It integrates two complete power stages, one step-up and one inverting, each of which need just one inductor, and input and output capacitor. The STOD1412 works in PWM mode, switching at a 1.3 MHz frequency, thus reducing the size and values of external components. An Enable pin makes it possible to turn off the device to reduce the quiescent current to less than 1 µA. The output voltages can be set easily by using two external resistors for each converter. Applications ■ Active matrix organic LED power supplies ■ Mobile phones ■ PDAs ■ Camcorders ■ Digital still cameras Table 1. QFN16L (3mm x 3mm) The device integrates a “soft start” with controlled inrush current limit, thermal shutdown and short circuit protection. High efficiency and low quiescent current, combined with the small number and tiny size of external components, make the STOD1412 suitable for battery-operated systems, particularly for powering Active Matrix OLED display panels. Device summary Order code Package Packaging STOD1412PUR QFN16L (3x3 mm) 4500 parts per reel August 2007 Rev. 1 1/21 www.st.com 21 STOD1412 Contents 1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 Setting output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2 Under voltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 Load disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.5 Soft start and inrush current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.6 Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.7 External components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.7.1 Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.7.2 Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.7.3 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/21 STOD1412 Diagram 1 Diagram Figure 1. Block diagram 3/21 Pin configuration STOD1412 2 Pin configuration Figure 2. Pin connections (top view) Table 2. Pin description Pin n° Symbol 1 VO1 2 TRIM Trimming pin. This pin must be left floating. 3 TRIM Trimming pin. This pin must be left floating. 4 TRIM Trimming pin. This pin must be left floating. 5 FB1 Feedback pin of the step-up converter. 6 VREF External voltage reference. A CREF = 100 nF ceramic capacitor must be connected to this pin. 7 GND Signal ground pin. This pin must be connected to PGND pin. 8 FB2 Feedback pin of the inverting converter. 9 VI Input supply voltage. 10 EN Enable control pin. ON = VI. When pulled low the device goes into shutdown mode. 11 TRIM 12 VCC Power input supply voltage. 13 Lx2 Switching node of the inverting converter. 14 VO2 Inverting converter output voltage. 15 PGND 16 Lx1 Exp pad 4/21 Description Step-up converter output voltage. Trimming pin; this pin must be left floating. Power ground pin. Switching node of the step-up converter. Exposed pad. This pin must be connected to VO2. STOD1412 Maximum ratings 3 Maximum ratings Table 3. Absolute maximum ratings Symbol Value Unit DC supply voltage -0.3 to 6 V EN Enable pin -0.3 to 6 V ILx2 Switching current of the converter Internally limited A Lx2 Inverting converter switching node -10 to VI+0.3 V VO2 Inverting converter output voltage F10 to GND+0.3 V FB2 Inverting converter feedback pin -1 to +1 V FB1 Step-up converter feedback pin -0.3 to VI+0.3 V VO1 Step-up converter output voltage -0.3 to 6 V Lx1 Step-up converter switching node -0.3 to OUT1+0.3 V ILx1 Step-up converter’s switching current Internally limited A VREF Reference voltage -0.3 to 3 V PD Power dissipation Internally Limited mW X Storage temperature range -65 to 150 °C TJ Operating junction temperature range -40 to 85 °C VI, VCC Table 4. Symbol RthJA Parameter Thermal data Parameter Thermal resistance junction-ambient Value Unit 49 °C/W 5/21 Electrical characteristics STOD1412 4 Electrical characteristics Table 5. Electrical characteristics (TJ=25°C, VI =VCC=3.7 V, CI=2.2 µF, CO1,2=4.7 µF, C3=1 µF, CREF=100 nF, L1=4.7 µH, L2=6.8 µH, IO1,2=IO1-IO2=30 mA, VEN=VI, VO1=4.6 V, VO2=-6.4 V, R1=470 kΩ, R2=166 kΩ, R3=533 kΩ, R4=100 kΩ, unless otherwise specified). Symbol Parameter Test condition Min. Typ. Max. Unit Supply section VI Supply input voltage 2.7 5.5 Operating input voltage range 2.7 4.5 UVLO_H Under voltage lockout HIGH UVLO_L Under voltage lockout LOW I_VI Input current V VCC V 2.5 V VFB1=1.3 V, VFB2= -0.5 V (no switching) 0.5 No Load 3.5 Quiescent current VEN=GND VEN H Enable high threshold VI=2.7 V to 4.5 V VEN L Enable low threshold VI=2.7 V to 4.5 V IEN Enable input current VEN=VI IQ 2.55 1 mA 1 µA 0.6 V 1 µA 1.2 Dynamic performance Freq. Frequency 1.3 MHz D1MAX Maximum duty cycle No load 90 % D2MAX Maximum duty cycle No load 90 % IO1,2=10 to 30 mA, VO1=4.6 V, VO2= -6.4 V 80 IO1,2=30 to 120 mA, VO1=4.6 V, VO2= -6.4 V 85 Total system efficiency % Step-up converter section VFB1 Feedback voltage on step-up (1) VI=2.7 V to 4.5 V ΔVO1 Static line regulation ΔVO1 Static line regulation 6/21 1.20 V VI=2.7 V to 4.2 V, IO1=5 mA, IO2 no load, TJ= -40°C to 85°C 2 % VI=2.7 V to 4.2 V, IO1=100 mA, IO2 no load, TJ= -40°C to 85°C 2 % STOD1412 Table 5. Symbol Electrical characteristics Electrical characteristics (continued) (TJ=25°C, VI =VCC=3.7 V, CI=2.2 µF, CO1,2=4.7 µF, C3=1 µF, CREF=100 nF, L1=4.7 µH, L2=6.8 µH, IO1,2=IO1-IO2=30 mA, VEN=VI, VO1=4.6 V, VO2=-6.4 V, R1=470 kΩ, R2=166 kΩ, R3=533 kΩ, R4=100 kΩ, unless otherwise specified). Parameter Test condition Min. Typ. Max. Unit ΔVO1 Static load regulation IO1=5 to 100 mA, IO2 no load, VI=2.7 V, TJ= -40°C to 85°C 2 % ΔVO1 Static load regulation IO1=5 to 100 mA, IO2 no load, VI=4.2 V, TJ= -40°C to 85°C 2 % ΔVO1 Load transient regulation IO1=3 to 30 mA and IO1=30 to 3 mA, TR=TF=30 µs 20 mV ΔVO1 Load transient regulation IO1=10 to 100 mA and IO1=100 to 10 mA, TR=TF=30 µs 30 mV ΔVO1 Ripple output voltage range IO1=5 to 100 mA @ Low frequency typ.=20 kHz 20 mV 120 mA IO1 Step-up range load current 0.9 A RDSONP1 1.10 Ω RDSONN1 0.85 Ω -0.5 mV I-L1MAX I peak current VO1 below 10% of nominal value Inverting converter section VFB2 Feedback voltage on inverting (1) VI=2.7 V to 4.5 V ΔVO2 Static line regulation VI=2.7 V to 4.2 V, IO2=5 mA, IO1 no load, TJ= -40°C to 85°C 2 % ΔVO2 Static line regulation VI=2.7 V to 4.2 V, IO2=100 mA, IO1 no load, TJ= -40°C to 85°C 2 % ΔVO2 Static load regulation IO2=5 to 100 mA, IO1 no load, VI=2.7 V, TJ= -40°C to 85°C 2 % ΔVO2 Static load regulation IO2=5 to 100 mA, IO1 no load, VI=4.2 V, TJ= -40°C to 85°C 2 % ΔVO2 Load transient regulation IO2=3 to 30 mA and IO2=30 to 3 mA, TR=TF=30 µs 50 mV ΔVO2 Load transient regulation IO2=10 to 100 mA and IO2=100 to 10 mA, TR=TF=30 µs 100 mV ΔVO2 Ripple output voltage range IO2=5 to 100 mA @ Low frequency typ.=20 kHz 20 mV IO2 Inverting range load current A RDSONP2 0.63 Ω RDSONN2 0.65 Ω VREF Voltage reference VO2 below 10% of nominal value mA -1 I-L2MAX I peak current -120 IREF=10 µA 1.192 1.209 1.228 V 7/21 Electrical characteristics Table 5. Symbol IREF STOD1412 Electrical characteristics (continued) (TJ=25°C, VI =VCC=3.7 V, CI=2.2 µF, CO1,2=4.7 µF, C3=1 µF, CREF=100 nF, L1=4.7 µH, L2=6.8 µH, IO1,2=IO1-IO2=30 mA, VEN=VI, VO1=4.6 V, VO2=-6.4 V, R1=470 kΩ, R2=166 kΩ, R3=533 kΩ, R4=100 kΩ, unless otherwise specified). Parameter Voltage reference current VREF = 1.192 V capability Test Min. Typ. Max. Unit µA 100 Thermal shutdown OTP OTPHYST Over-temperature protection 140 °C Over-temperature protection hysteresis 15 °C 1. Guaranteed by design. 2. The tolerance of external components is not included. 8/21 STOD1412 5 Introduction Introduction The STOD1412 is a dual DC-DC converter which produces one positive and one negative output voltage that are each independently regulated and the values of which can be adjusted with external resistors. Each DC-DC converter is able to supply up to 120 mA of current with input voltage ranging from 2.7 V and 5.5 V. The device uses a fixed-frequency PWM controller at 1.3 MHz. This control scheme simplifies noise filtering in sensitive applications and provides excellent line regulation. The operation of the STOD1412 can be best understood by referring to the block diagram in Figure 3, where the step-up control circuit is shown, and a similar scheme is adopted for the inverting section. At the start of each oscillator cycle, the SR latch is set, which turns on power switch SW1. A voltage proportional to the switch current is added to the sawtooth ramp and the resulting sum is fed into the positive terminal of the PWM comparator A2. When this voltage exceeds the level of the negative input of A2, the SR latch is reset, thus turning off the power switch. The voltage level of the negative input of A2 is set by the error amplifier A1, and it is simply an amplified version of the difference between the feedback voltage and the reference voltage. In this manner, the error amplifier sets the correct peak current level necessary to keep the output in regulation. If the error amplifier output increases, more current is delivered to the output; if it decreases, less current is delivered. The device also has a current limit circuit (not shown in Figure 2). The switch current is constantly monitored and not allowed to exceed the preset maximum switch current (IL1max, IL2-max). If the switch current reaches this value, the SR latch is reset regardless of the state of comparator A2. This current limit helps protecting the power switch as well as the external components connected to the device. The step up converter works in continuous mode detector (CMD) in the entire line and load range, while the inverting converter can work in both discontinuous mode detector (DMD) and CMD. Figure 3. PWM control scheme 9/21 Introduction 5.1 STOD1412 Setting output voltage The output voltage can be set using external network resistors. The positive output voltage range is 4.3 V minimum up to a maximum of 6.0 V. It is obtained by connecting FB1 to OUT1 through R2, and FB1 to PGND through R1 (see application circuit). The positive output value can be calculated using the following formula: VO1 = (R1 + R2)/R1 x VFB1 The negative output voltage range is -8.0 V minimum up to a maximum of -2.0 V. It is obtained connecting FB2 to VREF through R3 and FB2 to PGND through R4 (see application circuit). The value of negative output can be calculated using the following formula: VO2 = (R4/R3) x VREF 5.2 Under voltage lockout The device includes an under voltage lockout circuit. When the STOD1412 is enabled (EN pin is pulled high), the device will be OFF until the input voltage reaches the 2.55 V threshold. The UVLO circuit has a hysteresis of 50 mV, so once the device is on, it will keep working until VCC voltage falls below 2.50 V. 5.3 Enable This function allows switching ON and OFF the device using a logic level signal. If the EN pin is pulled high the device turns ON, given that the input voltage is higher than the under voltage lockout threshold. Pulling the EN pin low turns off the device regardless of the UVLO state. In this condition the current consumption is reduced to lower than 1 µA 5.4 Load disconnect When the device is turned OFF, there is no path for the current to flow from the input power supply to the load. In the device there are two switches that allow complete disconnection of the load. This function is useful to improve battery life when the device is not in operation. 5.5 Soft start and inrush current The device includes a soft start feature to limit inrush current when the device is turned on. This function is added to minimize battery loading at start-up. 5.6 Current limit The step-up and inverter converters include peak current limit circuitry. The inductor peak current cannot exceed 900mA for the step-up stage and 1A for the inverting stage. 10/21 STOD1412 Introduction 5.7 External components 5.7.1 Inductor The 1.3 MHz frequency allows the use of small inductors for both converters. In typical applications, a 4.7 µH and a 6.8 µH are recommended for step-up and inverting respectively. Larger values of inductor reduce the ripple inductor current. The inductor's current saturation rating must exceed the peak current. 5.7.2 Capacitors In order to reduce the ripple voltage on the outputs it is recommended to use capacitors with low equivalent series resistance (ESR) on output filters. The interaction between the ESR value of the capacitor and peak inductor current determines the amplitude of the ripple on the output voltage. The suggested value for output capacitors is 4.7 µF. In order to filter the input voltage variations, a ceramic capacitor must be connected between VCC and PGND. A minimum value of 2.2 µF is recommended. This value may be increased to further reduce the noise coming from input power supply. A 100 nF to 1 µF capacitor on the VREF pin is also recommended. 5.7.3 PCB Layout Board layout is important due to high current levels and high switching frequency that could radiate noise. It is important to connect the signal GND pin, the input and output capacitor ground leads and power ground to a single connection point to obtain a star ground configuration. This minimizes ground noise and improves regulation. It is useful to minimize lead lengths in order to reduce stray capacitance, trace resistance to avoid voltage drops and noise irradiation, especially to the feedback circuit, ground circuit and LX_ traces. Place feedback resistors close to their respective feedback pins. Place input capacitors as close as possible to VCC and PGND. Figure 4. Star ground plane 11/21 Typical application STOD1412 6 Typical application Figure 5. Typical application circuit Table 6. External components (see Figure 5.) Symbol Parameter Min Typ. Max Unit L1 Inductor 4.7 µH L2 Inductor 6.8 µH CI Ceramic capacitor SMD 2.2 µF C3 Ceramic capacitor SMD – OPTIONAL 1 µF C01,2 Ceramic capacitor SMD 4.7 µF CFb Ceramic capacitor SMD 22 nF CREF Ceramic capacitor SMD 1 µF R1 Feedback resistors 470 kΩ R2 Feedback resistors 166 kΩ R3 Feedback resistor 533 kΩ R4 Feedback resistor 100 kΩ 12/21 STOD1412 Typical performance characteristics 7 Typical performance characteristics Figure 6. System efficiency vs. output current Figure 7. IPK current step-up vs. input voltage Figure 8. IPK current inverting vs. input voltage Figure 9. Voltage reference vs. temperature Figure 10. VFB1 on step-up vs. temperature Figure 11. Line VFB1 on step-up vs. temperature 13/21 Typical performance characteristics STOD1412 Figure 12. VFB2 on inverting vs. temperature Figure 13. Line VFB2 on inverting vs. temperature Figure 14. Load transient response (step-up) Figure 15. Line transient response VIN=3.7V, IOUT=3mA to 30mA, TRISE=TFALL=30µs, T=25°C VIN=3V to 3.5V, IOUT1,2 = 120mA, TRISE=TFALL=50µs, T=25°C Figure 16. Start-up voltage VIN=0V to 2.5V, T=25°C 14/21 STOD1412 8 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 15/21 Package mechanical data STOD1412 Figure 17. QFN16L package outline 7997239/A 16/21 STOD1412 Table 7. Package mechanical data QFN16L mechanical data mm. inch. Dim. Min. Typ. Max. Min. Typ. Max. A 0.70 0.75 0.80 0.028 0.030 0.031 A1 0 0.02 0.05 0 0.001 0.002 A3 0.20 0.008 b 0.18 0.25 0.30 0.007 0.010 0.012 D 2.90 3 3.10 0.114 0.118 0.122 D2 1.50 1.70 1.80 0.059 0.067 0.071 E 2.90 3 3.10 0.114 0.118 0.122 E2 1.50 1.70 1.80 0.059 0.067 0.071 e L (1) 0.50 0.30 0.40 0.020 0.50 0.012 0.016 0.020 1. The value of "L" a JEDEC norm is MIN 0.35 - MAX 0.45. 17/21 Package mechanical data STOD1412 Tape & reel QFNxx/DFNxx (3x3) mechanical data mm. inch. Dim. Min. Typ. A Min. Typ. 180 13.2 Max. 7.087 C 12.8 D 20.2 0.795 N 60 2.362 T 18/21 Max. 0.504 0.519 14.4 0.567 Ao 3.3 0.130 Bo 3.3 0.130 Ko 1.1 0.043 Po 4 0.157 P 8 0.315 STOD1412 Package mechanical data Figure 18. QFN16L footprint - recommended data 19/21 Revision history STOD1412 9 Revision history Table 8. Document revision history Date Revision 31-Aug-2007 1 20/21 Changes Initial release. STOD1412 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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