STMICROELECTRONICS STS7PF30L_07

STS7PF30L
P-CHANNEL 30V - 0.16Ω - 7A - SO-8
STripFET™ II Power MOSFET
General features
Type
VDSS
RDS(on)
ID
STS7PF30L
30V
<0.021Ω
7A
■
STANDARD OUTLINE FOR EASY
AUTOMATED SURFACE MOUNT
ASSEMBLY
■
LOW THRESHOLD DRIVE
SO-8
Description
This Power MOSFET is the latest development of
STMicroelectronics’ unique “Single Feature
Size™” strip-based process. The resulting
transistor shows extremely high packing densisty
for low on-resistance, rugged avalanche
characteristics and less critical alignment steps,
therefore
a
remarkable
manufacturing
reproducibility.
Internal schematic diagram
Applications
■
BATTERY MANAGEMENT IN NOMADIC
EQUIPMENT.
■
BATTERY MANAGEMENT IN NOMADIC
EQUIPMENT
Order Codes
Sales Type
Marking
Package
Packaging
STS7PF30L
S7PF30L
SO-8
TAPE & REEL
November 2005
Rev 5
1/11
www.st.com
11
STS7PF30L
1 Electrical ratings
1
Electrical ratings
Table 1.
Absolute maximum ratings
Symbol
VDS
VDGR
VGS
Value
Unit
Drain-Source Voltage (VGS = 0)
30
V
Drain-gate Voltage (RGS = 20kΩ)
30
V
± 20
V
Gate-Source Voltage
ID
Drain Current (continuous) at TC = 25°C
7
A
ID
Drain Current (continuous) at TC = 100°C
4.4
A
Drain Current (pulsed)
28
A
Total Dissipation at TC = 25°C
2.5
W
50
°C/W
150
-55 to 150
°C
°C
IDM Note 1
PTOT
Table 2.
Rthj-amb
Note 2
Tj
Tstg
2/11
Parameter
Thermal data
Thermal Resistance Junction-ambient
Operating Junction Temperature
Storage Temperature Range
STS7PF30L
2
2 Electrical characteristics
Electrical characteristics
(TJ = 25 °C unless otherwise specified)
Table 3.
On/off states
Symbol
Parameter
Test Conditions
V(BR)DSS
Drain-Source Breakdown
Voltage
IDSS
Zero Gate Voltage Drain
Current (VGS = 0)
IGSS
Gate Body Leakage Current
(VDS = 0)
VDS = ± 16V
VGS(th)
Gate Threshold Voltage
VDS= VGS, ID = 250µA
RDS(on)
Static Drain-Source On
Resistance
VGS= 10 V, ID= 3.5A
Table 4.
Symbol
gfs Note 3
Ciss
Coss
Crss
Qg
Qgs
Qgd
Table 5.
Symbol
td(on)
tr
td(off)
tf
ID = 250µA, V GS= 0
Min.
Typ.
30
Unit
V
VDS = Max Rating,
VDS = Max Rating, Tc=125°C
VGS= 4.5 V, ID = 3.5A
Max.
1
10
µA
µA
±100
nA
1
1.6
2.5
V
0.011
0.016
0.016
0.022
0.021
0.028
Ω
Ω
Min.
Typ.
Max.
Unit
Dynamic
Parameter
Forward Transconductance
Test Conditions
VDS = 20V, ID= 3.5A
16
S
Input Capacitance
VDS = 25V, f = 1MHz, V GS =0
Output Capacitance
Reverse Transfer Capacitance
2600
523
174
pF
pF
pF
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
28
8.75
12.35
7
nC
nC
nC
Typ.
Max.
Unit
VDD= 15V, ID= 7A,
VGS= 4.5V
Switching times
Parameter
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Test Conditions
VDD = 15V, ID = 3.5A
RG= 4.7Ω, VGS= 4.5V,
(see Figure 13)
VDD = 15V, ID = 3.5A
RG= 4.7Ω, VGS= 4.5V,
(see Figure 13)
Min.
68
54
ns
ns
65
23
ns
ns
3/11
STS7PF30L
2 Electrical characteristics
Table 6.
Source-Drain Diode
Symbol
Parameter
Test Conditions
Min.
Typ.
ISD
Source-Drain Current
ISDM Note 1 Source-Drain Current (pulsed)
VSD
trr
Qrr
IRRM
Forward On Voltage
ISD = 7A, V GS = 0
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD = 7A, di/dt = 100A/µs
VDD = 15V, Tj = 150°C
(see Figure 15)
Max.
Unit
7
28
A
A
1.2
V
40
46
2.3
(1) Pulse with limited by safe operating area
(2) When mounted on 1inch² FR-4 board (t
≤
10µs)
(3) Pulsed: pulse duration = 300µs, duty cycle 1.5%
Note:
4/11
For the P-CHANNEL MOSFET the polarity of voltages and current have to be reversed
ns
nC
A
STS7PF30L
2.1
2 Electrical characteristics
Electrical characteristics (curves)
Figure 1.
Safe Operating Area
Figure 2.
Thermal Impedance
Figure 3.
Output Characteristics
Figure 4.
Transfer Characteristics
Figure 5.
Transconductance
Figure 6.
Static Drain-Source on Resistance
5/11
STS7PF30L
2 Electrical characteristics
Figure 7.
Gate Charge vs Gate-Source Voltage Figure 8.
Figure 9.
Normalized Gate Threshold Voltage Figure 10. Normalized on Resistance vs
vs Temperature
Temperature
Figure 11. Source-Drain Diode Forward
Characteristics
6/11
Capacitance Variations
Figure 12. Normalized Breakdown Voltage vs
Temperature
STS7PF30L
3
3 Test Circuits
Test Circuits
Figure 13. Switching Times Test Circuit For
Resistive Load
Figure 14. Gate Charge Test Circuit
Figure 15. Test Circuit For Inductive Load
Switching and Diode Recovery
Times
7/11
4 Package Mechanical Data
4
STS7PF30L
Package Mechanical Data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in compliance
with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are
available at: www.st.com
8/11
STS7PF30L
4 Package Mechanical Data
SO-8 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
A
a1
inch
MAX.
MIN.
TYP.
1.75
0.1
0.068
0.25
a2
MAX.
0.003
0.009
1.65
0.064
a3
0.65
0.85
0.025
0.033
b
0.35
0.48
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.25
0.5
0.010
0.019
D
4.8
5.0
0.188
0.196
E
5.8
6.2
0.228
c1
45 (typ.)
1.27
e
e3
3.81
0.150
F
3.8
4.0
0.14
L
0.4
1.27
0.015
M
S
0.244
0.050
0.6
0.157
0.050
0.023
8 (max.)
9/11
STS7PF30L
5 Revision History
5
10/11
Revision History
Date
Revision
Changes
13-Dec-2003
1
First Issue
25-Jun-2004
2
Preliminary Data
18-Jan-2005
3
Modified value on table 5
29-Sep-2005
4
Complete version
09-Nov-2005
5
New template
STS7PF30L
5 Revision History
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by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
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11/11