TS507 High precision rail-to-rail operational amplifier Features ■ Ultra low offset voltage: 25 µV typ, 100 µV max ■ Rail-to-rail input/output voltage swing ■ Operating from 2.7 V to 5.5 V ■ High speed: 1.9 MHz ■ 45° phase margin with 100 pF ■ Low consumption: 0.8 mA at 2.7 V ■ Very large signal voltage gain: 131 dB ■ High power supply rejection ratio: 105 dB ■ Very high ESD protection 5kV (HBM) ■ Latch-up immunity ■ Available in SOT23-5 micropackage Pin connections (top view) SOT23-5 Output 1 VDD 2 Non Inverting Input 3 5 VCC 4 Inverting Input SO-8 Applications ■ Battery-powered applications ■ Portable devices ■ Signal conditioning ■ Medical instrumentation N.C. 1 Inverting Input 2 Non Inverting Input 3 VDD 4 8 N.C. _ 7 VCC + 6 Output 5 N.C. Description The TS507 is a high performance rail-to-rail input and output amplifier with very low offset voltage. This amplifier uses a new trimming technique that yields ultra low offset voltages without any need for external zeroing. The circuit offers very stable electrical characteristics over the entire supply voltage range, and is particularly intended for automotive and industrial applications. The TS507 is housed in the space-saving 5-pin SOT23 package, making it well suited for batterypowered systems. This micropackage simplifies the PC board design because of its ability to be placed in tight spaces (external dimensions are 2.8 mm x 2.9 mm). April 2008 Rev 5 1/20 www.st.com 20 Contents TS507 Contents 1 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Application note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 3.1 Out-of-the-loop compensation technique . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 In-the-loop-compensation technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 SOT23-5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 SO-8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/20 TS507 1 Absolute maximum ratings and operating conditions Absolute maximum ratings and operating conditions Table 1. Absolute maximum ratings (AMR) Symbol VCC Vid Parameter Supply voltage (1) Differential input voltage (2) (3) Vin Input voltage Tstg Storage temperature Value Unit 6 V ±2.5 V VDD-0.3 to VCC+0.3 V -65 to +150 °C 250 125 °C/W (4) (5) Rthja Thermal resistance junction to ambient SOT23-5 SO-8 Rthjc Thermal resistance junction to case SOT23-5 SO-8 81 40 °C/W Maximum junction temperature 150 °C 5 kV 300 V 2 kV Tj HBM: human body model(6) ESD (7) MM: machine model CDM: charged device model (8) Latch-up immunity class A 1. Value with respect to VDD pin. 2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. 3. VCC-Vin must not exceed 6V and Vin must not exceed 6V. 4. Short-circuits can cause excessive heating and destructive dissipation. 5. Rthja/c are typical values. 6. Human body model: A 100 pF capacitor is charged to the specified voltage, then discharged through a 1.5 kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations while the other pins are floating. 7. Machine model: A 200 pF capacitor is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 Ω). This is done for all couples of connected pin combinations while the other pins are floating. 8. Charged device model: all pins and the package are charged together to the specified voltage and then discharged directly to the ground through only one pin. This is done for all pins. Table 2. Operating conditions Symbol Parameter VCC Supply voltage(1) Vicm Common mode input voltage range Vid Toper Differential input voltage(2) Operating free air temperature range TS507C TS507I Value Unit 2.7 to 5.5 V VDD to VCC V ±2.5 V 0 to +85 -40 to +125 °C 1. Value with respect to VDD pin. 2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. 3/20 Electrical characteristics TS507 2 Electrical characteristics Table 3. Electrical characteristics at VCC = +5V, VDD = 0V, Vicm = VCC/2, Tamb = 25°C, RL connected to VCC/2 (unless otherwise specified)(1) Symbol Parameter Conditions Min. Typ. Max. Unit 25 100 250 400 µV 450 550 750 µV DC performance Vio ΔVio/Δt Input offset voltage(2) Vicm = 0 to 3.8V, T=25°C TS507C full temp range TS507I full temp range Vicm = 0V to 5V, T=25°C TS507C full temp range TS507I full temp range Vio drift vs. temperature Tmin < Top < Tmax 1 Input bias current T = 25°C TS507C full temp range TS507I full temp range 8 Iib Input offset current T = 25°C TS507C full temp range TS507I full temp range 2 Iio CMRR Common mode rejection ratio 20 log (ΔVicm/ΔVio) Vicm from 0V to 3.8V, T=25°C TS507C full temp range TS507I full temp range 94 94 91 Vicm from 0V to 5V PSRR Avd VOL 4/20 nA 25 35 50 nA dB 96 VCC from 2.7V to 5.5V, Vicm=vcc/2, T=25°C TS507C full temp range TS507I full temp range 91 90 89 105 Large signal voltage gain RL = 10kΩ, Vout= 0.5V to 4.5V Full temp range 99 98 131 Low level output voltage 70 75 110 115 Power supply rejection ratio 20 log (ΔVCC/ΔVio) VCC-VOH High level output voltage drop µV/°C dB dB RL = 600Ω, T=25°C TS507C full temp range TS507I full temp range 67 RL = 10kΩ, T=25°C Full Temp range 4 15 15 RL = 600Ω, T=25°C TS507C full temp range TS507I full temp range 64 90 110 125 RL = 10kΩ, T=25°C Full temp range 4 95 110 120 15 15 mV mV TS507 Table 3. Electrical characteristics Electrical characteristics at VCC = +5V, VDD = 0V, Vicm = VCC/2, Tamb = 25°C, RL connected to VCC/2 (unless otherwise specified)(1) (continued) Symbol Parameter Min. Typ. 74 60 53 104 Isink Vout = VCC, Vid=-1V, T=25°C TS507C full temp range TS507I full temp range 90 77 70 128 Isource Vout = VDD, Vid=1V, T=25°C TS507C full temp range TS507I full temp range Supply current (per operator)(2) No load, Vout=VCC/2, Vicm=0 to 5V, T=25°C Full temp range 0.85 Gain bandwidth product RL = 2kΩ, CL = 100pF, f = 100kHz 1.9 MHz φm Phase margin RL = 2kΩ, CL=100pF 45 Degrees Gm Gain margin RL = 2kΩ, CL=100pF 10 dB SR Slew rate RL = 2kΩ, CL=100pF, Vout = 1.25V to 3.75V, 10% to 90% 0.6 V/µs eN Equivalent input noise voltage f = 1kHz 12 nV/√Hz iN Equivalent input noise current f = 10kHz 1.2 pA/√Hz 0.0003 % Iout ICC Conditions Max. Unit mA 1.15 1.25 mA Dynamic performance GBP THD+eN THD + noise f=1kHz, G=1, RL=2kΩ, Vicm=2V, Vout=3.5Vpp 1. All parameter limits at temperatures different from 25° C are guaranteed by correlation. 2. Measurements done at 4 Vicm values: Vicm=0 V, Vicm=3.8 V, Vicm=4.2 V, Vicm=5 V. 5/20 Electrical characteristics Table 4. TS507 Electrical characteristics at VCC = +3.3V, VDD = 0V, Vicm = VCC/2, Tamb = 25°C, RL connected to VCC/2 (unless otherwise specified)(1) Symbol Parameter Conditions Min. Typ. Max. Unit 25 100 250 400 µV 450 550 750 µV DC performance Vio ΔVio Input offset voltage(2) Vicm = 0V to 3.3V, T=25°C TS507C full temp range TS507I full temp range Vio drift vs. temperature Tmin < Top < Tmax 1 Input bias current T = 25°C TS507C full temp range TS507I full temp range 6 Iib Input offset current T = 25°C TS507C full temp range TS507I full temp range 2 Iio Common mode rejection ratio 20 log (ΔVicm/ΔVio) Vicm from 0V to 2.1V 115 dB Large signal voltage gain RL = 10kΩ, Vout= 0.5V to 2.8V 127 dB RL = 600Ω, T=25°C TS507C full temp range TS507I full temp range 59 RL = 10kΩ, T=25°C Full temp range 4 15 15 RL = 600Ω, T=25°C TS507C full temp range TS507I full temp range 57 80 100 115 RL = 10kΩ, T=25°C Full temp range 4 CMRR Avd VCC-VOH High level output voltage drop VOL Low level output voltage Vout = VCC, Vid=-1V, T=25°C TS507C full temp range TS507I full temp range 33 26 22 48 Isink 37 32 29 56 Isource Vout = VDD, Vid=1V, T=25°C TS507C full temp range TS507I full temp range Supply current (per operator)(2) No load, Vout=VCC/2, Vicm=0 to 3.3V, T=25°C Full temp range Iout ICC 6/20 Vicm = 0 to 2.1V, T=25°C TS507C full temp range TS507I full temp range µV/°C 70 75 145 nA 25 40 45 nA 85 100 110 mV mV 15 15 mA 0.81 1.1 1.2 mA TS507 Table 4. Electrical characteristics Electrical characteristics at VCC = +3.3V, VDD = 0V, Vicm = VCC/2, Tamb = 25°C, RL connected to VCC/2 (unless otherwise specified)(1) (continued) Symbol Parameter Conditions Min. Typ. Max. Unit Dynamic performance Gain bandwidth product RL = 2kΩ, CL = 100pF, f = 100kHz 1.9 MHz φm Phase margin RL = 2kΩ, CL=100pF 45 Degrees Gm Gain margin RL = 2kΩ, CL=100pF 10 dB SR Slew rate RL = 2kΩ, CL=100pF, Vout= 0.5V to 2.8V, 10% to 90% 0.6 V/µs eN Equivalent input noise voltage f = 1kHz 12 nV/√Hz 0.0004 % GBP THD+eN THD + noise f=1KHz, G=1, RL=2kΩ, Vicm=1.15V, Vout=1.8Vpp 1. All parameter limits at temperatures different from 25° C are guaranteed by correlation. 2. Measurements done at 4 Vicm values: Vicm=0 V, Vicm=2.1 V, Vicm=2.5 V, Vicm=3.3 V. 7/20 Electrical characteristics Table 5. TS507 Electrical characteristics at VCC = +2.7V VDD = 0V, Vicm = VCC/2, Tamb = 25°C, RL connected to VCC/2 (unless otherwise specified)(1) Symbol Parameter Conditions Min. Typ. Max. Unit 25 100 250 400 µV 450 550 750 µV DC performance Vio ΔVio Input offset voltage(2) Vicm = 0V to 2.7V, T=25°C TS507C full temp range TS507I full temp range Vio drift vs. temperature Tmin < Top < Tmax 1 Input bias current T = 25°C TS507C full temp range TS507I full temp range 8 Iib Input offset current T = 25°C TS507C full temp range TS507I full temp range 2 Iio Common mode rejection ratio 20 log (ΔVicm/ΔVio) Vicm from 0V to 1.5V 115 dB Large signal voltage gain RL = 10kΩ, Vout= 0.5V to 2.2V 126 dB RL = 600Ω, T=25°C TS507C full temp range TS507I full temp range 57 RL = 10kΩ, T=25°C Full temp range 4 15 15 RL = 600Ω, T=25°C TS507C full temp range TS507I full temp range 57 80 100 115 RL = 10kΩ, T=25°C Full temp range 4 CMRR Avd VCC-VOH High level output voltage drop VOL Low level output voltage Vout = VCC, Vid=-1V, T=25°C TS507C full temp range TS507I full temp range 20 15 13 30 Isink 22 19 17 35 Isource Vout = VDD, Vid=1V, T=25°C TS507C full temp range TS507I full temp range Supply current (per operator)(2) No load, Vout=VCC/2, Vicm=0 to 2.7V, T=25°C Full temp range Iout ICC 8/20 Vicm = 0 to 1.9V, T=25°C TS507C full temp range TS507I full temp range µV/°C 70 75 160 nA 25 45 45 nA 85 100 105 mV mV 15 15 mA 0.79 1.1 1.2 mA TS507 Table 5. Electrical characteristics Electrical characteristics at VCC = +2.7V VDD = 0V, Vicm = VCC/2, Tamb = 25°C, RL connected to VCC/2 (unless otherwise specified)(1) (continued) Symbol Parameter Conditions Min. Typ. Max. Unit Dynamic performance Gain bandwidth product RL = 2kΩ, CL = 100pF, f = 100kHz 1.9 MHz φm Phase margin RL = 2kΩ, CL=100pF 45 Degrees Gm Gain margin RL = 2kΩ, CL=100pF 11 dB SR Slew rate RL = 2kΩ, CL=100pF, Vout= 0.5V to 2.2V, 10% to 90% 0.6 V/µs eN Equivalent input noise voltage f = 1kHz 12 nV/√Hz 0.0005 % GBP THD+eN THD + noise f=1KHz, G=1, RL=2kΩ, Vicm=0.85V, Vout=1.2Vpp 1. All parameter limits at temperatures different from 25° C are guaranteed by correlation. 2. Measurements done at 4 Vicm values: Vicm=0 V, Vicm=1.5 V, Vicm=1.9 V, Vicm=2.7 V. 9/20 Electrical characteristics Figure 1. TS507 Input offset voltage distribution for Figure 2. Vicm≤ VCC-1.2V at T=25°C 30 Input offset voltage distribution vs. temperature for Vicm≤ VCC-1.2V 400 350 300 Vio distribution at T=25°C for 0V<=Vicm<=Vcc-1.2V 25 0V<=Vicm<=Vcc-1.2V 250 200 150 100 Vio (µV) Population % 20 15 10 50 0 -50 -100 -150 -200 -250 5 -300 -350 0 -120 -400 -100 -80 -60 -40 -20 0 20 40 60 80 100 -50 -40 -30 -20 -10 120 0 Temperature (°C) Input offset voltage (µV) Figure 3. 10 20 30 40 50 60 70 80 90 100 110 120 130 Input offset voltage distribution vs. Figure 4. temperature for Vicm ≥ VCC-0.8V Input offset voltage distribution for Vicm ≤ VCC-1.2V at T=25°C after HTB 45 700 Vio distribution at T=25°C for 0V<=Vicm<=Vcc-1.2V after HTB (1000 hours at 125°C) 600 40 Vcc-0.8V<=Vicm<=Vcc 500 400 35 300 30 Population % Vio (µV) 200 100 0 -100 -200 -300 25 20 15 -400 10 -500 -600 5 -700 -50 -40 -30 -20 -10 0 0 -100 10 20 30 40 50 60 70 80 90 100 110 120 130 -80 -60 Temperature (°C) Figure 5. -40 -20 0 20 40 60 80 100 Input offset voltage (µV) Input offset voltage distribution for Figure 6. Vicm ≤ VCC-1.2V at T=25°C after THB Input offset voltage vs. input common mode voltage at T=25°C 40 35 Vcc=3.3V Population % 25 20 15 10 5 0 -120 0 -20 Vcc=5.5V Vcc=5V -40 -60 -80 -100 -80 -60 -40 -20 0 20 40 Input offset voltage (µV) 10/20 Vcc=2.7V 20 Vio distribution at T=25°C for 0V<=Vicm<=Vcc-1.2V after THB (1000 hours at 85°C, humidity 85%) Input Offset Voltage (μV) 30 60 80 100 120 -100 -2.5 -2.0 -1.5 -1.0 Vicm-Vcc (V) -0.5 0.0 TS507 Electrical characteristics Figure 7. Supply current vs. input common mode voltage in closed loop configuration at VCC=5V Figure 8. Supply current vs. supply voltage at Vicm=VCC/2 1.0 1.0 0.8 0.8 0.7 T=25°C Supply Current (mA) Supply Current (mA) T=125°C T=125°C T=-40°C 0.5 0.3 Vcc=5V Closed loop 0.7 T=25°C 0.5 T=-40°C 0.3 0.2 0.2 0.0 0.0 Vicm=Vcc/2 0 Figure 9. 1 2 3 4 Input common mode voltage (V) 5 Supply current vs. input common mode voltage in follower configuration at VCC=2.7V 0 1 2 3 Supply voltage (V) 4 5 Figure 10. Supply current vs. input common mode voltage in follower configuration at VCC=5V 1.0 1.0 T=125°C 0.8 T=25°C 0.7 0.5 Supply Current (mA) Supply Current (mA) 0.8 T=-40°C 0.3 Follower configuration Vcc=2.7V 0.2 0.7 T=125°C 0.5 0.3 Follower configuration Vcc=5V 0.2 0.0 0.0 T=25°C T=-40°C 0.0 0.5 1.0 1.5 2.0 Input Common Mode Voltage (V) 2.5 0 1 2 3 4 Input Common Mode Voltage (V) 5 Figure 11. Output current vs. supply voltage at Figure 12. Output current vs. output voltage at Vicm=VCC/2 VCC=2.7V 150 100 Output Current (mA) 75 Source Vid = 1V T=125°C T=-40°C T=25°C Output Current (mA) 125 50 25 Vicm=Vcc/2 0 -25 -50 -75 -100 -125 T=125°C Sink Vid = -1V T=25°C T=-40°C -150 3.0 3.5 4.0 4.5 Supply voltage (V) 5.0 5.5 40 T=-40°C 35 30 Source 25 Vid=1V 20 T=25°C 15 T=125°C 10 5 0 Vcc=2.7V -5 -10 T=125°C -15 T=25°C -20 Sink -25 -30 Vid=-1V -35 T=-40°C -40 0.0 0.5 1.0 1.5 2.0 2.5 Output Voltage (V) 11/20 Electrical characteristics TS507 Figure 13. Output current vs. output voltage at Figure 14. Positive and negative slew rate vs. VCC=5V supply voltage T=25°C 125 Source Vid=1V 100 T=-40°C Output Current (mA) 75 50 Positive and Negative Slew Rate (V/µs) 150 T=125°C 25 Vcc=5V 0 -25 T=125°C -50 -75 -100 -125 -150 0.0 Sink Vid=-1V T=-40°C 1.0 T=25°C 2.0 3.0 Output Voltage (V) 4.0 1.0 0.6 0.4 T=-40°C 0.2 Vin : from 0.5V to Vcc-0.5V SR : calculated from 10% to 90% 0.0 T=25°C T=-40°C -0.2 T=25°C -0.4 -0.6 -0.8 T=125°C Negative slew rate -1.0 2.0 5.0 T=125°C Positive slew rate 0.8 2.5 3.0 3.5 4.0 4.5 Supply Voltage (V) 5.0 5.5 6.0 Figure 15. Voltage gain and phase vs. Figure 16. Voltage gain and phase vs. frequency at VCC=5V and Vicm=2.5V frequency at VCC=5V and Vicm=2.5V at T=25°C at T=-40°C 40 Phase 180 50 180 150 40 150 120 30 120 30 90 Cl=230pF 30 Gain 0 0 -30 -10 -20 -30 -60 Vcc=5V, Vicm=2.5V, G= -100 Rl=2kOhms, Vrl=Vcc/2 Tamb=25°C 10 5 10 6 60 10 30 Phase 0 10 -30 -60 -20 -90 Vcc=5V, Vicm=2.5V, G= -100 Rl=2kOhms, Cl=100pF, Vrl=Vcc/2 Tamb=-40°C -30 -120 7 0 Gain -10 -90 -40 -50 4 10 Gain (dB) Gain (dB) 10 90 20 60 Phase (°) Cl=100pF 20 Phase (°) 50 -150 -40 -180 -50 4 10 10 Frequency (Hz) 5 10 -120 -150 6 10 7 -180 Frequency (Hz) Figure 17. Voltage gain and phase vs. Figure 18. Closed loop gain in voltage follower frequency at VCC=5V and Vicm=2.5V configuration for different at T=125°C capacitive load at T=25°C 50 180 40 150 20 120 30 10 90 60 30 Phase 0 0 -30 Gain -10 -60 -20 -30 -40 -50 4 10 10 10 6 Frequency (Hz) 12/20 G ain without C L -10 G ain with C L =300 pF -20 -90 Vcc=5V, Vicm=2.5V, G= -100 Rl=2kOhms, Cl=100pF, Vrl=Vcc/2 Tamb=125°C 5 0 Gain (dB) 10 Phase (°) Gain (dB) 20 TS507 : V cc = 5 V V icm = 2,5 V T = 25 °C R L = 10 k Ω -120 G ain with C L =550 pF -30 -150 10 7 -180 -40 10k 100k 1M Frequency (H z) 10M TS507 Electrical characteristics Figure 19. Gain margin according the output load, at VCC=5V and T=25°C Figure 20. Phase margin according the output load, at VCC=5V and T=25°C 1E-6 1E-6 V cc = 5 V V icm = 2,5 V T amb = 25 °C 1E-7 Load Capacitor (F) Load Capacitor (F) 1E-7 UNSTABLE 1E-8 1E-9 0 dB 1E-10 10 dB 1E-11 30 dB 20 dB V cc = 5 V V icm = 2,5 V T amb = 25 °C UNSTABLE 0° 1E-8 10 ° 1E-9 20 ° 1E-10 30 ° 1E-11 40 ° STABLE 1E-12 1E-12 1 10 100 1k 10k 100k 1M 1 10M 10 100 Figure 21. Gain margin vs. output current, at VCC=5V and T=25°C 10k 100k 1M 10M Figure 22. Phase margin vs. output current, at VCC=5V and T=25°C 20.0 70 17.5 R ecom m ended area 50 Phase Margin (°) 100 pF 12.5 10.0 300 pF 7.5 550 pF 5.0 V cc = 5 V V icm = 2,5 V T am b = 25 °C RL = 2 kΩ 2.5 0.0 -3 -2 -1 0 1 2 3 5 50 pF 30 20 V cc = 5 V V icm = 2,5 V T am b = 2 5 °C R L = 2 kΩ 0 -1 0 4 -4 -3 O utput Current (m A) 10 25 0 0 -10 -25 Gain Margin -20 -50 0.0100 2 3 4 Vcc=3.3V Vcc=2.7V f=1kHz Rl=2kO hm s G ain=1 BW =22kHz Vicm =(Vcc-1V)/2 0.0010 Phase Margin -75 Load Capacitor (F) 1 Vcc=5V THD + N (%) 20 1n 0 0.1000 Phase (°) 75 Vcc = 5 V Vicm = 2,5 V 50 Tamb = 25 °C RL = 2 k Ω 100p -1 Figure 24. Distortion + noise vs. output voltage 30 -40 10p -2 O utput C urrent (m A) Figure 23. Phase and gain margins vs capacitive load at = 25°C -30 30 0 pF 10 0 pF 40 10 -2.5 -4 R ecom m e nded a rea 60 15.0 Gain Margin (dB) 1k Load Resistor ( Ω ) Load Resistor ( Ω ) Gain (dB) STABLE 50 ° -100 10n 0.0001 0.01 0.1 1 Output Voltage (Vpp) 13/20 Electrical characteristics TS507 Figure 25. Distortion + noise vs. frequency Figure 26. Noise vs. frequency 1000 Vout=Vcc-1.5Vpp Rl=2kO hm s G ain=1 BW =80kHz Vicm =(Vcc-1V)/2 Vcc=2.7V 1E-3 Vcc=3.3V Vcc=5V 1E-4 10 14/20 Input equivalent noise density (nV/VHz) THD + N (%) 0.01 100 10 Vcc=5V, Vicm=2.5V, Tamb=25°C 1 100 1000 Frequency (Hz) 10000 1 10 100 Frequency (Hz) 1000 10000 TS507 Application note 3 Application note An application note, based on the TS507, describes three compensation techniques for solving stability issues when driving large capacitive loads. Two of them are briefly explained here. For more details, refer to the application note on www.st.com. To find it, do a keyword search for AN2653. 3.1 Out-of-the-loop compensation technique The first technique, named the out-of-the-loop compensation, uses an isolation resistor, ROL, added in series between the output of the amplifier and its load (see Figure 27). The resistor isolates the op-amp feedback network from the capacitive load. This compensation method is effective, but the drawback is a limitation on the accuracy of Vout depending on the resistive load value. Figure 27. Out-of-the-loop compensation schematics To help implement the compensation, the abacus given in Figure 28 to Figure 29 provide the ROL value to choose for a given CL and phase/gain margins. These abacus are plotted in the case of a voltage follower configuration with a load resistor of 10 kΩ at 25°C. Figure 28. Gain margin abacus : serial resistor Figure 29. Phase margin abacus : serial to be added in a voltage follower resistor to be added in a voltage configuration at 25°C follower configuration at 25°C 100 100 STAB LE 8 dB 0 dB 4 dB 12 dB 1 16 dB Compensation Resistor ROL 10 U NSTAB LE 0 .1 0 .0 1 10p 100p 1n 10n 100n L o ad C ap a cito r (F ) V cc = 5 V V ic m = 2 ,5 V T = 2 5 °C RL = 10 kΩ 1µ 10µ Compensation Resistor ROL 30 ° STABLE 20 ° 10 10 ° 1 0 ° U N STAB LE V cc = 5 V V icm = 2 ,5 V T = 2 5 °C R L = 10 kΩ 0 .1 0 .0 1 10p 100p 1n 10n 100n 1µ 10µ L o ad C a p a cito r (F ) 15/20 Application note 3.2 TS507 In-the-loop-compensation technique The second technique is called the in-the-loop-compensation technique, because the additional components (a resistor and a capacitor) used to improve the stability are inserted in the feedback loop (see Figure 30). Figure 30. In-the-loop compensation schematics This compensation method allows, by a good choice of compensation components, to compensate the original pole (caused by the capacitive load), and thus to improve stability. The main drawback of this circuit is the reduction of the output swing, because the isolation resistor is in the signal path. Table 6 helps you to choose the best compensation components for different ranges of load capacitors (and with RL = 10 kΩ) in voltage follower configuration. Table 6. Best compensation components for different load capacitor ranges in voltage follower configuration for TS507 (with RL = 10 kΩ) Load capacitor range RIL (kΩ) CIL (pF) Minimum gain margin (dB)(1) Minimum phase margin (degree)(1) 10 pF to 100 pF 1 250 17 55 100 pF to 1 nF 1 250 16 42 1 nF to 10 nF 1 630 11 27 1. Parameter guaranteed by design at 25°C. 16/20 TS507 4 Package information Package information In order to meet environmental requirements, STMicroelectronics offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an STMicroelectronics trademark. ECOPACK specifications are available at: www.st.com. 4.1 SOT23-5 package information Figure 31. SOT23-5 package mechanical drawing Table 7. SOT23-5 package mechanical data Dimensions Ref. Millimeters Min. Typ. Mils Max. Min. Typ. Max. A 0.90 1.45 35.4 57.1 A1 0.00 0.15 0.00 5.9 A2 0.90 1.30 35.4 51.2 b 0.35 0.50 13.7 19.7 C 0.09 0.20 3.5 7.8 D 2.80 3.00 110.2 118.1 E 2.60 3.00 102.3 118.1 E1 1.50 1.75 59.0 68.8 e 0.95 37.4 e1 1.9 74.8 L 0.35 0.55 13.7 21.6 17/20 Package information 4.2 TS507 SO-8 package Figure 32. SO-8 package mechanical drawing Table 8. SO-8 package mechanical data Dimensions Ref. Millimeters Min. Typ. A Max. Min. Typ. 1.75 0.25 Max. 0.069 A1 0.10 A2 1.25 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.010 D 4.80 4.90 5.00 0.189 0.193 0.197 E 5.80 6.00 6.20 0.228 0.236 0.244 E1 3.80 3.90 4.00 0.150 0.154 0.157 e 0.004 0.010 0.049 1.27 0.050 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 k 1° 8° 1° 8° ccc 18/20 Inches 0.10 0.004 TS507 5 Ordering information Ordering information Table 9. Order codes Temperature range Order code Package TS507ID TS507IDT Packing SO-8 TS507IYD(1) TS507IYDT(1) TS507I -40°C to 125°C SO-8 (Automotive grade) SOT23-5(2) TS507ILT TS507IYLT(1) Tape & reel K137 SO-8 Tube or Tape & reel TS507C SOT23-5(2) Tape & reel K136 0°C to 85°C TS507CLT TS507Y K131 (Automotive grade) TS507CD TS507CDT Tube or Tape & reel Tape & reel SOT23-5(2) -40°C to 125°C Marking 1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 & Q 002 or equivalent are on-going. 2. All information related to the SOT23-5 package is subject to change without notice. 6 Revision history Table 10. Document revision history Date Revision Changes 01-Oct-2004 1 Preliminary data release for product in development. 02-May-2006 2 Update preliminary data release for product in development. 15-Dec-2006 3 First public release. 03-May-2007 4 Automotive grade products added. 08-Apr-2008 5 Electrical characteristics curves for Bode and AC stability added and updated. Application note section added. 19/20 TS507 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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