TSV611, TSV611A, TSV612, TSV612A Rail-to-rail input/output 10 µA, 120 kHz CMOS operational amplifiers Features TSV611ILT - TSV611ICT ■ Rail-to-rail input and output ■ Low power consumption: 10 µA typ at 5 V ■ Low supply voltage: 1.5 to 5.5 V ■ Gain bandwidth product: 120 kHz typ ■ Unity gain stable ■ Low input offset voltage: 800 µV max (A version) VCC- 2 In- 3 ■ Low input bias current: 1 pA typ ■ Temperature range: -40 to +85° C Battery-powered applications ■ Smoke detectors ■ Proximity sensors ■ Portable devices ■ Signal conditioning ■ Active filtering ■ Medical instrumentation +_ 4 Out SOT23-5/SC70-5 Applications ■ 5 VCC+ In+ 1 TSV612IST - TSV612ID/DT Out1 1 In1- 2 _ In1+ 3 + VCC- 4 8 VCC+ 7 Out2 _ 6 In2- + 5 In2+ MiniSO-8/SO-8 Description The TSV61x family of single and dual operational amplifiers offers low voltage, low power operation and rail-to-rail input and output. The devices also feature an ultra-low input bias current as well as a low input offset voltage. The TSV61x have a gain bandwidth product of 120 kHz while consuming only 10 µA at 5 V. These features make the TSV61x family ideal for sensor interfaces, battery supplied and portable applications, as well as active filtering. January 2010 Doc ID 15768 Rev 2 1/19 www.st.com 19 Absolute maximum ratings and operating conditions 1 TSV611, TSV611A, TSV612, TSV612A Absolute maximum ratings and operating conditions Table 1. Absolute maximum ratings Symbol VCC Vid Parameter Supply voltage (1) Differential input voltage (2) (3) Vin Input voltage Tstg Storage temperature Thermal resistance junction to ambient Rthja Tj Unit 6 V ±VCC V VCC- -0.2 to VCC++0.2 V -65 to +150 °C (4)(5) SC70-5 205 SOT23-5 250 MiniSO-8 190 SO-8 125 Maximum junction temperature HBM: human body ESD Value MM: machine model(6) model(7) CDM: charged device model(8) Latch-up immunity °C/W 150 °C 4 kV 200 V 1.5 kV 200 mA 1. All voltage values, except differential voltage are with respect to network ground terminal. 2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. 3. Vcc-Vin must not exceed 6 V. 4. Short-circuits can cause excessive heating and destructive dissipation. 5. Rth are typical values. 6. Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for all couples of pin combinations with other pins floating. 7. Machine model: a 200 pF cap is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 Ω), done for all couples of pin combinations with other pins floating. 8. Charged device model: all pins plus package are charged together to the specified voltage and then discharged directly to ground. Table 2. Operating conditions Symbol 2/19 Parameter VCC Supply voltage Vicm Common mode input voltage range Toper Operating free air temperature range Doc ID 15768 Rev 2 Value Unit 1.5 to 5.5 V VCC- -0.1 to VCC+ +0.1 V -40 to +85 °C TSV611, TSV611A, TSV612, TSV612A 2 Electrical characteristics Electrical characteristics Table 3. Electrical characteristics at VCC+ = +1.8 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25° C, and RL connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit DC performance TSV61x TSV61xA Vio DVio Iio Iib CMR Avd 4 0.8 Offset voltage mV 5 2 Tmin. < Top < Tmax. TSV61x Tmin. < Top < TmaxTSV61xA Input offset voltage drift Input offset current (Vout = Vcc/2) Tmin. < Top < Tmax. Input bias current (Vout = Vcc/2) Tmin. < Top < Tmax. Common mode rejection ratio 20 log (ΔVic/ΔVio) Large signal voltage gain 0 V to 1.8 V, Vout = 0.9 V 55 Tmin. < Top < Tmax. 53 RL = 10 kΩ, Vout = 0.5 V to 1.3 V 78 Tmin. < Top < Tmax. 74 35 50 1 (1) 10 pA 1 100 pA 1 10(1) pA 1 100 pA 71 83 4 RL = 10 kΩ Tmin. < Top < Tmax. VOL Low level output voltage RL = 10 kΩ Tmin. < Top < Tmax. Isink Vo = 1.8 V Tmin. < Top < Tmax. 9 9 13 Isource Vo = 0 V Tmin. < Top < Tmax. 8 8 10 6.5 9 No load, Vout = Vcc/2 Supply current (per operator) Tmin. < Top < Tmax. dB dB High level output voltage ICC dB dB VOH Iout μV/°C 2 7 mV 35 50 mV mA 6 12 µA 12.5 µA AC performance GBP Gain bandwidth product RL = 10 kΩ, CL = 20 pF 100 kHz φm Phase margin RL = 10 kΩ, CL = 20 pF 60 Degrees Gm Gain margin RL = 10 kΩ, CL = 20 pF 9.5 dB SR Slew rate RL = 10 kΩ, CL = 20 pF, Vout = 0.5V to 1.3V 0.03 V/μs Doc ID 15768 Rev 2 3/19 Electrical characteristics Table 3. Symbol en THD+N TSV611, TSV611A, TSV612, TSV612A Electrical characteristics at VCC+ = +1.8 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25° C, and RL connected to VCC/2 (unless otherwise specified) (continued) Parameter Conditions Typ. Max. Unit Equivalent input noise voltage f = 1 kHz 110 nV -----------Hz Total harmonic distortion + noise Fin = 1 kHz, Av = 1, Vout = 1 Vpp, RL = 100 kΩ, BW = 22 kHz 0.07 % 1. Guaranteed by design. 4/19 Min. Doc ID 15768 Rev 2 TSV611, TSV611A, TSV612, TSV612A Table 4. Electrical characteristics VCC+ = +3.3 V, VCC- = 0 V, Vicm = VCC/2, Tamb = 25° C, RL connected to VCC/2 (unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit DC performance TSV61x TSV61xA Vio DVio Iio Iib CMR Avd 4 0.8 Offset voltage mV 5 2 Tmin<Top<Tmax TSV61x Tmin<Top<TmaxTSV61xA Input offset voltage drift 1 10(1) pA 1 100 pA 1 10(1) pA 1 100 pA Input offset current Tmin. < Top < Tmax. Input bias current Tmin. < Top < Tmax. Common mode rejection ratio 20 log (ΔVic/ΔVio) 0 V to 3.3 V, Vout = 1.75 V 61 Tmin. < Top < Tmax. 58 RL = 10 kΩ, Vout = 0.5 V to 2.8 V 85 Large signal voltage gain Tmin. < Top < Tmax. 83 35 50 76 92 5 RL = 10 kΩ Tmin. < Top < Tmax. VOL Low level output voltage RL = 10 kΩ Tmin. < Top < Tmax. Isink Vo = VCC Tmin. < Top < Tmax. 37 35 44 Isource Vo = 0 V Tmin. < Top < Tmax. 32 30 38 No load, Vout = VCC/2 6.5 9.5 Supply current (per operator) Tmin. < Top < Tmax. dB dB High level output voltage Iout dB dB VOH ICC μV/°C 2 10 mV 35 50 mV mA 6 12.5 µA 13 µA AC performance GBP Gain bandwidth product RL = 10 kΩ, CL = 20 pF 110 kHz φm Phase margin RL = 10 kΩ, CL = 20 pF 60 Degrees Gm Gain margin RL = 10 kΩ, CL = 20 pF, 9.5 dB SR Slew rate RL = 10 kΩ, CL = 20 pF, Vout = 0.5V to 2.8V 0.035 V/μs en Equivalent input noise voltage f = 1 kHz 110 nV -----------Hz 1. Guaranteed by design. Doc ID 15768 Rev 2 5/19 Electrical characteristics Table 5. TSV611, TSV611A, TSV612, TSV612A VCC+ = +5 V, VCC- = 0 V, Vicm = VCC/2, Tamb = 25° C, RL connected to VCC/2 (unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit DC performance TSV61x TSV61xA Vio DVio Iio Iib CMR SVR Avd 4 0.8 Offset voltage mV 5 2 Tmin<Top<Tmax TSV61x Tmin<Top<Tmax TSV61xA Input offset voltage drift 1 10(1) pA 1 100 pA 1 10(1) pA 1 100 pA Input offset current Tmin. < Top < Tmax. Input bias current Tmin. < Top < Tmax. Common mode rejection ratio 20 log (ΔVic/ΔVio) 0 V to 5 V, Vout = 2.5 V 64 Tmin. < Top < Tmax. 63 Supply voltage rejection ratio 20 log (ΔVcc/ΔVio) Vcc = 1.8 to 5 V 76 Tmin. < Top < Tmax. 74 RL = 10 kΩ, Vout = 0.5 V to 4.5 V 88 Tmin<Top<Tmax 85 35 50 Large signal voltage gain 80 93 93 7 VOL Low level output voltage RL = 10 kΩ Tmin. < Top < Tmax. Isink Vo = VCC Tmin. < Top < Tmax. 52 42 57 Isource Vo = 0 V Tmin. < Top < Tmax. 58 49 63 No load, Vout = VCC/2 7.5 10.5 Tmin. < Top < Tmax. dB dB RL = 10 kΩ Tmin. < Top < Tmax. Supply current (per operator) dB dB High level output voltage Iout dB dB VOH ICC μV/°C 2 16 mV 35 50 mV mA 7 14 µA 15 µA AC performance GBP 6/19 Gain bandwidth product RL = 10 kΩ, CL = 20 pF 120 kHz φm Phase margin RL = 10 kΩ, CL = 20 pF 62 Degrees Gm Gain margin RL = 10 kΩ, CL = 20 pF 10 dB SR Slew rate RL = 10 kΩ, CL = 20 pF, Vout = 0.5V to 4.5V 0.04 V/μs Doc ID 15768 Rev 2 TSV611, TSV611A, TSV612, TSV612A Table 5. Symbol en THD+N Electrical characteristics VCC+ = +5 V, VCC- = 0 V, Vicm = VCC/2, Tamb = 25° C, RL connected to VCC/2 (unless otherwise specified) (continued) Parameter Min. Typ. Max. Unit Equivalent input noise voltage f = 1 kHz 105 nV -----------Hz Total harmonic distortion + noise Fin = 1 kHz, Av = 1, Vout = 1 Vpp, RL = 100 kΩ, BW = 22kHz 0.02 % 1. Guaranteed by design. Supply current vs. supply voltage at Vicm = VCC/2 Figure 3. Output current vs. output voltage at Figure 4. VCC = 5 V Gain (dB) Figure 2. Doc ID 15768 Rev 2 Output current vs. output voltage at VCC = 1.5 V Voltage gain and phase vs. frequency at VCC = 1.5 V Phase margin (°) Figure 1. 7/19 Electrical characteristics Figure 7. Figure 6. Phase margin vs. output current Figure 8. Negative slew rate vs. time, VCC = 1.5 V, CLoad = 100 pF, RLoad = 10 kΩ Phase margin(°) Voltage gain and phase vs. frequency at VCC = 5 V Gain (dB) Figure 5. TSV611, TSV611A, TSV612, TSV612A Positive slew rate vs. time, VCC = 1.5 V, CLoad = 100 pF, RLoad = 10 kΩ VCC=1.5V, Vicm=VCC/2, RLoad=10kΩ, CLoad=100pF VLoad=VCC/2 Amplitude (V) T=85°C T=−40°C T=-40°C T=25°C T=85°C VCC=1.5V, Vicm=VCC/2 RLoad=10kΩ, CLoad=100pF T=25°C Time (µs) Figure 9. Time (µs) Positive slew rate vs. time, VCC = 5.5 V, CLoad = 100 pF, RLoad = 100 kΩ Figure 10. Negative slew rate vs. time, VCC = 5.5 V, CLoad = 100 pF, RLoad = 100 kΩ Ω Ω 8/19 Doc ID 15768 Rev 2 TSV611, TSV611A, TSV612, TSV612A Electrical characteristics Figure 12. Noise vs. frequency at Vcc = 5 V Input equivalent noise density (nV/VHz) Figure 11. Slew rate vs. supply voltage Vicm=2.5V Vicm=4.5V VCC=5V T=25°C Frequency (Hz) Figure 13. Distortion + noise vs. frequency Figure 14. Distortion + noise vs. output voltage Vcc=1.5V Rl=10kΩ THD + N (%) THD + N (%) 1 0.1 Vcc=1.5V Rl=100kΩ Vcc=1.5V Rl=10kohms Vcc=1.5V Rl=100kohms Vcc=5.5V Rl=10kohms Ω Vcc=5.5V Rl=100kohms 0.01 Ω 10 100 1000 f=1kHz Gain=1 BW=22kHz Vicm=Vcc/2 10000 Output Voltage (Vpp) Doc ID 15768 Rev 2 Phase margin (°) Gain (dB) Phase margin (°) Gain (dB) Figure 15. Voltage gain and phase vs. Figure 16. Voltage gain and phase vs. frequency at VCC = 1.8 V (based on frequency at VCC = 5 V (based on simulation results) simulation results) 9/19 Application information TSV611, TSV611A, TSV612, TSV612A 3 Application information 3.1 Operating voltages The TSV61x can operate from 1.5 to 5.5 V. Their parameters are fully specified for 1.8, 3.3 and 5 V power supplies. However, the parameters are very stable in the full VCC range and several characterization curves show the TSV61x characteristics at 1.5 V. Additionally, the main specifications are guaranteed in extended temperature ranges from -40° C to +85° C. 3.2 Rail-to-rail input The TSV61x are built with two complementary PMOS and NMOS input differential pairs. The devices have a rail-to-rail input, and the input common mode range is extended from VCC- -0.1 V to VCC+ +0.1 V. The transition between the two pairs appears at VCC+ -0.7 V. In the transition region, the performance of CMRR, PSRR, Vio and THD is slightly degraded (as shown in Figure 17 and Figure 18 for Vio vs. Vicm). Figure 17. Input offset voltage vs input common mode at VCC = 1.5 V Figure 18. Input offset voltage vs input common mode at VCC = 5 V 1.4 1.5 1.2 1.0 Input Offset Voltage (mV) Input Offset Voltage (mV) 1.0 0.5 0.0 -0.5 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -1.0 -0.8 -1.5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Input Common Mode Voltage (V) 1.4 -1.0 0.0 1.0 2.0 3.0 4.0 Input Common Mode Voltage (V) 5.0 The device is guaranteed without phase reversal. 3.3 Rail-to-rail output The operational amplifiers’ output levels can go close to the rails: less than 35 mV above GND rail and less than 35 mV below VCC rail when connected to 10 kΩ load to VCC/2. 3.4 Driving resistive and capacitive loads These products are micro-power, low-voltage operational amplifiers optimized to drive rather large resistive loads, above 10 kΩ. For lower resistive loads, the THD level may significantly increase. 10/19 Doc ID 15768 Rev 2 TSV611, TSV611A, TSV612, TSV612A Application information In a follower configuration, these operational amplifiers can drive capacitive loads up to 100 pF with no oscillations. When driving larger capacitive loads, adding an in-series resistor at the output can improve the stability of the devices (see Figure 19 for recommended in-series resistor values). Once the in-series resistor value has been selected, the stability of the circuit should be tested on bench and simulated with the simulation model. In-series resistor (Ω) Figure 19. In-series resistor vs. capacitive load 3.5 PCB layouts For correct operation, it is advised to add 10 nF decoupling capacitors as close as possible to the power supply pins. 3.6 Macromodel An accurate macromodel of the TSV61x is available on STMicroelectronics’ web site at www.st.com. This model is a trade-off between accuracy and complexity (that is, time simulation) of the TSV61x operational amplifiers. It emulates the nominal performances of a typical device within the specified operating conditions mentioned in the datasheet. It also helps to validate a design approach and to select the right operational amplifier, but it does not replace on-board measurements. Doc ID 15768 Rev 2 11/19 Package information 4 TSV611, TSV611A, TSV612, TSV612A Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 12/19 Doc ID 15768 Rev 2 TSV611, TSV611A, TSV612, TSV612A 4.1 Package information SOT23-5 package information Figure 20. SOT23-5 package mechanical drawing Table 6. SOT23-5 package mechanical data Dimensions Ref. A Millimeters Inches Min. Typ. Max. Min. Typ. Max. 0.90 1.20 1.45 0.035 0.047 0.057 A1 0.15 0.006 A2 0.90 1.05 1.30 0.035 0.041 0.051 B 0.35 0.40 0.50 0.013 0.015 0.019 C 0.09 0.15 0.20 0.003 0.006 0.008 D 2.80 2.90 3.00 0.110 0.114 0.118 D1 1.90 0.075 e 0.95 0.037 E 2.60 2.80 3.00 0.102 0.110 0.118 F 1.50 1.60 1.75 0.059 0.063 0.069 L 0.10 0.35 0.60 0.004 0.013 0.023 K 0 degrees 10 degrees Doc ID 15768 Rev 2 13/19 Package information 4.2 TSV611, TSV611A, TSV612, TSV612A SC70-5 (SOT323-5) package information Figure 21. SC70-5 (SOT323-5) package mechanical drawing SIDE VIEW DIMENSIONS IN MM GAUGE PLANE COPLANAR LEADS SEATING PLANE TOP VIEW Table 7. SC70-5 (SOT323-5) package mechanical data Dimensions Ref Millimeters Min A Typ 0.80 A1 14/19 Inches Max Min 1.10 0.315 Typ 0.043 0.10 A2 0.80 b 0.90 Max 0.004 1.00 0.315 0.035 0.15 0.30 0.006 0.012 c 0.10 0.22 0.004 0.009 D 1.80 2.00 2.20 0.071 0.079 0.087 E 1.80 2.10 2.40 0.071 0.083 0.094 E1 1.15 1.25 1.35 0.045 0.049 0.053 e 0.65 0.025 e1 1.30 0.051 L 0.26 < 0° 0.36 0.46 8° Doc ID 15768 Rev 2 0.010 0.014 0.039 0.018 TSV611, TSV611A, TSV612, TSV612A 4.3 Package information SO-8 package information Figure 22. SO-8 package mechanical drawing Table 8. SO-8 package mechanical data Dimensions Ref. Millimeters Min. Typ. A Inches Max. Min. Typ. 1.75 0.069 A1 0.10 A2 1.25 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.010 D 4.80 4.90 5.00 0.189 0.193 0.197 E 5.80 6.00 6.20 0.228 0.236 0.244 E1 3.80 3.90 4.00 0.150 0.154 0.157 e 0.25 Max. 0.004 0.010 0.049 1.27 0.050 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 L1 k ccc 1.04 1° 0.040 8° 0.10 Doc ID 15768 Rev 2 1° 8° 0.004 15/19 Package information 4.4 TSV611, TSV611A, TSV612, TSV612A MiniSO-8 package information Figure 23. MiniSO-8 package mechanical drawing Table 9. MiniSO-8 package mechanical data Dimensions Ref. Millimeters Min. Typ. A Max. Min. Typ. 1.1 A1 0 A2 0.75 b Max. 0.043 0.15 0 0.95 0.030 0.22 0.40 0.009 0.016 c 0.08 0.23 0.003 0.009 D 2.80 3.00 3.20 0.11 0.118 0.126 E 4.65 4.90 5.15 0.183 0.193 0.203 E1 2.80 3.00 3.10 0.11 0.118 0.122 e L 0.85 0.65 0.40 0.60 0.006 0.033 0.80 0.016 0.024 0.95 0.037 L2 0.25 0.010 ccc 0° 0.037 0.026 L1 k 16/19 Inches 8° 0.10 Doc ID 15768 Rev 2 0° 0.031 8° 0.004 TSV611, TSV611A, TSV612, TSV612A 5 Ordering information Ordering information Table 10. Order codes Order code Temperature range Package Packing TSV611ILT Marking K12 SOT23-5 TSV611AILT K11 Tape & reel TSV611ICT K12 SC70-5 TSV611AICT K11 -40° C to 85° C TSV612ID/DT V612I SO-8 Tube & tape & reel TSV612AID/DT V612AI TSV612IST K113 MiniSO-8 TSV612AIST Tape & reel K115 Doc ID 15768 Rev 2 17/19 Revision history 6 TSV611, TSV611A, TSV612, TSV612A Revision history Table 11. 18/19 Document revision history Date Revision Changes 28-May-2009 1 Initial release. 18-Jan-2010 2 Full datasheet for product now in production. Added Figure 1 to Figure 19. Doc ID 15768 Rev 2 TSV611, TSV611A, TSV612, TSV612A Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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