USBLC6-2 ® ASD (Application Specific Devices) VERY LOW CAPACITANCE ESD PROTECTION MAIN APPLICATIONS ■ USB2.0 ports at 480Mbps (high speed) and USB OTG ports ■ Backwards Compatible with USB1.1 Low and full speed ■ Ethernet port: 10/100Mb/s ■ SIM card protection ■ Video line protection ■ Portable and mobile electronics DESCRIPTION The USBLC6-2P6 and USBLC6-2SC6 are two monolithic Application Specific Devices dedicated to ESD protection of high speed interfaces such as USB2.0, Ethernet links and Video lines. The very low line capacitance secures a high level of signal integrity without compromising in protection sensitive chips against the most stringent characterized ESD strikes. FEATURES ■ 2 data lines protection ■ Protects VBUS ■ Very low capacitance: 3.5pF max ■ Very low leakage current: 1µA max ■ SOT-666 and SOT23-6L packages ■ RoHS compliant BENEFITS ■ Very low capacitance between lines to GND for optimized data integrity and speed ■ Ultra low PCB space consuming: 2.9mm² max for SOT-666 package and 9mm² max for SOT23-6L package ■ Enhanced ESD protection: IEC61000-4-2 level 4 compliance guaranteed at device level, hence greater immunity at system level ■ ESD protection of VBUS. Allows ESD current flowing to Ground when ESD event occurs on data line ■ High reliability offered by monolithic integration ■ Very low leakage current for longer operation of battery powered devices ■ Fast response time ■ Consistant D+/D- signal balance - Best capacitance matching tolerance I/O to GND of 0.04pF - Compliance with USB2.0 requirement (<1pF) June 2005 SOT23-6L USBLC6-2SC6 SOT-666 USBLC6-2P6 Table 1: Order Codes Part Number USBLC6-2SC6 USBLC6-2P6 Marking UL26 F Figure 1: Functional Diagram I/O1 1 6 I/O1 GND 2 5 VBUS I/O2 3 4 I/O2 COMPLIES WITH THE FOLLOWING STANDARDS: ■ IEC61000-4-2 level 4: 15kV (air discharge) 8kV (contact discharge) REV. 2 1/11 USBLC6-2 Table 2: Absolute Ratings Symbol Parameter VPP Peak pulse voltage Tstg Storage temperature range Value At device level: IEC61000-4-2 air discharge IEC61000-4-2 contact discharge MIL STD883C-Method 3015-6 Unit 15 15 25 kV -55 to +150 °C Tj Maximum junction temperature 125 °C TL Lead solder temperature (10 seconds duration) 260 °C Table 3: Electrical Characteristics (Tamb = 25°C) Symbol Parameter Test Conditions Value Min. Typ. Unit VRM Reverse stand-off voltage IRM Leakage current VRM = 5V VBR Breakdown voltage between VBUS and GND IF = 1mA Forward voltage IF = 10mA 1.1 V IPP = 1A, tp = 8/20µs Any I/O pin to GND 12 V IPP = 5A, tp = 8/20µs Any I/O pin to GND 17 V VF VCL Ci/o-GND Clamping voltage Capacitance between I/O and GND V = 0V F = 1MHz any I/O pin to GND Ci/o-i/o ∆Ci/o-i/o 5 V 1 µA 6 V 2.5 3.5 pF ∆Ci/o-GND 2/11 Max. 0.04 Capacitance between I/O V = 0V F = 1MHz between I/O, GND not connected 1.2 1.7 pF 0.04 USBLC6-2 Figure 2: Capacitance versus line voltage (typical values) Figure 3: Line capacitance versus frequency (typical values) C(pF) C(pF) 3.0 2.8 2.6 CO=I/O-GND 2.4 2.5 VOSC=30mVRMS Tj=25°C VLINE=0V to 3.3V 2.2 F=1MHz VOSC=30mVRMS Tj=25°C 2.0 2.0 1.8 1.6 1.5 1.4 Cj=I/O-I/O 1.2 1.0 1.0 0.8 0.6 0.5 0.4 0.2 Data line voltage (V) F(MHz) 0.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Figure 4: Relative variation of leakage current versus junction temperature (typical values) 1 10 100 1000 Figure 5: Frequency response 0.00 IRM[Tj] / IRM[Tj=25°C] 100 S21(dB) VBUS=5V -5.00 -10.00 10 -15.00 Tj(°C) F(Hz) 1 25 50 75 100 125 -20.00 100.0k 1.0M 10.0M 100.0M 1.0G 3/11 USBLC6-2 TECHNICAL INFORMATION 1. SURGE PROTECTION The USBLC6-2 is particularly optimized to perform surge protection based on the rail to rail topology. The clamping voltage VCL can be calculated as follow : VCL+ = VBUS + VF for positive surge VCL- = - VF for negative surge with: VF = VT + Rd.Ip (VF forward drop voltage) / (VT threshold voltage) We assume that the value of the dynamic resistance of the clamping diode is typically: Rd = 0.5Ω and VT = 1.2V. For an IEC61000-4-2 surge Level 4 (Contact Discharge: Vg=8kV, Rg=330Ω), VBUS = +5V, and if in first approximation, we assume that : Ip = Vg / Rg = 24A. So, we find: VCL+ = +17V VCL- = -12V Note: the calculations do not take into account phenomena due to parasitic inductances. 2. SURGE PROTECTION APPLICATION EXAMPLE If we consider that the connections from the pin VBUS to VCC and from GND to PCB GND are done by two tracks of 10mm long and 0.5mm large; we assume that the parasitic inductances Lw of these tracks are about 6nH. So when an IEC61000-4-2 surge occurs, due to the rise time of this spike (tr=1ns), the voltage VCL has an extra value equal to Lw.dI/dt. The dI/dt is calculated as: dI/dt = Ip/tr = 24 A/ns The overvoltage due to the parasitic inductances is: Lw.dI/dt = 6 x 24 = 144V By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will be : VCL+ = +17 + 144 = 161V VCL- = -12 - 144 = -156V We can reduce as much as possible these phenomena with simple layout optimization. It’s the reason why some recommendations have to be followed (see paragraph “How to ensure a good ESD protection”). Figure 6: ESD behavior; parasitic phenomena due to unsuitable layout VCL+ 183V Lw VBUS ESD SURGE +VCC VF Lw di dt Lw di dt POSITIVE SURGE VCC+VF t I/O tr=1ns di VCL+ = VBUS+VF+Lw dt surge >0 di surge <0 VCL- = -VF-Lw dt VI/O Lw di dt tr=1ns t -VF -Lw di dt NEGATIVE SURGE GND -178V VCL- 4/11 USBLC6-2 3. HOW TO ENSURE A GOOD ESD PROTECTION While the USBLC6-2 provides a high immunity to ESD surge, an efficient protection depends on the layout of the board. In the same way, with the rail to rail topology, the track from the VBUS pin to the power supply +VCC and from the GND pin to GND must be as short as possible to avoid overvoltages due to parasitic phenomena (see figure 6). It’s often harder to connect the power supply near to the USBLC6-2 unlike the ground thanks to the ground plane that allows a short connection. To ensure the same efficiency for positive surges when the connections can’t be short enough, we recommend to put close to the USBLC6-2, between VBUS and ground, a capacitance of 100nF to prevent from these kinds of overvoltage disturbances (see figure 7). The add of this capacitance will allow a better protection by providing during surge a constant voltage. The figures 8, 9 and 10 show the improvement of the ESD protection according to the recommendations described above. Figure 7: ESD behavior: optimized layout and add of a capacitance of 100nF Figure 8: ESD behavior: measurements conditions (with coupling capacitance) ESD SURGE VCL+ TEST BOARD Lw ESD SURGE REF2=+VCC POSITIVE SURGE USBLC6-2SC6 C=100nF t I/O t VCL+ = VCC+VF surge >0 VI/O VCL- = -VF surge <0 +5V NEGATIVE SURGE REF1=GND VCL- C=100nF Figure 9: Remaining voltage after the USBLC6-2 during positive ESD surge Figure 10: Remaining voltage after USBLC6-2 during negative ESD surge the Vin Vin Vout Vout IMPORTANT: A main precaution to take is to put the protection device closer to the disturbance source (generally the connector). Note: The measurements have been done with the USBLC6-2 in open circuit. 5/11 USBLC6-2 4. CROSSTALK BEHAVIOR 4.1. Crosstalk phenomena Figure 11: Crosstalk phenomena RG1 Line 1 VG1 α 1 VG1 + β12VG2 RL1 RG2 Line 2 VG2 α 2VG2 + β21VG1 RL2 DRIVERS RECEIVERS The crosstalk phenomena are due to the coupling between 2 lines. The coupling factor (β12 or β21) increases when the gap across lines decreases, particularly in silicon dice. In the example above the expected signal on load RL2 is α2VG2, in fact the real voltage at this point has got an extra value β21VG1. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few kΩ). Figure 12: Analog crosstalk measurements TRACKING GENERATOR SPECTRUM ANALYSER TEST BOARD USBLC6-2SC6 50Ω 50Ω Vg Vin Vout C=100nF VBUS Figure 12 gives the measurement circuit for the analog application. In usual frequency range of analog signals (up to 240MHz) the effect on disturbed line is less than -55 dB (please see figure 13). Figure 13: Analog crosstalk results Analog Crosstalk APLAC 7.91 User: ST Microelectronics Jan 12 2005 0.00 dB -30.00 -60.00 -90.00 -120.00 100.0k 1.0M Attenuation 6/11 10.0M 100.0M f/Hz 1.0G As the USBLC6-2 is designed to protect high speed data lines, it must ensure a good transmission of operating signals. The frequency response (figure 5) gives attenuation information and shows that the USBLC6-2 is well suitable for data line transmission up to 480 Mbit/s while it works as a filter for undesirable signals like GSM (900MHz) frequencies, for instance. USBLC6-2 5. APPLICATION EXAMPLES Figure 14: USB2.0 port application diagram using USBLC6-2 + 3.3V DEVICEUPSTREAM RPU TRANSCEIVER SW2 + 5V USB connector SW1 VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS GND TX LS/FS + TX LS/FS - Protecting Bus Switch VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS - VBUS D+ DGND RS RS RS USBLC6-2SC6 RS RPD + 3.3V DEVICEUPSTREAM RPU TRANSCEIVER SW2 TX LS/FS - TX LS/FS - RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS - D+ DGND RS RS TX LS/FS + RPD VBUS TX LS/FS + GND USB connector SW1 VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS GND HUBDOWNSTREAM TRANSCEIVER RS USBLC6-2P6 RS RPD Mode SW1 SW2 Low Speed LS Open Closed Full Speed FS Closed Open High Speed HS Closed then open Open GND TX LS/FS + USBLC6-4SC6 TX LS/FS - RPD +VCC Tx 100nF USBLC6-2SC6 Figure 15: T1/E1/Ethernet protection SMP75-8 DATA +VCC Rx 100nF USBLC6-2SC6 TRANSCEIVER SMP75-8 7/11 USBLC6-2 6. PSPICE MODEL Figure 16 shows the PSPICE model of one USBLC6-2 cell. In this model, the diodes are defined by the PSPICE parameters given in figure 17. Figure 16: PSPICE model LI/O RI/O RI/O LI/O D+out D+in MODEL = Dlow LGND RGND MODEL = Dhigh RI/O MODEL = Dzener LI/O GND VBUS MODEL = Dlow LI/O MODEL = Dhigh RI/O RI/O LI/O D-in D-out Note: This simulation model is available only for an ambient temperature of 27°C. Figure 17: PSPICE parameters Figure 18: considerations Dlow Dhigh Dzener LI/O 750p BV 50 50 7.3 RI/O 110m CJ0 0.9p 2.0p 40p LGND 550p IBV 1m 1m 1m RGND 60m M 0.3333 0.3333 0.3333 RS 0.2 0.52 0.84 VJ 0.6 0.6 0.6 TT 0.1u 0.1u 0.1u 8/11 D+in USBLC6-2 PCB layout D+out 1 VBUS GND CBUS = 100nF D-in USBLC6-2 D-out USBLC6-2 Figure 19: Ordering Information Scheme USB LC 6 - 2 xxx Product Designation Low capacitance Breakdown Voltage 6 = 6 Volts Number of lines protected 2 = 2 lines Packages SC6 = SOT23-6L P6 = SOT-666 Figure 20: SOT-666 Package Mechanical Data DIMENSIONS REF. Millimeters Inches Min. Max. Min. Max. A 0.50 0.60 0.020 0.024 bp 0.17 0.27 0.007 0.011 bp D E A Lp U He c 0.08 0.18 0.003 0.007 D 1.50 1.70 0.060 0.067 E 1.10 1.30 0.043 0.051 e e1 e1 1.00 typ. 0.50 typ. 0.040 typ. 0.020 typ. He 1.50 1.70 0.059 0.067 Lp 0.10 0.30 0.004 0.012 e Figure 21: Foot Print Dimensions (in millimeters) 0.43 2.75 1.16 0.5 0.3 9/11 USBLC6-2 Figure 22: SOT23-6L Package Mechanical Data DIMENSIONS A REF. E Millimeters Min. e B D A 0.90 A1 0 Inches Min. Typ. Max. 1.45 0.035 0.057 0.10 0.004 0 0.90 1.30 0.035 0.051 b 0.35 0.50 0.014 0.02 C 0.09 0.20 0.004 0.008 D 2.80 3.05 0.110 0.120 E 1.50 A2 e A1 θ Max. A2 e c Typ. L H 1.75 0.059 0.95 0.069 0.037 H 2.60 3.00 0.102 0.118 L 0.10 0.60 0.004 0.024 θ 0° 10° 0° 10° Figure 23: Foot Print Dimensions (in millimeters) 0.60 1.20 0.95 3.50 1.10 2.30 Table 4: Ordering Information Ordering code Marking Package Weight Base qty Delivery mode USBLC6-2SC6 UL26 SOT23-6L 16.7 mg 3000 Tape & reel USBLC6-2P6 F SOT-666 2.9 mg 3000 Tape & reel Table 5: Revision History Date Revision 14-Mar-2005 1 First issue. 07-Jun-2005 2 Format change to figure 3; no content changed. 10/11 Description of Changes USBLC6-2 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. 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