VN750-E / VN750S-E VN750PT-E / VN750B5-E HIGH SIDE DRIVER Table 1. General Features Type VN750-E VN750B5-E VN750S-E VN750PT Figure 1. Package RDS(on) IOUT VCC 60 mΩ 6A 36 V SO-8 CMOS COMPATIBLE INPUT ON STATE OPEN LOAD DETECTION ■ OFF STATE OPEN LOAD DETECTION ■ SHORTED LOAD PROTECTION ■ UNDERVOLTAGE AND OVERVOLTAGE SHUTDOWN ■ PROTECTION AGAINST LOSS OF GROUND ■ VERY LOW STAND-BY CURRENT PENTAWATT ■ ■ P2PAK PPAK Active current limitation combined with thermal shutdown and automatic restart protect the device against overload. The device detects open load condition both is on and off state. Output shorted to VCC is detected in the off state. Device automatically turns off in case of ground pin disconnection. REVERSE BATTERY PROTECTION (*) IN COMPLIANCE WITH THE 2002/95/EC EUROPEAN DIRECTIVE ■ ■ DESCRIPTION The VN750-E, VN750S-E, VN750PT-E, VN750B5-E are a monolithic device designed in STMicroelectronics VIPower M0-3 Technology, intended for driving any kind of load with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). Table 2. Order Codes Package Tube Tape and Reel PENTAWATT VN750-E - SO-8 VN750S-E VN750STR-E P PAK VN750B5-E VN750B5TR-E PPAK VN750PT-E VN750PTTR-E 2 Note: (*) See application schematic at page 9. Rev. 1 October 2004 1/31 VN750-E / VN750S-E / VN750PT-E / VN750B5-E Figure 2. Block Diagram VCC OVERVOLTAGE DETECTION VCC CLAMP UNDERVOLTAGE DETECTION GND Power CLAMP DRIVER INPUT OUTPUT LOGIC CURRENT LIMITER ON STATE OPENLOAD DETECTION STATUS OVERTEMPERATURE DETECTION OFF STATE OPENLOAD AND OUTPUT SHORTED TO VCC DETECTION Table 3. Absolute Maximum Ratings Symbol VCC - VCC - Ignd IOUT - IOUT IIN ISTAT Parameter SO-8 DC Supply Voltage Reverse DC Supply Voltage DC Reverse Ground Pin Current DC Output Current Reverse DC Output Current DC Input Current DC Status Current Electrostatic Discharge Value PENTAWATT P2PAK 41 - 0.3 - 200 Internally Limited -6 +/- 10 +/- 10 PPAK Unit V V mA A A mA mA (Human Body Model: R=1.5KΩ; C=100pF) VESD EMAX EMAX Ptot Tj Tc Tstg 2/31 - INPUT 4000 V - STATUS 4000 V - OUTPUT 5000 V - VCC Maximum Switching Energy 5000 V (L=1.8mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IL=9A) Maximum Switching Energy (L=2.46mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IL=9A) Power Dissipation TC=25°C Junction Operating Temperature Case Operating Temperature Storage Temperature 100 mJ 138 4.2 60 60 Internally Limited - 40 to 150 - 55 to 150 138 mJ 60 W °C °C °C VN750-E / VN750S-E / VN750PT-E / VN750B5-E Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins VCC OUTPUT OUTPUT VCC OUTPUT STATUS VCC INPUT GND 5 5 4 8 1 N.C. STATUS INPUT GND 4 3 2 1 PPAK / P2PAK SO-8 Connection / Pin Status Floating X To Ground N.C. X X PENTAWATT Output X Input X Through 10KΩ resistor Figure 4. Current and Voltage Conventions IS VF IIN VCC INPUT ISTAT IOUT STATUS VCC OUTPUT GND VIN VSTAT IGND VOUT Table 4. Thermal Data Symbol Parameter Rthj-case Rthj-lead Thermal Resistance Junction-case Thermal Resistance Junction-lead Rthj-amb Thermal Resistance Junction-ambient Max Max Max S0-8 30 93 (1) 82 (2) Value PENTAWATT P2PAK 2.1 2.1 62.1 52.1 (3) 62.1 37 (4) PPAK 2.1 77.1 (3) 44 (4) Unit °C/W °C/W °C/W °C/W (1) When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35µm thick) connected to all VCC pins. Horizontal mounting and no artificial air flow. (2) When mounted on a standard single-sided FR-4 board with 2cm2 of Cu (at least 35µm thick) connected to all VCC pins. Horizontal mounting and no artificial air flow. (3) When mounted on a standard single-sided FR-4 board with 0.5cm 2 of Cu (at least 35µm thick). Horizontal mounting and no artificial air flow. (4) When mounted on a standard single-sided FR-4 board with 6cm2 of Cu (at least 35µm thick). Horizontal mounting and no artificial air flow. 3/31 VN750-E / VN750S-E / VN750PT-E / VN750B5-E ELECTRICAL CHARACTERISTICS (8V<VCC<36V; -40°C<Tj<150°C unless otherwise specified) Table 5. Power Symbol Parameter VCC Min. Typ. Max. Unit Operating Supply Voltage 5.5 13 36 V VUSD Undervoltage Shut-down 3 4 5.5 V VUSDhyst Undervoltage Shut-down Hysteresis VOV Overvoltage Shut-down RON On State Resistance IS Supply Current Test Conditions 0.5 V 36 IOUT=2A; Tj=25°C; VCC>8V V (#) IOUT=2A; VCC>8V 60 mΩ 120 mΩ 25 µA Off State; VCC=13V; VIN=VOUT=0V 10 Off State; VCC=13V; VIN=VOUT=0V; Tj=25°C 10 20 µA On State; VCC=13V; VIN=5V; IOUT=0A 2 3.5 mA (#) 50 µA 0 µA IL(off1) Off State Output Current VIN=VOUT=0V 0 IL(off2) Off State Output Current VIN=0V; VOUT=3.5V IL(off3) Off State Output Current VIN=VOUT=0V; VCC=13V; Tj =125°C 5 µA IL(off4) Off State Output Current VIN=VOUT=0V; VCC=13V; Tj =25°C 3 µA Max. Unit -75 Table 6. Switching (VCC =13V) Symbol Parameter Test Conditions Min. Typ. td(on) Turn-on Delay Time RL=6.5Ω from VIN rising edge to VOUT=1.3V 40 µs td(off) Turn-off Delay Time RL=6.5Ω from VIN falling edge to VOUT=11.7V 30 µs dVOUT/ dt(on) Turn-on Voltage Slope RL=6.5Ω from VOUT=1.3V to VOUT=10.4V (#) V/µs dVOUT/ dt(off) Turn-off Voltage Slope RL=6.5Ω from VOUT=11.7V to VOUT=1.3V (#) V/µs Table 7. Input Pin Symbol Parameter VIL Input Low Level IIL Low Level Input Current VIH Input High Level IIH High Level Input Current Vhyst Input Hysteresis Voltage VICL Input Clamp Voltage Note: (#) See relative diagram 4/31 Test Conditions VIN=1.25V Min. Unit (#) 1.25 V (#) µA 3.25 (#) V (#) 0.5 IIN=-1mA Max. 1 VIN=3.25V IIN=1mA Typ. 6 10 (#) 6.8 -0.7 µA V 8 V V VN750-E / VN750S-E / VN750PT-E / VN750B5-E ELECTRICAL CHARACTERISTICS (continued) Table 8. VCC - Output Diode Symbol VF Parameter Test Conditions Forward on Voltage Min. Typ. -IOUT=1.3A; Tj=150°C Max. Unit 0.6 V Max 0.5 10 Unit V µA 100 pF 8 V Table 9. Status Pin Symbol VSTAT ILSTAT CSTAT VSCL Parameter Test Conditions Status Low Output Voltage ISTAT=1.6mA Status Leakage Current Normal Operation; VSTAT=5V Status Pin Input Normal Operation; VSTAT=5V Capacitance ISTAT=1mA Status Clamp Voltage ISTAT=-1mA Min 6 Typ (#) (#) 6.8 -0.7 V Table 10. Protections (see note 1) Symbol TTSD TR Thyst tSDL Parameter Shut-down Temperature Reset Temperature Thermal Hysteresis Status delay in overload condition Ilim Current limitation Vdemag Turn-off Output Clamp Voltage Test Conditions Min 150 135 7 Typ 175 6 9 5V<VCC<36V IOUT=2A; VIN=0V; L=6mH VCC-41 Unit °C °C °C 20 µs 15 A 15 A VCC-55 V 15 Tj>Tjsh 9V<VCC<36V Max 200 VCC-48 Note: 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. Table 11. Openload Detection Symbol IOL tDOL(on) VOL tDOL(off) Parameter Openload ON State Detection Threshold Openload ON State Detection Delay Openload OFF State Voltage Detection Threshold Openload Detection Delay at Turn Off Test Conditions VIN=5V Min Typ Max Unit 50 (#) 200 mA 200 µs 3.5 V 1000 µs IOUT=0A VIN=0V 1.5 (#) Note: (#) See relative diagram 5/31 VN750-E / VN750S-E / VN750PT-E / VN750B5-E Figure 5. OPEN LOAD STATUS TIMING (with external pull-up) IOUT< IOL VOUT > VOL OVERTEMP STATUS TIMING Tj > Tjsh VIN VIN VSTAT VSTAT tDOL(off) tDOL(on) tSDL tSDL Table 12. Truth Table CONDITIONS INPUT OUTPUT STATUS Normal Operation L H L H H H Current Limitation L H H L X X H (Tj < TTSD) H (Tj > TTSD) L Overtemperature L H L L H L Undervoltage L H L L X X Overvoltage L H L L H H Output Voltage > VOL L H H H L H Output Current < IOL L H L H H L Figure 6. Switching time Waveforms VOUTn 90% 80% dVOUT/dt(off) dVOUT/dt(on) 10% t VINn td(on) td(off) t 6/31 VN750-E / VN750S-E / VN750PT-E / VN750B5-E Table 13. Electrical Transient Requirements On VCC Pin TEST LEVELS ISO T/R 7637/1 Test Pulse I II III IV 1 2 3a 3b 4 5 -25 V +25 V -25 V +25 V -4 V +26.5 V -50 V +50 V -50 V +50 V -5 V +46.5 V -75 V +75 V -100 V +75 V -6 V +66.5 V -100 V +100 V -150 V +100 V -7 V +86.5 V ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 CLASS C E Delays and Impedance 2 ms 10 Ω 0.2 ms 10 Ω 0.1 µs 50 Ω 0.1 µs 50 Ω 100 ms, 0.01 Ω 400 ms, 2 Ω I TEST LEVELS RESULTS II III IV C C C C C C C C C C C E C C C C C E C C C C C E CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. 7/31 VN750-E / VN750S-E / VN750PT-E / VN750B5-E Figure 7. Waveforms NORMAL OPERATION INPUT LOAD VOLTAGE STATUS UNDERVOLTAGE VUSDhyst VCC VUSD INPUT LOAD VOLTAGE STATUS undefined OVERVOLTAGE VCC<VOV VCC>VOV VCC INPUT LOAD VOLTAGE STATUS OPEN LOAD with external pull-up INPUT VOUT>VOL LOAD VOLTAGE VOL STATUS OPEN LOAD without external pull-up INPUT LOAD VOLTAGE STATUS Tj INPUT LOAD CURRENT STATUS 8/31 TTSD TR OVERTEMPERATURE VN750-E / VN750S-E / VN750PT-E / VN750B5-E Figure 8. Application Schematic +5V +5V VCC Rprot STATUS Dld µC Rprot INPUT OUTPUT GND RGND VGND GND PROTECTION REVERSE BATTERY NETWORK AGAINST Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND ≤ 600mV / (IS(on)max). 2) RGND ≥ (−VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device’s datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggests to utilize Solution 2 (see below). Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of DGND the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected. LOAD DUMP PROTECTION Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table. µC I/Os PROTECTION: If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the µC I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os. -VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V 5kΩ ≤ Rprot ≤ 65kΩ. Recommended Rprot value is 10kΩ. 9/31 VN750-E / VN750S-E / VN750PT-E / VN750B5-E VOUT=(VPU/(RL+RPU))RL<VOlmin. 2) no misdetection when load is disconnected: in this case the VOUT has to be higher than VOLmax; this results in the following condition RPU<(VPU–VOLmax)/ IL(off2). Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pull-up resistor RPU should be connected to a supply that is switched OFF when the module is in standby. The values of VOLmin, VOLmax and IL(off2) are available in the Electrical Characteristics section. OPEN LOAD DETECTION IN OFF STATE Off state open load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: 1) no false open load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition Figure 9. Open Load detection in off state V batt. VPU VCC RPU INPUT DRIVER + LOGIC IL(off2) OUT + R STATUS VOL GROUND 10/31 RL VN750-E / VN750S-E / VN750PT-E / VN750B5-E Figure 10. Off State Output Current Figure 11. High Level Input Current Iih (uA) IL(off1) (uA) 7 3 2.5 6 Off state Vcc=36V Vin=Vout=0V 2 Vin=3.25V 5 1.5 4 1 3 0.5 2 0 1 -0.5 -1 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (ºC) 50 75 100 125 150 175 125 150 175 125 150 175 Tc (ºC) Figure 12. Input Clamp Voltage Figure 14. Status Leakage Current Ilstat (uA) Vicl (V) 0.05 8 7.8 Iin=1mA 0.04 7.6 7.4 Vstat=5V 0.03 7.2 7 0.02 6.8 6.6 0.01 6.4 6.2 0 6 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 Tc (°C) Tc (°C) Figure 13. Status Low Output Voltage Figure 15. Status Clamp Voltage Vstat (V) Vscl (V) 0.6 8 7.8 Istat=1mA 0.5 7.6 Istat=1.6mA 7.4 0.4 7.2 7 0.3 6.8 0.2 6.6 6.4 0.1 6.2 6 0 -50 -25 0 25 50 75 Tc (ºC) 100 125 150 175 -50 -25 0 25 50 75 100 Tc (°C) 11/31 VN750-E / VN750S-E / VN750PT-E / VN750B5-E Figure 16. On State Resistance Vs Tcase Figure 17. On State Resistance Vs VCC Ron (mOhm) Ron (mOhm) 140 120 110 120 Iout=2A Iout=2A Vcc=8V; 13V; 36V 100 100 Tc= 150°C 90 80 80 Tc= 125°C 70 60 60 50 40 Tc= 25°C 40 Tc= - 40°C 20 30 20 0 -50 -25 0 25 50 75 100 125 150 5 175 10 15 20 25 30 35 40 Vcc (V) Tc (ºC) Figure 18. Openload On State Detection Threshold Figure 20. Openload Off State Voltage Detection Threshold Iol (mA) Vol (V) 5 220 200 4.5 Vcc=13V Vin=5V 180 Vin=0V 4 160 140 3.5 120 3 100 2.5 80 60 2 40 1.5 20 0 1 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (ºC) 50 75 100 125 150 175 Tc (ºC) Figure 19. Input High Level Figure 21. Input Low Level Vih (V) Vil (V) 3.6 2.8 3.4 2.6 2.4 3.2 2.2 3 2 2.8 1.8 2.6 1.6 2.4 1.4 2.2 1.2 2 1 -50 -25 0 25 50 75 Tc (ºC) 12/31 100 125 150 175 -50 -25 0 25 50 75 Tc (ºC) 100 125 150 175 VN750-E / VN750S-E / VN750PT-E / VN750B5-E Figure 22. Turn-on Voltage Slope Figure 25. Turn-off Voltage Slope dVout/dt/(on) (V/ms) dVout/dt(off) (V/ms) 1000 500 900 450 Vcc=13V Rl=6.5Ohm 800 Vcc=13V Rl=6.5Ohm 400 700 350 600 300 500 250 400 200 300 150 200 100 100 50 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (ºC) 50 75 100 125 150 175 100 125 150 175 Tc (ºC) Figure 23. Overvoltage Shutdown Figure 26. ILIM Vs Tcase Vov (V) Ilim (A) 50 20 48 18 46 16 44 14 42 12 40 10 38 8 36 6 34 4 32 2 Vcc=13V 30 0 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) -50 -25 0 25 50 75 Tc (ºC) Figure 24. Input Hysteresis Voltage Vhyst (V) 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 -50 -25 0 25 50 75 100 125 150 175 Tc (ºC) 13/31 VN750-E / VN750S-E / VN750PT-E / VN750B5-E Figure 27. SO-8 Maximum turn off current versus load inductance ILMAX (A) 100 10 A B C 1 0.1 1 10 100 L(mH) A = Single Pulse at TJstart=150ºC B= Repetitive pulse at TJstart=100ºC C= Repetitive Pulse at TJstart=125ºC Conditions: VCC=13.5V Values are generated with RL=0Ω In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. VIN, IL Demagnetization Demagnetization Demagnetization t 14/31 VN750-E / VN750S-E / VN750PT-E / VN750B5-E Figure 28. PPAK, P2PAK Maximum turn off current versus load inductance ILMAX (A) 100 10 A B C 1 0.1 1 10 100 L(mH) A = Single Pulse at TJstart=150ºC B= Repetitive pulse at TJstart=100ºC C= Repetitive Pulse at TJstart=125ºC Conditions: VCC=13.5V Values are generated with RL=0Ω In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. VIN, IL Demagnetization Demagnetization Demagnetization t 15/31 VN750-E / VN750S-E / VN750PT-E / VN750B5-E SO-8 Thermal Data Figure 29. SO-8 PC Board Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm, Cu thickness=35µm, Copper areas: 0.14cm2, 0.8cm2, 2cm2). Figure 30. Rthj-amb Vs PCB copper area in open box free air condition RTHj_amb (ºC/W) SO-8 at 2 pins connected to TAB 110 105 100 95 90 85 80 75 70 0 0.5 1 1.5 PCB Cu heatsink area (cm^2) 16/31 2 2.5 VN750-E / VN750S-E / VN750PT-E / VN750B5-E P2PAK Thermal Data Figure 31. P2PAK PC Board Layout condition of Rth and Zth measurements (PCB FR4 area= 60mm x 60mm, PCB thickness=2mm, Cu thickness=35µm, Copper areas: 0.97cm2, 8cm2). Figure 32. Rthj-amb Vs PCB copper area in open box free air condition RTHj_amb (°C/W) 55 Tj-Tamb=50°C 50 45 40 35 30 0 2 4 6 8 10 PCB Cu heatsink area (cm^2) 17/31 VN750-E / VN750S-E / VN750PT-E / VN750B5-E PPAK Thermal Data Figure 33. PPAK PC Board Layout condition of Rth and Zth measurements (PCB FR4 area= 60mm x 60mm, PCB thickness=2mm, Cu thickness=35µm, Copper areas: 0.44cm2, 8cm2). Figure 34. Rthj-amb Vs PCB copper area in open box free air condition RTHj_amb (ºC/W) 90 80 70 60 50 40 30 20 10 0 0 2 4 6 PCB Cu heatsink area (cm^2) 18/31 8 10 VN750-E / VN750S-E / VN750PT-E / VN750B5-E Figure 35. SO-8 Thermal Impedance Junction Ambient Single Pulse ZTH (°C/W) 1000 0.5 cm2 100 2 cm2 10 1 0.1 0.01 0.0001 0.001 0.01 0.1 1 Time (s) Figure 36. Thermal fitting model of a single channel HSD in SO-8 10 100 1000 Pulse calculation formula THδ where = R TH ⋅ δ + Z THtp ( 1 – δ ) δ = tp ⁄ T Table 14. Thermal Parameter Tj C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 R6 Pd T_amb R1 R2 R3 R4 R5 R6 C1 C2 C3 C4 C5 C6 Area/island (cm2) (°C/W) (°C/W) ( °C/W) (°C/W) (°C/W) (°C/W) (W.s/°C) (W.s/°C) (W.s/°C) (W.s/°C) (W.s/°C) (W.s/°C) 0.5 0.05 0.8 3.5 21 16 58 0.006 2.60E-03 0.0075 0.045 0.35 1.05 2 28 2 19/31 VN750-E / VN750S-E / VN750PT-E / VN750B5-E Figure 37. PPAK Thermal Impedance Junction Ambient Single Pulse ZT H (°C/W) 1000 100 0.44 cm2 6 cm2 10 1 0.1 0.0001 0.001 0.01 0.1 1 T ime (s) Figure 38. Thermal fitting model of a single channel HSD in PPAK 10 100 1000 Pulse calculation formula THδ where = R TH ⋅ δ + Z THtp ( 1 – δ ) δ = tp ⁄ T Table 15. Thermal Parameter Tj C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 R6 Pd T_amb 20/31 R1 R2 R3 R4 R5 R6 C1 C2 C3 C4 C5 C6 Area/island (cm2) (°C/W) (°C/W) ( °C/W) (°C/W) (°C/W) (°C/W) (W.s/°C) (W.s/°C) (W.s/°C) (W.s/°C) (W.s/°C) (W.s/°C) 0.5 0.15 0.7 1.6 2 15 61 0.0006 0.0025 0.08 0.3 0.45 0.8 6 24 5 VN750-E / VN750S-E / VN750PT-E / VN750B5-E Figure 39. P2PAK Thermal Impedance Junction Ambient Single Pulse ZTH (°C/W) 1000 100 0.5 cm2 6 cm2 10 1 0.1 0.0001 0.001 0.01 0.1 1 Time (s) Figure 40. Thermal fitting model of a single channel HSD in P2PAK 10 100 1000 Pulse calculation formula THδ where = R TH ⋅ δ + Z THtp ( 1 – δ ) δ = tp ⁄ T Table 16. Thermal Parameter Tj C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 R6 Pd T_amb R1 R2 R3 R4 R5 R6 C1 C2 C3 C4 C5 C6 Area/island (cm2) (°C/W) (°C/W) ( °C/W) (°C/W) (°C/W) (°C/W) (W.s/°C) (W.s/°C) (W.s/°C) (W.s/°C) (W.s/°C) (W.s/°C) 0.5 0.15 0.7 0.7 4 9 37 0.0006 0.0025 0.055 0.4 2 3 6 22 5 21/31 VN750-E / VN750S-E / VN750PT-E / VN750B5-E PACKAGE MECHANICAL Table 17. SO-8 Mechanical Data Symbol millimeters Min Typ A a1 1.75 0.1 0.25 a3 0.65 0.85 a2 1.65 b 0.35 0.48 b1 0.19 0.25 C 0.25 c1 0.5 45 (typ.) D 4.8 E 5.8 e 5 6.2 1.27 e3 3.81 F 3.8 4 L 0.4 1.27 M 0.6 S L1 8 (max.) 0.8 Figure 41. SO-8 Package Dimensions 22/31 Max 1.2 VN750-E / VN750S-E / VN750PT-E / VN750B5-E PACKAGE MECHANICAL Table 18. PENTAWATT (VERTICAL) Mechanical Data Symbol millimeters Min Typ A 4.8 C D Max 1.37 2.4 2.8 D1 1.2 1.35 E 0.35 0.55 F 0.8 1.05 F1 1 1.4 G 3.2 3.4 G1 6.6 6.8 H2 H3 3.6 7 10.4 10.05 10.4 L 17.85 L1 15.75 L2 21.4 L3 22.5 L5 2.6 3 L6 15.1 15.8 L7 6 6.6 M 4.5 M1 Diam. 4 3.65 3.85 Figure 42. PENTAWATT (VERTICAL) Package Dimensions 23/31 VN750-E / VN750S-E / VN750PT-E / VN750B5-E PACKAGE MECHANICAL Table 19. P2PAK Mechanical Data Symbol millimeters Min Typ Max A 4.30 4.80 A1 2.40 2.80 A2 0.03 0.23 b 0.80 1.05 c 0.45 0.60 c2 1.17 1.37 D 8.95 9.35 D2 E 8.00 10.00 E1 10.40 8.50 e 3.20 3.60 e1 6.60 7.00 L 13.70 14.50 L2 1.25 1.40 L3 0.90 1.70 L5 1.55 2.40 R V2 0.40 0º Package Weight 8º 1.40 Gr (typ) Figure 43. P2PAK Package Dimensions P010R 24/31 VN750-E / VN750S-E / VN750PT-E / VN750B5-E PACKAGE MECHANICAL Table 20. PPAK Mechanical Data Symbol millimeters Min Typ Max A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 B 0.40 0.60 B2 5.20 5.40 C 0.45 0.60 C2 0.48 0.60 D1 5.1 D 6.00 6.20 E 6.40 6.60 E1 4.7 e 1.27 G 4.90 5.25 G1 2.38 2.70 H 9.35 L2 L4 1.00 0.60 R V2 10.10 0.8 1.00 0.2 0º Package Weight 8º Gr. 0.3 Figure 44. PPAK Package Dimensions P032T1 25/31 VN750-E / VN750S-E / VN750PT-E / VN750B5-E Figure 45. SO-8 TUBE SHIPMENT (no suffix) B Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) C A 100 2000 532 3.2 6 0.6 All dimensions are in mm. Figure 46. SO-8 TAPE AND REEL SHIPMENT (suffix “TR”) REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 12.4 60 18.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 (± 0.1) P D (± 0.1/-0) D1 (min) F (± 0.05) K (max) P1 (± 0.1) All dimensions are in mm. 12 4 8 1.5 1.5 5.5 4.5 2 End Start Top No components Components No components cover tape 500mm min Empty components pockets saled with cover tape. User direction of feed 26/31 500mm min VN750-E / VN750S-E / VN750PT-E / VN750B5-E Figure 47. PENTAWAT TUBE SHIPMENT (no suffix) B C Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) 50 1000 532 18 33.1 1 All dimensions are in mm. A 27/31 VN750-E / VN750S-E / VN750PT-E / VN750B5-E Figure 48. P2PAK TUBE SHIPMENT (no suffix) Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) B C 50 1000 532 18 33.1 1 All dimensions are in mm. A Figure 49. P2PAK TAPE AND REEL SHIPMENT (suffix “TR”) REEL DIMENSIONS Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 1000 330 1.5 13 20.2 24.4 60 30.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 (± 0.1) P D (± 0.1/-0) D1 (min) F (± 0.05) K (max) P1 (± 0.1) All dimensions are in mm. 24 4 16 1.5 1.5 11.5 6.5 2 End Start Top No components Components No components cover tape 500mm min Empty components pockets saled with cover tape. User direction of feed 28/31 500mm min VN750-E / VN750S-E / VN750PT-E / VN750B5-E Figure 50. PPAK SUGGESTED PAD LAYOUT and TUBE SHIPMENT (no suffix) A C Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) B 3 1.8 75 3000 532 6 21.3 0.6 6.7 All dimensions are in mm. Figure 51. PPAK TAPE AND REEL SHIPMENT (suffix “TR”) REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 16.4 60 22.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 (± 0.1) P D (± 0.1/-0) D1 (min) F (± 0.05) K (max) P1 (± 0.1) All dimensions are in mm. 16 4 8 1.5 1.5 7.5 2.75 2 End Start Top No components Components No components cover tape 500mm min Empty components pockets saled with cover tape. 500mm min User direction of feed 29/31 VN750-E / VN750S-E / VN750PT-E / VN750B5-E REVISION HISTORY Table 21. Revision History Date Revision Oct. 2004 1 30/31 Description of Changes - First Issue. VN750-E / VN750S-E / VN750PT-E / VN750B5-E Information furnished is believed to be accurate and reliable. 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