TI THS4511RGTT

THS4511
www.ti.com
SLOS471 – SEPTEMBER 2005
WIDEBAND, LOW NOISE, LOW DISTORTION FULLY DIFFERENTIAL AMPLIFIER
FEATURES
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DESCRIPTION
Fully Differential Architecture
Common-Mode Input Range Includes
the Negative Rail
Unity Gain Stable
Bandwidth: 1.6 GHz (Gain = 0 dB)
Slew Rate: 4900 V/µs
0.1% Settling Time: 3.3 ns
HD2: –72 dBc at 70 MHz
HD3: –87 dBc at 70 MHz
OIP2: 76 dBm at 70 MHz
OIP3: 42 dBm at 70 MHz
Input Voltage Noise: 2 nV/√Hz (f > 10 MHz)
Noise Figure: 21.8 dB (50 Ω System, G = 6 dB)
Output Common-Mode Control
5-V Power Supply Current: 39.2 mA
Power-Down Capability: 0.65 mA
APPLICATIONS
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5-V Data-Acquisition Systems
High Linearity ADC Amplifier
Wireless Communication
Medical Imaging
Test and Measurement
RELATED PRODUCTS
Device
Min. Gain
Common Mode Range
of Input*
THS4508
6 dB
–0.3V to 2.3V
THS4509
6 dB
0.75V to 4.25V
THS4511
0 dB
–0.3V to 2.3V
THS4513
0 dB
0.75V to 4.25V
The THS4511 is a wideband, fully-differential operational amplifier designed for single-supply 5-V
data-acquisition systems. It has very low noise at 2
nV/√Hz, and extremely low harmonic distortion of –72
dBc HD2 and –87 dBc HD3 at 70 MHz with 2 Vpp,
G = 0 dB, and 200-Ω load. Slew rate is very high at
4900 Vµs and with settling time of 3.3 ns to 0.1% (2
V step) it is ideal for pulsed applications. It is
designed for minimum gain of 0 dB.
To allow for dc coupling to ADCs, its unique output
common-mode control circuit maintains the output
common-mode voltage within 5-mV offset (typical)
from the set voltage, when set within ±0.5 V of
mid-supply. The common-mode set point is set to
mid-supply by internal circuitry, which may be
over-driven from an external source.
The THS4511 is a high-performance amplifier that
has been optimized for use in 5-V single supply data
acquisition systems. The output has been optimized
for best performance with its common-mode voltages
set to mid supply, and the input has been optimized
for performance over a wide range of common-mode
input voltages. High performance at a low
power-supply voltage enables single-supply 5-V
data-acquisition systems while minimizing component
count.
The THS4511 is offered in a Quad 16-pin leadless
QFN package (RGT), and is characterized for operation over the full industrial temperature range from
–40°C to 85°C.
Video Buffer, Single-Ended to Differential
Video Source
RS = 75 W
VSignal
VIN
348 W
175 W
130 W
VS+ = 5 V
*Note: Assumes a 5V single-ended power supply
RO
THS4511
175 W
RO
VOD
+
75 W
130 W
VS-
VCM = 2.5 V
348 W
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
THS4511
www.ti.com
SLOS471 – SEPTEMBER 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
UNIT
VSS
Supply voltage
VS– to VS+
VI
Input voltage
VID
Differential input voltage
IO
Output current
5.5 V
±VS
4V
200 mA
Continuous power dissipation
See Dissipation Rating Table
temperature (2)
TJ
Maximum junction
TJ
Maximum junction temperature, continuous operation, long term reliability (3)
150°C
TA
Operating free-air temperature range
–40°C to 85°C
Tstg
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
ESD ratings
(1)
(2)
(3)
125°C
300°C
HBM
2000 V
CDM
1500 V
MM
100 V
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
The maximum junction temperature for continuous operation is limited by the package constraints. Operation above this temperature
may result in reduced reliability and/or lifetime of the device. The THS4511 incorporates a (QFN) exposed thermal pad on the underside
of the chip. This acts as a heatsink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so
may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical brief
SLMA002 and SLMA004 for more information about utilizing the QFN thermally enhanced package.
DISSIPATION RATINGS TABLE PER PACKAGE
(1)
2
PACKAGE (1)
θJC
θJA
RGT (16)
2.4°C/W
39.5°C/W
POWER RATING
TA ≤ 25°C
TA = 85°C
2.3 W
225 mW
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
THS4511
www.ti.com
SLOS471 – SEPTEMBER 2005
DEVICE INFORMATION
THS4511
(RGT PACKAGE)
(TOP VIEW)
VS-
16
15
14
13
NC
1
12
PD
VIN-
2
11
VIN+
VOUT+
3
10
VOUT-
CM
4
9
5
6
7
CM
8
VS+
TERMINAL FUNCTIONS
TERMINAL
(RGT PACKAGE)
NO.
DESCRIPTION
NAME
1
NC
No internal connection
2
VIN–
Inverting amplifier input
3
VOUT+
Noninverted amplifier output
4,9
CM
Common-mode voltage input
5,6,7,8
VS+
Positive amplifier power supply input
10
VOUT–
Inverted amplifier output
11
VIN+
Noninverting amplifier input
12
PD
Powerdown, PD = logic low puts part into low power mode, PD = logic high or open for normal operation
13,14,15,16
VS–
Negative amplifier power supply input
3
THS4511
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SLOS471 – SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS; VS+– VS– = 5 V:
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, G = 0 dB, CM = open, VO = 2 Vpp, RF = 349 Ω, RL = 200 Ω
Differential, T = 25°C Single-Ended Input, Differential Output, Input Referenced to Ground, and Output Referenced to
Mid-supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
TEST
LEVEL (1)
AC PERFORMANCE (Figure 38)
Small-Signal Bandwidth
G = 0 dB, VO = 100 mVpp
1.6
G = 6 dB, VO = 100 mVpp
1.4
G = 0 dB, VO = 2 Vpp
160
G = 6 dB, VO = 2 Vpp
620
Gain-Bandwidth Product
Bandwidth for 0.1-dB flatness
Large-Signal Bandwidth
2
G = 10 dB, VO = 2 Vpp
Slew Rate (Differential)
Rise Time
GHz
MHz
1.35
GHz
4900
V/µs
0.5
ns
Fall Time
0.5
ns
Settling Time to 0.1%
3.3
ns
2nd Order Harmonic Distortion
3rd Order Harmonic Distortion
VO = 2-V Step
GHz
f = 10 MHz
–117
f = 50 MHz
–80
f = 100 MHz
–64
f = 10 MHz
–106
f = 50 MHz
–92
f = 100 MHz
–80
2nd Order Intermodulation Distortion
200 kHz tone spacing,
RL = 100 Ω
3rd Order Intermodulation Distortion
2nd Order Output Intercept Point
200 kHz tone spacing,
RL = 100 Ω
3rd Order Output Intercept Point
fC = 70 MHz
–78
fC = 140 MHz
–56
fC = 70 MHz
–88
fC = 140 MHz
–71.4
fC = 70 MHz
76.3
fC = 140 MHz
53.4
fC = 70 MHz
42
fC = 140 MHz
dBc
C
dBc
dBm
34
fC = 70 MHz
12.2
fC = 140 MHz
10.8
Noise Figure
50-Ω system, 10 MHz
21.8
dB
Input Voltage Noise
f > 10 MHz
2
nV/√Hz
Input Current Noise
f > 10 MHz
1.5
pA/√Hz
1-dB Compression Point (2)
dBm
DC PERFORMANCE
Open-Loop Voltage Gain (AOL)
Input Offset Voltage
63
TA = 25°C
1
4
TA = -40°C to 85°C
1
5
Average Offset Voltage Drift
Input Bias Current
2.3
TA = 25°C
TA = -40°C to 85°C
Average Bias Current Drift
Input Offset Current
Average Offset Current Drift
(1)
(2)
4
1.75
8
15.5
8
18.5
20
TA = 25°C
0.5
3.6
TA = -40°C to 85°C
0.5
7
7
dB
C
mV
A
µA/°C
B
µA
A
nA/°C
B
µA
A
nA/°C
B
Test levels: (A) 100% tested at 25°C. Overtemperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
The 1-dB compression point is measured at the load with 50-Ω double termination. Add 3 dB to refer to amplifier output.
THS4511
www.ti.com
SLOS471 – SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS; VS+– VS– = 5 V: (continued)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, G = 0 dB, CM = open, VO = 2 Vpp, RF = 349 Ω, RL = 200 Ω
Differential, T = 25°C Single-Ended Input, Differential Output, Input Referenced to Ground, and Output Referenced to
Mid-supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
TEST
LEVEL (1)
V
B
dB
B
INPUT
Common-Mode Input Range High
2.3
Common-Mode Input Range Low
-0.3
Common-Mode Rejection Ratio
90
OUTPUT
Maximum Output Voltage High
Each output with 100 Ω
to mid-supply
Minimum Output Voltage Low
Differential Output Voltage Swing
TA = 25°C
3.7
3.8
TA = -40°C to 85°C
3.6
3.8
TA = 25°C
TA = -40°C to 85°C
V
1.2
1.3
1.2
1.4
TA = 25°C
4.8
5.2
TA = -40°C to 85°C
4.4
5.2
A
V
A
Differential Output Current Drive
RL = 20 Ω
61
mA
C
Output Balance Error
VO = 100 mV, f = 1 MHz
-52
dB
C
Closed-Loop Output Impedance
f = 1 MHz
0.3
Ω
C
Small-Signal Bandwidth
250
MHz
Slew Rate
110
V/µs
1
V/V
OUTPUT COMMON-MODE VOLTAGE CONTROL
Gain
Output Common-Mode Offset from CM input
1.25 V < CM < 3.5 V
5
mV
CM Input Bias Current
1.25 V < CM < 3.5 V
±40
µA
1.25 to
3.75
V
32 || 1.5
kΩ || pF
2.5
V
CM Input Voltage Range
CM Input Impedance
CM Default Voltage
CM pins floating
C
POWER SUPPLY
3.75 (3)
Specified Operating Voltage
Maximum Quiescent Current
TA = 25°C
TA = -40°C to 85°C
Minimum Quiescent Current
TA = 25°C
TA = -40°C to 85°C
5
5.25
39.2
42.5
39.2
43.5
35.9
39.2
35
39.2
Power Supply Rejection (±PSRR)
To differential output
POWERDOWN
Referenced to Vs–
Enable Voltage Threshold
Device assured on above 2.1 V + VS–
> 2.1
Disable Voltage Threshold
Device assured off below 0.7 V + VS–
< 0.7
TA = 25°C
0.65
0.9
TA = -40°C to 85°C
0.65
1
Powerdown Quiescent Current
Input Bias Current
PD = VS–
Input Impedance
90
V
C
mA
A
dB
C
V
C
mA
A
100
µA
50 || 2
kΩ || pF
Turn-on Time Delay
Measured to output on
55
ns
Turn-off Time Delay
Measured to output off
10
µs
(3)
C
See the Application Information section of this data sheet for device operation with full supply voltages less than 5 V.
5
THS4511
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SLOS471 – SEPTEMBER 2005
TYPICAL CHARACTERISTICS
TYPICAL AC PERFORMANCE: VS+– VS– = 5 V
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, G = 0 dB, CM = open, VO = 2 Vpp, RF = 349 Ω, RL = 200 Ω
Differential, Single-Ended Input, Input Referenced to Ground and Output Referenced to Midrail
Small-Signal Frequency Response
G = 0 dB, VOD = 100 mVPP
Figure 1
G = 6 dB, VOD = 100 mVPP
Figure 2
Large Signal Frequency Response
G = 0 dB, VOD = 2 VPP
Figure 3
G = 6 dB, VOD = 2 VPP
Figure 4
HD2, G = 0 dB, VOD = 2 VPP
vs Frequency
Figure 5
HD3, G = 0 dB, VOD = 2 VPP
vs Frequency
Figure 6
HD2, G = 6 dB, VOD = 2 VPP
vs Frequency
Figure 7
HD3, G = 6 dB, VOD = 2 VPP
vs Frequency
Figure 8
HD2, G = 0 dB
vs Output Voltage
Figure 9
HD3, G = 0 dB
vs Output Voltage
Figure 10
HD2, G = 0 dB
vs CM Output Voltage
Figure 11
HD3, G = 0 dB
vs CM Output Voltage
Figure 12
IMD2, G = 0 dB
vs Frequency
Figure 13
IMD3, G = 0 dB
vs Frequency
Figure 14
OIP2
vs Frequency
Figure 15
OIP3
vs Frequency
Figure 16
S-Parameters
vs Frequency
Figure 17
Transition Rate
vs Output Voltage
Figure 18
Harmonic
Distortion
Intermodulation
Distortion
Output Intercept Point
Transient Response
Figure 19
Settling Time
Figure 20
Rejection Ratio
vs Frequency
Figure 21
Output Impedance
vs Frequency
Figure 22
Overdrive Recovery
Differential Output Voltage
Figure 23
Load Resistance
Turn-Off Time
Figure 24
Figure 25
Turn-On Time
Figure 26
Input Offset Voltage
vs Input Common-Mode Voltage
Figure 27
Open Loop Gain & Phase
vs Frequency
Figure 28
Input Referred Noise
vs Frequency
Figure 29
Noise Figure
vs Frequency
Figure 30
Quiescent Current
vs Supply Voltage
Figure 31
Output Balance Error
vs Frequency
Figure 32
CM Input Impedance
vs Frequency
Figure 33
CM Small-Signal Frequency Response
Figure 34
CM Input Bias Current
vs CM Input Voltage
Figure 35
Differential Output Offset Voltage
vs CM Input Voltage
Figure 36
Output Common-Mode Offset
vs CM Input Voltage
Figure 37
6
THS4511
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SLOS471 – SEPTEMBER 2005
SMALL-SIGNAL FREQUENCY RESPONSE
SMALL-SIGNAL FREQUENCY RESPONSE
7
5
VO = 100 mV PP
VO = 100 mV PP
G = 0 dB
4
6
RL = 1 kΩ
RL = 500 Ω
3
RL = 200 Ω
G = 6 dB
Signal Gain − dB
Signal Gain − dB
RL = 1 kΩ
RL = 500 Ω
5
2
1
0
−1
RL = 100 Ω
−2
4
RL = 200 Ω
3
RL = 100 Ω
2
−3
−4
1
−5
−6
0
10
100
1000
f− Frequency −MHz
10000
10
100
1000
Figure 1.
Figure 2.
LARGE SIGNAL FREQUENCY RESPONSE
LARGE SIGNAL FREQUENCY RESPONSE
8
4
VO = 2 VPP
G = 0 dB
3
VO = 2 VPP
G = 6 dB
7
RL = 1 kΩ
RL = 500 Ω
2
6
1
Signal Gain − dB
Signal Gain − dB
10000
f− Frequency −MHz
0
RL = 200 Ω
RL = 100 Ω
−1
−2
−3
RL = 1 kΩ
RL = 500 Ω
5
4
3
RL = 200 Ω
2
RL = 100 Ω
−4
1
−5
0
−6
10
100
1000
f− Frequency −MHz
10
10000
100
1000
Figure 3.
Figure 4.
HD2 vs Frequency
HD3 vs Frequency
−70
−60
VO = 2 VPP
G = 0 dB
VO = 2 VPP
G = 0 dB
3rd Order Harmonic Distortion − dBc
2nd Order Harmonic Distortion − dBc
10000
f− Frequency −MHz
−70
−80
−90
RL = 1 kΩ
RL = 100 Ω
−100
RL = 500 Ω
−110
−80
−90
RL = 1kΩ
RL = 200 Ω
−100
RL = 500 Ω
RL = 200 Ω
−120
1
10
100
f − Frequency − MHz
Figure 5.
1000
−110
RL = 100 Ω
1
10
100
1000
f − Frequency − MHz
Figure 6.
7
THS4511
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SLOS471 – SEPTEMBER 2005
HD2 vs Frequency
G = 6 dB
RF = 348 Ω
RG = 165 Ω
VO = 2 VPP
−60
HD3 vs Frequency
−70
3rd Order Harmonic Distortion − dBc
2nd Order Harmonic Distortion − dBc
−50
RL = 500 Ω
−70
−80
RL = 1kΩ
RL = 100 Ω
−90
−100
−110
−120
G = 6 dB
RF = 348 Ω
RG = 165 Ω
VO = 2 VPP
−80
RL = 100 Ω
−90
L
RL = 500 Ω
−100
RL = 200 Ω
−130
1
10
100
f − Frequency − MHz
−110
1000
10
1
100
1000
f − Frequency − MHz
Figure 7.
Figure 8.
HD2 vs OUTPUT VOLTAGE
−40
HD3 vs OUTPUT VOLTAGE
−40
f = 150 MHz
VOD = 2 VPP
f = 150 MHz
VOD = 2 VPP
−50
3rd Order Harmonic Distortion − dBc
2nd Order Harmonic Distortion − dBc
= 200 Ω
RL = 1k Ω
f = 100 MHz
−60
f = 64 MHz
−70
f = 32 MHz
−80
f = 8 MHz
−90
f = 16 MHz
−100
−110
−50
f = 100 MHz
−60
f = 64 MHz
−70
f = 8 MHz
−80
f = 32 MHz
−90
f = 16 MHz
−100
−110
−120
0
1
2
3
VO − Output Voltage − VPP
4
−120
5
0
1
2
3
4
5
VO − Output Voltage− V PP
Figure 9.
Figure 10.
HD2 vs CM OUTPUT VOLTAGE
HD3 vs CM OUTPUT VOLTAGE
0
0
−20
3rd Order Harmonic Distortion − dBc
2nd Order Harmonic Distortion − dBc
f = 150 MHz
f = 100 MHz
−40
f = 64 MHz
−60
−80
f = 1 MHz
−100
−120
−0.8
−0.6
−0.4
−0.2
f = 64 MHz
0
0.2
0.4
Figure 11.
f = 32 MHz
−60
−80
−100
f = 4 MHz
f = 1 MHz
f = 8 MHz
0.6
VCM − Common-Mode Output Voltage − V
8
−40
f = 4 MHz
f = 8 MHz
−140
−1
f = 100 MHz
−120
f = 32 MHz
f = 150 MHz
−20
0.8
1
−140
−1
−0.8 −0.6
−0.4
−0.2
0
0.2
0.4
0.6
VCM − Common-Mode Output Voltage − V
Figure 12.
0.8
1
THS4511
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SLOS471 – SEPTEMBER 2005
IMD2 vs FREQUENCY
IMD3 vs FREQUENCY
−40
−60
IMD 2 − Intermodulation Distortion − dBc
VOD = 2V PP Envelope
200 kHz Tone Spacing
IMD 3 − Intermodulation Distortion − dBc
−50
RL = 200 Ω
−60
−70
RL = 1 kΩ
−80
RL = 100 Ω
−90
VOD = 2V PP Envelope
200 kHz Tone Spacing
−65
−70
RL = 100 Ω
−75
RL = 1 kΩ
−80
−85
−90
−95
RL = 200 Ω
−100
−105
−110
−100
0
50
100
150
0
200
50
100
Figure 13.
200
Figure 14.
OIP2 vs FREQUENCY
OIP3 vs FREQUENCY
95
50
OIP3 − Output Intercept Point − dBm
RL = 100 Ω
VOD = 2V PP Envelope
200 kHz Tone Spacing
90
OIP2 − Output Intercept Point − dBm
150
f − Frequency − MHz
f − Frequency − MHz
85
80
75
70
65
60
55
RL = 100 Ω
VOD = 2V PP Envelope
200 kHz Tone Spacing
45
40
35
30
50
45
25
0
50
100
150
0
200
Figure 15.
Figure 16.
S-PARAMETERS vs FREQUENCY
150
200
TRANSITION RATE vs OUTPUT VOLTAGE
6000
RL = 200 Ω
20% - 80%
10
0
5000
S21
SR − Transition Rate − V/ms
S−Parameter − dB
100
f − Frequency − MHz
20
−10
S22
−20
−30
S11
−40
−50
−60
50
f − Frequency − MHz
S12
−70
Falling
4000
Rising
3000
2000
1000
−80
−90
0.1
0
1
10
f − Frequency − MHz
Figure 17.
100
1000
0
0.5
1
1.5
2
2.5
3
VOD − Output Voltage − V PP
Figure 18.
9
THS4511
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SLOS471 – SEPTEMBER 2005
TRANSIENT RESPONSE
SETTLING TIME
4
0.5
3.5
0.3
Percent of Final Value - %
V OD − Differential Output Voltage − V
VOD = 2 VPP
3
2.5
2
0.1
-0.1
-0.3
1.5
1
-0.5
t - Time - 1ns/div
t − Time − 500 ps/div
Figure 19.
Figure 20.
REJECTION RATIOS vs FREQUENCY
OUTPUT IMPEDANCE vs FREQUENCY
100
100
PSRR+
90
Z o − Output Impedance − Ω
Rejection Ratio −dB
80
70
CMRR
60
50
40
30
20
10
1
10
0
0.01
0.1
10
1
100
1000
0.1
0.1
f − Frequency − MHz
100
Figure 22.
OVERDRIVE RECOVERY
DIFFERENTIAL OUTPUT VOLTAGE
vs LOAD RESISTANCE
4
3
2.4
2
Output
1
1.4
0
−1
0.4
−2
−3
−4
−0.6
t − Time − 100 ns/div
Figure 23.
1000
7
VOD - Differential Output Voltage Swing - V
Input
V O − Output Voltage − V
10
f − Frequency− MHz
Figure 21.
3.4
10
1
6
5
4
3
2
1
0
10
100
RL - Load Resistance - kW
Figure 24.
1000
THS4511
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SLOS471 – SEPTEMBER 2005
PD Input
0.4
0
Output
t - Time - (2.5 ms/div)
t - Time - (2.5 ms/div)
Figure 25.
Figure 26.
INPUT OFFSET VOLTAGE
vs
INPUT COMMON-MODE VOLTAGE
OPEN-LOOP GAIN AND PHASE
vs FREQUENCY
10
9
80
90
70
50
8
10
60
7
Open-loop Gain - dB
VOS - Input Offset Voltage - mV
6.4
6
5.6
5.2
4.8
4.4
4
3.6
3.2
2.8
2.4
2
1.6
1.2
0.8
0.4
0
PD Input
Powerdown Input - V
Output
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
6
5
4
3
GAIN
-30
50
PHASE
40
-70
30
-110
20
-150
10
-190
Phase - Degrees
VO - Output Voltage - V
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
VO - Output Voltage - V
TURN-ON TIME
6.4
6
5.6
5.2
4.8
4.4
4
3.6
3.2
2.8
2.4
2
1.6
1.2
0.8
Powerdown Input - V
TURN-OFF TIME
3.2
2
1
0
-0.5
0
0.5
0
1
2
1.5
2.5
3
-230
100
1M
10K
VIC - Commom-Mode Input Voltage - V
100M
10G
f - Frequency - Hz
Figure 27.
Figure 28.
INPUT REFERRED NOISE vs FREQUENCY
NOISE FIGURE vs FREQUENCY
1000
25
24
100
Input Current Noise
NF - Noise Figure - dB
Vn - Voltage Noise - V/rt(Hz)
In - Current Noise - pA/rt(Hz)
50-W System
G = 6 dB
10
Input Voltage Noise
1
0
23
22
21
20
10
100
1k
10k
100k
f - Frequency - Hz
Figure 29.
1M
10M
0
20
40
60
80
100
120
140
160
180
200
f - Frequency - MHz
Figure 30.
11
THS4511
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SLOS471 – SEPTEMBER 2005
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
OUTPUT BALANCE ERROR
vs
FREQUENCY
44
-20
VOD = 500 mVPP
TA = 25o C
42
-25
-30
Balance Error - dB
IQ - Quiescent Current - mA
o
TA = 85 C
40
38
36
TA = -40o C
34
-35
-40
-45
32
-50
30
-55
28
3.75
4.25
4
4.5
4.75
5
-60
100k
5.25
1M
VS - Supply Voltage - V
10M
100M
10G
f - Frequency - Hz
Figure 31.
Figure 32.
CM INPUT IMPEDANCE
vs
FREQUENCY
CM SMALL-SIGNAL FREQUENCY RESPONSE
100
2
0
VOCM - Gain - dB
CM Input Impedance − kW
1
10
1
-1
-2
0.1
-3
-4
0.01
100k
1M
10M
f − Frequency − Hz
Figure 33.
12
100M
1G
100k
1M
10M
f - Frequency - Hz
Figure 34.
100M
10G
THS4511
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SLOS471 – SEPTEMBER 2005
CM INPUT BIAS CURRENT
vs
CM INPUT VOLTAGE
DIFFERENTIAL OUTPUT OFFSET VOLTAGE
vs CM INPUT VOLTAGE
5
Differential Output Offset Voltage - mV
100
0
-100
-200
-300
4
3
2
1
0
-1
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0
5
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VIC - Common-Mode Input Voltage - V
VIC - Common-Mode Input Voltage - V
Figure 35.
Figure 36.
OUTPUT COMMON-MODE OFFSET
vs CM INPUT VOLTAGE
VOC - Common-Mode Output Offset Voltage - mV
Common-Mode Input-Bias Current - mA
200
50
40
30
20
10
0
-10
-20
-30
-40
-50
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VIC - Common-Mode Input Voltage - V
Figure 37.
13
THS4511
www.ti.com
SLOS471 – SEPTEMBER 2005
TEST CIRCUITS
The THS4511 is tested with the following test circuits
built on the EVM. For simplicity, the power supply
decoupling is not shown – see the layout in the
application information section for recommendations.
Depending on the test conditions, component values
are changed per the following tables, or as otherwise
noted. The signal generators used are ac coupled
50-Ω sources and a 0.22-µF capacitor and a 49.9-Ω
resistor to ground are inserted across RIT on the
alternate input to balance the circuit.
Table 1. Gain Component Values
From
50 W
Source
RF
RG
RIT
5V
49.9 W
RG
0.22 mF
THS4511
49.9 W
CM
RIT
100 W
Output Measured
Here With High
Impedance
Differential Probe
Open
0.22 mF
49.9 W
RF
Figure 38. Frequency Response Test Circuit
Distortion and 1dB Compression
GAIN
RF
RG
RIT
0 dB
348 Ω
340 Ω
56.2 Ω
6 dB
348 Ω
165 Ω
61.9 Ω
Note the gain setting includes 50-Ω source impedance. Components are chosen to achieve gain
and 50-Ω input termination.
Table 2. Load Component Values
RL
RO
ROT
100 Ω
25 Ω
open
Atten.
6 dB
200 Ω
86.6 Ω
69.8 Ω
16.8 dB
499 Ω
237 Ω
56.2 Ω
25.5 dB
1k Ω
487 Ω
52.3 Ω
31.8 dB
Note the total load includes 50-Ω termination by
the test equipment. Components are chosen to
achieve load and 50-Ω line termination through a
1:1 transformer.
Due to the voltage divider on the output formed by
the load component values, the amplifier's output is
attenuated. The column Atten in Table 2 shows the
attenuation expected from the resistor divider. When
using a transformer at the output as shown in
Figure 39, the signal will see slightly more loss, and
these numbers will be approximate.
The circuit shown in Figure 39 is used to measure
harmonic distortion, intermodulation distortion, and
1-db compression point of the amplifier.
A signal generator is used as the signal source and
the output is measured with a spectrum analyzer. The
output impedance of the signal generator is 50 Ω. RIT
and RG are chosen to impedance-match to 50 Ω, and
to maintain the proper gain. To balance the amplifier,
a 0.22-µF capacitor and 49.9-Ω resistor to ground are
inserted across RIT on the alternate input.
A low-pass filter is inserted in series with the input to
reduce harmonics generated at the signal source.
The level of the fundamental is measured, then a
high-pass filter is inserted at the output to reduce the
fundamental so that it does not generate distortion in
the input of the spectrum analyzer.
The transformer used in the output to convert the
signal from differential to single ended is an
ADT1-1WT. It limits the frequency response of the
circuit so that measurements cannot be made below
approximately 1MHz.
From
50 W
Source
The circuit shown in Figure 38 is used to measure the
frequency response of the circuit.
A network analyzer is used as the signal source and
as the measurement device. The output impedance
of the network analyzer is 50 Ω. RIT and RG are
chosen to impedance match to 50 Ω, and to maintain
the proper gain. To balance the amplifier, a 0.22-µF
capacitor and 49.9-Ω resistor to ground are inserted
across RIT on the alternate input.
The output is probed using a high-impedance differential probe across the 100-Ω resistor. The gain is
referred to the amplifier output by adding back the
6-dB loss due to the voltage divider on the output.
VIN
RF
RG
RIT
5V
RO
RG
Frequency Response
14
VIN
0.22 mF
RIT
THS4511
CM
49.9 W
RO
1:1
VOUT
ROT
To 50 W
Test
Equipment
Open
0.22 mF
RF
Figure 39. Distortion Test Circuit
The 1-dB compression point is measured with a
spectrum analyzer with 50-Ω double termination or
100-Ω termination as shown in Table 2. The input
power is increased until the output is 1 dB lower than
expected. The number reported in the table data is
the power delivered to the spectrum analyzer input.
Add 3 dB to refer to the amplifier output.
THS4511
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SLOS471 – SEPTEMBER 2005
S-Parameter, Slew Rate, Transient Response, Settling Time, Output Impedance, Overdrive, Output
Voltage, and Turn-On/Off Time
The circuit shown in Figure 40 is used to measure
s-parameters, slew rate, transient response, settling
time, output impedance, overdrive recovery, output
voltage swing, and turn-on/turn-off times of the amplifier. For output impedance, the signal is injected at
VOUT with VIN left open and the drop across the 49.9
Ω resistor is used to calculate the impedance seen
looking into the amplifier’s output.
Because S21 is measured single-ended at the load
with 50-Ω double termination, add 12 dB to refer to
the amplifier’s output as a differential signal.
From V IN
50-W
Source
RG
R IT
RF
THS4511
49.9 W
VOUT-
R IT
0.22 mF
RIT
5V
49.9 W
49.9 W
VOUT–
RG
0.22 mF
THS4511
49.9 W
VOUT+
CM
RIT
To
50-W
Test
Equipment
RCM
VIN
49.9 W
RCMT
RF
From
50-W
source
Figure 41. CM Input Test Circuit
VOUT+
0.22 mF
RF
RG
5V
49.9 W
RG
at VOUT+ or VOUT– with the input injected at VIN, RCM =
0 Ω and RCMT = 49.9 Ω. The input impedance is
measured with RCM = 49.9 Ω with RCMT = open, and
calculated by measuring the voltage drop across RCM
to determine the input current.
CM
49.9 W
To 50-W
Test
Equipment
Open
0.22 mF
CMRR and PSRR
The circuit shown in Figure 42 is used to measure the
CMRR and PSRR of VS+ and VS–. The input is
switched appropriately to match the test being performed.
RF
Figure 40. S-Parameter, SR, Transient Response,
Settling Time, ZO, Overdrive Recovery, VOUT
Swing, and Turn-on/off Test Circuit
CM Input
The circuit shown in Figure 41 is used to measure the
frequency response and input impedance of the CM
input. Frequency response is measured single-ended
348 W
VS+
PSRR+
From VIN
50 W
CMRR
Source
5V
49.9 W
100 W
100 W
PSRRVS-
THS4511
CM
69.8 W
49.9 W
100 W
Open
0.22 mF
Output
Measured
Here
With High
Impedance
Differential
Probe
348 W
Figure 42. CMRR and PSRR Test Circuit
15
THS4511
www.ti.com
SLOS471 – SEPTEMBER 2005
APPLICATION INFORMATION
APPLICATIONS
Single-Ended
Input
The following circuits show application information for
the THS4511. For simplicity, power supply decoupling
capacitors are not shown in these diagrams. For
more detail on the use and operation of fully differential operational amplifiers refer to application report
Fully-Differential Amplifiers (SLOA054) .
RG
RF
Differential
5V
Output
+
RG
–
VOUT–
THS4511
–
+
VOUT+
Differential Input to Differential Output Amplifier
The THS4511 is a fully differential operational amplifier, and can be used to amplify differential input
signals to differential output signals. A basic block
diagram of the circuit is shown in Figure 43 (CM input
not shown). The gain of the circuit is set by RF
divided by RG.
RF
Differential
Input
5V
RG
+
V IN+
VIN–
Differential
Output
–
– +
VOUT+
RF
Figure 43. Differential Input to Differential Ouput
Amplifier
Depending on the source and load, input and output
termination can be accomplished by adding RIT and
RO.
Single-Ended
Amplifier
Input
to
Differential
Output
The THS4511 can be used to amplify and convert
single-ended input signals to differential output signals. A basic block diagram of the circuit is shown in
Figure 44 (CM input not shown). The gain of the
circuit is again set by RF divided by RG.
16
Figure 44. Single-Ended Input to Differential
Output Amplifier
Input Common-Mode Voltage Range
The input common-model voltage of a fully differential
operational amplifier is the voltage at the (+) and (–)
input pins of the operational amplifier.
It is important to not violate the input common-mode
voltage range (VICR) of the operational amplifier.
Assuming the operational amplifier is in linear operation the voltage across the input pins is only a few
millivolts at most. So finding the voltage at one input
pin determines the input common-mode voltage of
the operational amplifier.
VOUT–
THS4511
RG
RF
Treating the negative input as a summing node, the
voltage is given by Equation 1:
ö
æ
ö æ
RG
RF
÷
÷ + ç VIN- ´
VIC = çç VOUT + ´
ç
÷
R G + R F ÷ø
R G + RF ø è
è
(1)
To determine the VICR of the operational amplifier, the
voltage at the negative input is evaluated at the
extremes of VOUT+.
As the gain of the operational amplifier increases, the
input common-mode voltage becomes closer and
closer to the input common-mode voltage of the
source.
THS4511
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SLOS471 – SEPTEMBER 2005
Setting the Output Common-Mode Voltage
The output common-mode voltage is set by the
voltage at the CM pin(s). The internal common-mode
control circuit maintains the output common-mode
voltage within 5-mV offset (typical) from the set
voltage, when set within 0.5 V of mid-supply. If left
unconnected, the common-mode set point is set to
mid-supply by internal circuitry, which may be
over-driven from an external source. Figure 45 is
representative of the CM input. The internal CM
circuit has about 700 MHz of –3-dB bandwidth, which
is required for best performance, but it is intended to
be a dc-bias input pin. Bypass capacitors are recommended on this pin to reduce noise at the output.
The external current required to overdrive the internal
resistor divider is given by Equation 2:
IEXT =
2VCM - (VS + - VS - )
50 kW
(2)
where VCM is the voltage applied to the CM pin, and
VS+ ranges from 3.75 V to 5 V, and VS- is 0 V
(ground).
VS+
50 kW
to internal
CM circuit
I EXT
operational amplifier. Note RS and RIT are added to
the alternate input from the signal input to balance
the amplifier. One resistor that is equal to the
combined value RI = RG + RS||RIT can be placed at
the alternate input.
RS
RG
VSignal
RIT
RF
RPD
VS+ = 3.75 V to 5 V
RO
THS4511
RG
RO
VOUTVOUT+
CM
RS
RIT
RPD
VS–
VCM
RF
Figure 46. THS4511 DC Coupled Single-Source
Supply Range From 3.75 V to 5 V With RPD Used
To Set VIC
Note that in Figure 46, the source is referenced to
ground as is the input termination resistor RIT. The
proper value of resistance to add can be calculated
from Equation 3:
RPD =
CM
50 kW
1
é
1 ê
1 .6
êV
R F ê S + - 1 .6
êë 2
ù
ú
1
ú RI
ú
úû
(3)
V S–
Figure 45. CM Input Circuit
Device Operation with Single Power Supplies
Less than 5 V
The THS4511 is optimized to work in systems using
5-V single supplies, and the characterization data
presented in this data sheet was taken with 5-V
single-supply inputs. For ac-coupled systems or
dc-coupled systems operating with supplies less than
5 V and greater than 3.75 V, the amplifier input
common-mode range is maximized by adding
pull-down resistors at the device inputs. The
pull-down resistors provide additional loading at the
input, and lower the common-mode voltage that is fed
back into the device input through resistor RF.
Figure 46 shows the circuit configuration for this
mode of operation where RPD is added to the
dc-coupled circuit to avoid violating the VICR of the
where RI = RG + RS||RIT.
VS+ is the power-supply voltage, RF is the feedback
resistance, RG is the gain-setting resistance, RS is the
signal source resistance, and RIT is the termination
resistance.
Table 3 is a modification of Table 1 to add the proper
values with RPD assuming VS+ = 3.75 V, a dc-coupled
50-Ω source impedance, and setting the output common-mode voltage to mid-supply.
Table 3. RPD Values for Various Gains,
VS+ = 3.75 V, DC-coupled Signal Source
Gain
RF
RG
RIT
RPD
0 dB
348 Ω
340 Ω
56.2 Ω
422 Ω
6 dB
348 Ω
169 Ω
64.9 Ω
86.6 Ω
If the signal originates from an ac-coupled 50-Ω
source (see Figure 47), the equivalent dc-source
resistance is an open circuit and RI = RG + RIT.
Table 4 is a modification of Table 1 to add the proper
values with RPD assuming VS+ = 3.75 V, an
ac-coupled 50-Ω source impedance, and setting the
output common-mode voltage to mid-supply.
17
THS4511
www.ti.com
SLOS471 – SEPTEMBER 2005
Table 4. RPD Values for Various Gains,
VS+ = 3.75 V, AC-coupled Signal Source
Gain
RF
RG
RIT
RPD
0 dB
348 Ω
340 Ω
56.2 Ω
390 Ω
6 dB
348 Ω
169 Ω
64.9 Ω
80.6 Ω
Video Source
RS = 75 W
VSignal
VIN
348 W
175 W
130 W
VS+ = 5 V
RO
-
C
RS
RIT
V Signal
RPD
RO
THS4511
175 W
RF
RG
VOD
+
VS+ = 3.75 V to 5 V
75 W
130 W
VCM = 2.5 V
VS-
RO
V OUTTHS4511
RG
V OUT+
C
RS
RIT
RO
RPD
V S-
348 W
Figure 48. Single-Supply Video Buffer, Gain = 2
CM
0.8
RF
Figure 48 shows a possible application of the
THS4508 as a DC-coupled video buffer with a gain of
2. Figure 49 shows a plot of the Y' signal originating
from a HDTV 720p video system. The input signal
includes a tri-level sync (minimum level at –0.3 V)
and the portion of a video signal with maximum
amplitude of 0.7 V. Although the buffer draws its
power from a 5V single-ended power supply, internal
level shifters allow the buffer to support input signals
which are as much as –0.3 V below ground. This
allows maximum design flexibility while maintaining a
minimum parts count. Figure 50 shows the differential
output of the buffer. Note that the DC-coupled amplifier can introduce a DC offset on a signal applied at
its input.
0.4
Voltage - V
Video Buffer
0.6
0.2
0
-0.2
-0.4
0
5
10
15
20
t - Time - ms
Figure 49. Y' Signal with 3-Level Sync and Video
Signal
1.5
VOD - Video Buffer Output - V
Figure 47. THS4511 AC Coupled Single-Source
Supply Range From 3.75 V to 5 V With RPD Used
To Set VIC
1
0.5
0
-0.5
-1
0
5
10
15
20
t - Time - ms
Figure 50. Video Buffer Differential Output Signal
18
THS4511
www.ti.com
SLOS471 – SEPTEMBER 2005
THS4511 + ADS5500 Combined Performance
THS4511 + ADS5424 Combined Performance
The THS4511 is designed to be a high performance
drive amplifier for high performance data converters
like the ADS5500 14-bit 125-MSPS ADC. Figure 51
shows a circuit combining the two devices. The
THS4511 amplifier circuit provides 0 dB of gain, and
converts the single-ended input signal to a differential
output signal. The default common-mode output of
the THS4511 (2.5 V) is not compatible with the
required common-mode input of the ADS5500 (1.55
V), so dc-blocking capicitors are added (0.22 µF).
Note that a biasing circuit (not shown in Figure 51) is
needed to provide the required common-mode,
dc-input for the ADS5500. The 100-Ω resistors and
2.7-pF capacitor between the THS4511 outputs and
ADS5500 inputs along with the input capacitance of
the ADS5500 limit the bandwidth of the signal to 115
MHz (–3 dB). For testing, a signal generator is used
for the signal source. The generator is an ac-coupled
50-Ω source. A band-pass filter is inserted in series
with the input to reduce harmonics and noise from the
signal source. Input termination is accomplished via
the 69.8-Ω resistor and 0.22-µF capacitor to ground
in conjunction with the input impedance of the amplifier circuit. A 0.22-µF capacitor and 49.9-Ω resistor is
inserted to ground across the 69.8-Ω resistor and
0.22-µF capacitor on the alternate input to balance
the circuit. Gain is a function of the source impedance, termination, and 348-Ω feedback resistor.
See Table 1 for component values to set proper 50-Ω
termination for other common gains.
Figure 52 shows the THS4511 driving the ADS5424
ADC.
From
50-W
source
VIN
As before, the THS4511 amplifier provides 0 dB of
gain, converts the single-ended input to differential,
and sets the proper input common-mode voltage to
the ADS5424. Input termination and circuit testing is
the same as described above for the THS4511 +
ADS5500 circuit.
The 225-Ω resistors and 2.7-pF capacitor between
the THS4511 outputs and ADS5424 inputs (along
with the input capacitance of the ADC) limit the
bandwidth of the signal to about 100MHz (-3dB).
When the THS4511 is operated from a single power
supply with VS+ = 5 V and VS- = ground, the 2.5-V
output common-mode voltage is compatable with the
recommended value of the ADS5424 input common-mode voltage (2.4 V).
From
50-W
source
V IN
348 W
340 W
56.2 W
5V
225 W
340
49 .9 W
56.2 W
THS4511
225 W
2 .7 pF
CM
0.22 mF
348 W
14-bit,
105 MSPS
A IN+
ADS5424
A IN– VBG
49.9 W
0.1 mF
0.1 mF
Figure 52. THS4511 + ADS5424 Circuit
340 W
56.2 W
348 W
5V
0.22 mF
100 W
14-bit,
125 MSPS
A IN +
340 W
49.9 W
56.2 W
THS4511
2.7 pF
ADS5500
A IN - CM
CM
0.22 mF
0.22 mF
100 W
0.1 mF
348 W
Figure 51. THS4511 + ADS5500 Circuit
19
THS4511
www.ti.com
SLOS471 – SEPTEMBER 2005
Layout Recommendations
It is recommended to follow the layout of the external
components near the amplifier, ground plane construction, and power routing of the EVM as closely as
possible. General guidelines are:
1. Signal routing should be direct and as short as
possible into and out of the operational amplifier
circuit.
2. The feedback path should be short and direct
avoiding vias.
3. Ground or power planes should be removed from
directly under the amplifier’s input and output
pins.
4. An output resistor is recommended on each
output, as near to the output pin as possible.
5. Two 10-µF and two 0.1-µF power-supply decoupling capacitors should be placed as near to the
power-supply pins as possible.
6. Two 0.1-µF capacitors should be placed between
the CM input pins and ground. This limits noise
coupled into the pins. One each should be placed
to ground near pin 4 and pin 9.
7. It is recommended to split the ground pane on
layer 2 (L2) as shown below and to use a solid
ground on layer 3 (L3). A single-point connection
should be used between each split section on L2
20
and L3.
8. A single-point connection to ground on L2 is
recommended for the input termination resistors
R1 and R2. This should be applied to the input
gain resistors if termination is not used.
9. The THS4511 recommended PCB footprint is
shown in Figure 53.
0.144
0.049
0.012
Pin 1
0.0095
0.015
0.144
0.0195 0.0705
0.010
vias
0.032
0.030
0.0245
Top View
Figure 53. QFN Etch and Via Pattern
THS4511
www.ti.com
SLOS471 – SEPTEMBER 2005
THS4511 EVM
Figure 54 is the THS4511 EVAL1 EVM schematic, layers 1 through 4 of the PCB are shown in ADDREFS
through ADDREFS , and Table 5 is the bill of material for the EVM as supplied from TI.
GND
TP1
VS+
J5
J6
VCC
J8
R5
348 W
R1
56.2 W
R3
J1
C15
R12
49.9 W
12
2
3
VO+
-
U1 11
+
R4
340 W
R2
56.2 W
TP2
C14
0.1 mF
4
VOPwrPad 10
R7
86.6 W
R8
86.6 W
15 13
14 16
R6
C5
6
C12
C13
1
5
4
0.1 mF
VCC
3
XFMR_ADT1-1WT
Vocm
9
0.1 mF
J3
T1
R11
69.8 W
10 mF
C3
R9
open
7
PD
340 W
0.22 mF
J2
VCC
8
6
5
10 mF
R10
open
C1
open
J7
348 W
TP3
C11
0.1 mF
C8
open
C7
open
C2
open
Figure 54. THS4511 EVAL1 EVM Schematic
21
THS4511
www.ti.com
SLOS471 – SEPTEMBER 2005
Table 5. THS4511RGT EVM Bill of Materials
ITEM
(1)
DESCRIPTION
SMD
SIZE
REFERENCE
DESIGNATOR
PCB
QTY
MANUFACTURER'S
PART NUMBER (1)
1
CAP, 10.0 µF, Ceramic, X5R, 6.3V
0805
C3, C5
2
(AVX) 08056D106KAT2A
2
CAP, 0.1 µF, Ceramic, X5R, 10V
0402
C11, C12, C13, C14
4
(AVX) 0402ZD104KAT2A
3
CAP, 0.22 µF, Ceramic, X5R, 6.3V
0402
C15
1
(AVX) 04026D224KAT2A
4
OPEN
0402
C1, C2, C7, C8, C9, C10
6
5
OPEN
0402
R9, R10
2
6
Resistor, 49.9 Ω, 1/16W, 1%
0402
R12
1
7
Resistor, 56.2 Ω, 1/16W, 1%
0402
R1, R2
8
Resistor, 69.8 Ω, 1/16W, 1%
0402
R11
3
(KOA) RK73H1ETTP69R8F
9
Resistor, 86.6 Ω, 1/16W, 1%
0402
R7, R8
2
(KOA) RK73H1ETTP86R6F
10
Resistor, 340 Ω, 1/16W, 1%
0402
R3, R4
2
(KOA) RK73H1ETTP3400F
11
Resistor, 348 Ω, 1/16W, 1%
0402
R5, R6
2
(KOA) RK73H1ETTP3480F
12
Resistor, 0 Ω, 5%
0805
C4, C6
2
(KOA) RK73Z2ATTD
13
Transformer, RF
T1
1
(MINI-CIRCUITS) ADT1-1WT
14
Jack, banana receptance, 0.25" diameter
hole
J5, J6
15
OPEN
J1, J7, J8
3
16
Connector, edge, SMA PCB Jack
J2, J3
2
(JOHNSON) 142-0701-801
17
Test point, Red
TP1, TP2, TP3
3
(KEYSTONE) 5000
18
IC, THS4511
U1
1
(TI) THS4511RGT
19
Standoff, 4-40 HEX, 0.625" length
4
(KEYSTONE) 1808
20
SCREW, PHILLIPS, 4-40, 0.250"
4
SHR-0440-016-SN
21
Printed circuit board
1
(TI) EDGE# 6475513
(KOA) RK73H1ETTP49R9F
(KOA) RK73H1ETTP56R2F
2
(HH SMITH) 101
The manufacturer's part numbers were used for tesr purposes only.
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input and output voltage ranges as specified in the table provided
below.
Input Range, VS+ to VS-
3.0 V to 6.0 V
Input Range, VI
3.0 V to 6.0 V NOT TO EXCEED VS+ or VS-
Output Range, VO
3.0 V to 6.0 V NOT TO EXCEED VS+ or VS-
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If
there are questions concerning the input range, please contact a TI field representative prior to connecting the
input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible
permanent damage to the EVM. Please consult the product data sheet or EVM user's guide (if user's guide is
available) prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 30°C. The EVM is
designed to operate properly with certain components above 50°C as long as the input and output ranges are
maintained. These components include but are not limited to linear regulators, switching transistors, pass
transistors, and current sense resistors. These types of devices can be identified using the EVM schematic
located in the material provided. When placing measurement probes near these devices during operation, please
be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265
22
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
THS4511RGTR
ACTIVE
QFN
RGT
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS4511RGTRG4
ACTIVE
QFN
RGT
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS4511RGTT
ACTIVE
QFN
RGT
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS4511RGTTG4
ACTIVE
QFN
RGT
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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