Freescale Semiconductor
Document Number: MPC8250EC
Rev. 2, 07/2009
MPC8250
Hardware Specifications
This document contains detailed information on power
considerations, DC/AC electrical characteristics, and AC
timing specifications for the MPC8250 PowerQUICC II™
communications processor.
The following topics are addressed:
The MPC8250 is available in two packages—the standard
TBGA package (480 pins) and an alternate PBGA package
(516 pins)—as described in Section 4, “Pinout,” and
Section 5, “Package Description.” For more information on
PBGA packages, contact your Freescale sales office. Note
that throughout this document references to the MPC8250
are inclusive of its PBGA version unless otherwise specified.
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2003, 2005, 2009. All rights reserved.
1.
2.
3.
4.
5.
6.
7.
Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Electrical and Thermal Characteristics . . . . . . . . . . . . 6
Clock Configuration Modes . . . . . . . . . . . . . . . . . . . 20
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 55
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 59
Document Revision History . . . . . . . . . . . . . . . . . . . 59
Features
Figure 1 shows the block diagram for the MPC8250.
16 Kbytes
I-Cache
I-MMU
System Interface Unit
(SIU)
G2 Core
16 Kbytes
D-Cache
Bus Interface Unit
Communication Processor Module (CPM)
PCI Bus
32 bits, up to 66 MHz
60x-to-PCI
Bridge
60x-to-Local
Bridge
D-MMU
60x Bus
or
Local Bus
32 bits, up to 66 MHz
Memory Controller
Timers
Serial
DMAs
32 Kbytes
Dual-Port RAM
Interrupt
Controller
Clock Counter
Parallel I/O
32-bit RISC Microcontroller
and Program ROM
Baud Rate
Generators
MCC2
FCC1
FCC2
FCC3
SCC1
SCC2
4 Virtual
IDMAs
SCC3
SCC4
System Functions
SMC1
SMC2
SPI
I2C
Time Slot Assigner
Serial Interface
4 TDM Ports
3 MII
Ports
Non-Multiplexed
I/O
Figure 1. MPC8250 Block Diagram
1
Features
The major features of the MPC8250 are as follows:
• Footprint-compatible with the MPC8260
• Dual-issue integer core
— A core version of the EC603e microprocessor
— System core microprocessor supporting frequencies of 150–200 MHz
— Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
— PowerPC architecture-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
— High-performance (4.4–5.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at
200 MHz)
MPC8250 Hardware Specifications, Rev. 2
2
Freescale Semiconductor
Features
•
•
•
•
•
•
•
— Supports bus snooping for data cache coherency
— Floating-point unit (FPU)
Separate power supply for internal logic (1.8 V) and for I/O (3.3V)
Separate PLLs for G2 core and for the CPM
— G2 core and CPM can run at different frequencies for power/performance optimization
— Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
64-bit data and 32-bit address 60x bus
— Bus supports multiple master designs
— Supports single- and four-beat burst transfers
— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
— Supports data parity or ECC and address parity
32-bit data and 18-bit address local bus
— Single-master bus, supports external slaves
— Eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
60x-to-PCI bridge
— Programmable host bridge and agent
— 32-bit data bus, 66 MHz, 3.3 V
— Synchronous and asynchronous 60x and PCI clock modes
— All internal address space available to external PCI host
— DMA for memory block transfers
— PCI-to-60x address remapping
System interface unit (SIU)
— Clock synthesizer
— Reset controller
— Real-time clock (RTC) register
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IEEE 1149.1™ JTAG test access port
Twelve-bank memory controller
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other userdefinable peripherals
— Byte write enables and selectable parity generation
— 32-bit address decodes with programmable bank size
— Three user programmable machines, general-purpose chip-select machine, and page-mode
pipeline SDRAM machine
— Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
3
Features
•
•
— Dedicated interface logic for SDRAM
CPU core can be disabled and the device can be used in slave mode to an external core
Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support
for communications protocols
— Interfaces to G2 core through on-chip 32-Kbyte dual-port RAM and DMA controller
— Serial DMA channels for receive and transmit on all serial channels
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
— Three fast communications controllers supporting the following protocols:
– 10/100-Mbit Ethernet/IEEE 802.3® CDMA/CS interface through media independent
interface (MII)
– Transparent
– HDLC—Up to T3 rates (clear channel)
— One multichannel controller (MCC2)
– Handles 128 serial, full-duplex, 64-Kbps data channels. The MCC can be split into four
subgroups of 32 channels each.
– Almost any combination of subgroups can be multiplexed to single or multiple TDM
interfaces up to four TDM interfaces per MCC
— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting
the digital portions of the following protocols:
– Ethernet/IEEE 802.3 CDMA/CS
– HDLC/SDLC and HDLC bus
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART
– Binary synchronous (BISYNC) communications
– Transparent
— Two serial management controllers (SMCs), identical to those of the MPC860
– Provide management for BRI devices as general circuit interface (GCI) controllers in timedivision-multiplexed (TDM) channels
– Transparent
– UART (low-speed operation)
— One serial peripheral interface identical to the MPC860 SPI
— One inter-integrated circuit (I2C) controller (identical to the MPC860 I2C controller)
– Microwire compatible
– Multiple-master, single-master, and slave modes
— Up to four TDM interfaces
– Supports one group of four TDM channels
MPC8250 Hardware Specifications, Rev. 2
4
Freescale Semiconductor
Features
–
–
–
–
•
2,048 bytes of SI RAM
Bit or byte resolution
Independent transmit and receive routing, frame synchronization
Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN
primary rate, Freescale interchip digital link (IDL), general circuit interface (GCI), and
user-defined TDM serial interfaces
— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,
SCCs, SMCs, and serial channels
— Four independent 16-bit timers that can be interconnected as two 32-bit timers
PCI bridge
— PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz
— On-chip arbitration
— Support for PCI to 60x memory and 60x memory to PCI streaming
— PCI Host Bridge or Peripheral capabilities
— Includes 4 DMA channels for the following transfers:
– PCI-to-60x to 60x-to-PCI
– 60x-to-PCI to PCI-to-60x
– PCI-to-60x to PCI-to-60x
– 60x-to-PCI to 60x-to-PCI
— Includes all of the configuration registers (which are automatically loaded from the EPROM
and used to configure the MPC8265A) required by the PCI standard as well as message and
doorbell registers
— Supports the I2O standard
— Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0
August 3, 1998)
— Support for 66 MHz, 3.3 V specification
— 60x-PCI bus core logic which uses a buffer pool to allocate buffers for each port
— Makes use of the local bus signals, so there is no need for additional pins
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
5
Electrical and Thermal Characteristics
2
Electrical and Thermal Characteristics
This section provides AC and DC electrical specifications and thermal characteristics for the MPC8250.
2.1
DC Electrical Characteristics
This section describes the DC electrical characteristics for the MPC8250. Table 1 shows the maximum
electrical ratings.
Table 1. Absolute Maximum Ratings 1
Rating
Core supply voltage 2
Value
Unit
VDD
-0.3 – 2.5
V
2
VCCSYN
-0.3 – 2.5
V
3
VDDH
-0.3 – 4.0
V
VIN
GND(-0.3) – 3.6
V
Tj
120
°C
TSTG
(-55) – (+150)
°C
PLL supply voltage
I/O supply voltage
Symbol
Input voltage 4
Junction temperature
Storage temperature range
1
Absolute maximum ratings are stress ratings only; functional operation (see Table 2) at the maximums is not
guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage.
2
Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset.
3 Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH should
not exceed VDD/VCCSYN by more than 2.5 V during normal operation.
4
Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.
Table 2 lists recommended operational voltage conditions.
Table 2. Recommended Operating Conditions 1
Rating
2
3
4
5
Value
Unit
Core supply voltage
VDD
1.7 – 1.9 2
1.7–2.1 3
1.9 –2.2 4
V
PLL supply voltage
VCCSYN
1.7 – 1.92
1.7–2.13
1.9–2.24
V
I/O supply voltage
VDDH
3.135 – 3.465
V
VIN
GND (-0.3) – 3.465
V
Junction temperature (maximum)
Tj
105 5
°C
Ambient temperature
TA
0–705
°C
Input voltage
1
Symbol
Caution: These are the recommended and tested operating conditions. Proper device operating outside of these
conditions is not guaranteed.
CPU frequency less than or equal to 200 MHz.
CPU frequency greater than 200 MHz but less than 233 MHz.
CPU frequency greater than or equal to 233 MHz.
Note that for extended temperature parts the range is (-40)T – 105Tj.
A
MPC8250 Hardware Specifications, Rev. 2
6
Freescale Semiconductor
Electrical and Thermal Characteristics
NOTE: Core, PLL, and I/O Supply Voltages
VDDH, VCCSYN, and VDD must track each other and both must vary in
the same direction—in the positive direction (+5% and +0.1 Vdc) or in the
negative direction (-5% and -0.1 Vdc).
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (either GND or VCC).
Figure 2 shows the undershoot and overshoot voltage of the 60x and local bus memory interface of the
MPC8280. Note that in PCI mode the I/O interface is different.
4V
GVDD + 5%
GVDD
VIH
GND
GND – 0.3 V
VIL
GND – 1.0 V
Not to exceed 10%
of tSDRAM_CLK
Figure 2. Overshoot/Undershoot Voltage
Table 3 shows DC electrical characteristics.
Table 3. DC Electrical Characteristics 1
Characteristic
Symbol
Min
Max
Unit
Input high voltage, all inputs except CLKIN
VIH
2.0
3.465
V
Input low voltage
VIL
GND
0.8
V
VIHC
2.4
3.465
V
VILC
GND
0.4
V
IIN
—
10
µA
IOZ
—
10
µA
Signal low input current, VIL = 0.8 V
IL
—
1
µA
Signal high input current, VIH = 2.0 V
IH
—
1
µA
VOH
2.4
—
V
CLKIN input high voltage
CLKIN input low voltage
Input leakage current, VIN = VDDH
2
Hi-Z (off state) leakage current, VIN = VDDH
Output high voltage, IOH = –2 mA
2
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
7
Electrical and Thermal Characteristics
Table 3. DC Electrical Characteristics 1 (continued)
Characteristic
IOL = 7.0mA
BR
BG
ABB/IRQ2
TS
A[0-31]
TT[0-4]
TBST
TSIZE[0–3]
AACK
ARTRY
DBG
DBB/IRQ3
D[0-63]
DP(0)/RSRV/EXT_BR2
DP(1)/IRQ1/EXT_BG2
DP(2)/TLBISYNC/IRQ2/EXT_DBG2
DP(3)/IRQ3/EXT_BR3/CKSTP_OUT
DP(4)/IRQ4/EXT_BG3/CORE_SREST
DP(5)/TBEN/IRQ5/EXT_DBG3
DP(6)/CSE(0)/IRQ6
DP(7)/CSE(1)/IRQ7
PSDVAL
TA
TEA
GBL/IRQ1
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
L2_HIT/IRQ4
CPU_BG/BADDR31/IRQ5
CPU_DBG
CPU_BR
IRQ0/NMI_OUT
IRQ7/INT_OUT/APE
PORESET
HRESET
SRESET
RSTCONF
QREQ
Symbol
Min
Max
Unit
VOL
—
0.4
V
MPC8250 Hardware Specifications, Rev. 2
8
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 3. DC Electrical Characteristics 1 (continued)
Characteristic
IOL = 5.3mA
CS[0-9]
CS(10)/BCTL1
CS(11)/AP(0)
BADDR[27–28]
ALE
BCTL0
PWE(0:7)/PSDDQM(0:7)/PBS(0:7)
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
LWE[0–3]LSDDQM[0:3]/LBS[0–3]/PCI_CFG[0–3
LSDA10/LGPL0/PCI_MODCKH0
LSDWE/LGPL1/PCI_MODCKH1
LOE/LSDRAS/LGPL2/PCI_MODCKH2
LSDCAS/LGPL3/PCI_MODCKH3
LGTA/LUPMWAIT/LGPL4/LPBS
LSDAMUX/LGPL5/PCI_MODCK
LWR
MODCK1/AP(1)/TC(0)/BNKSEL(0)
MODCK2/AP(2)/TC(1)/BNKSEL(1)
MODCK3/AP(3)/TC(2)/BNKSEL(2)
IOL = 3.2mA
L_A14/PAR
L_A15/FRAME/SMI
L_A16/TRDY
L_A17/IRDY/CKSTP_OUT
L_A18/STOP
L_A19/DEVSEL
L_A20/IDSEL
L_A21/PERR
L_A22/SERR
L_A23/REQ0
L_A24/REQ1/HSEJSW
L_A25/GNT0
L_A26/GNT1/HSLED
L_A27/GNT2/HSENUM
L_A28/RST/CORE_SRESET
L_A29/INTA
L_A30/REQ2
L_A31
LCL_D(0-31)/AD(0-31)
LCL_DP(0-3)/C/BE(0-3)
PA[0–31]
PB[4–31]
PC[0–31]
PD[4–31]
TDO
Symbol
Min
Max
Unit
VOL
—
0.4
V
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
9
Electrical and Thermal Characteristics
1
The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive
DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.
2
The leakage current is measured for nominal VDD, VCCSYN, and VDD.
2.2
Thermal Characteristics
Table 4 describes thermal characteristics.
Table 4. Thermal Characteristics
Value
Characteristic
Symbol
Junction to ambient—
single-layer board 1
Junction to ambient—
four-layer board
θJA
Unit
Air Flow
480 TBGA
516 PBGA
13
24
Natural convection
10
18
1 m/s
11
16
8
13
°C/W
Natural convection
1 m/s
Junction to board 2
θJB
4
8
°C/W
—
Junction to case 3
θJC
1.1
6
°C/W
—
1
Assumes no thermal vias
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
3 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
2
2.3
Power Considerations
The average chip-junction temperature, TJ, in °C can be obtained from the following:
TJ = TA + (PD x θJA)
(1)
where
TA = ambient temperature °C
θJA = package thermal resistance, junction to ambient, °C/W
PD = PINT + PI/O
PINT = IDD x VDD Watts (chip internal power)
PI/O = power dissipation on input and output pins (determined by user)
For most applications PI/O < 0.3 x PINT. If PI/O is neglected, an approximate relationship between PD and
TJ is the following:
PD = K/(T J + 273° C)
(2)
Solving equations (1) and (2) for K gives:
K = PD x (TA + 273° C) + θJA x PD2
(3)
MPC8250 Hardware Specifications, Rev. 2
10
Freescale Semiconductor
Electrical and Thermal Characteristics
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving equations (1) and (2) iteratively for any value of TA.
2.3.1
Layout Practices
Each VCC pin should be provided with a low-impedance path to the board’s power supply. Each ground
pin should likewise be provided with a low-impedance path to ground. The power supply pins drive
distinct groups of logic on chip. The VCC power supply should be bypassed to ground using at least four
0.1 µF by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads
and associated printed circuit traces connecting to chip VCC and ground should be kept to less than half an
inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND
planes.
All output pins on the MPC8250 have fast rise and fall times. Printed circuit (PC) trace interconnection
length should be minimized in order to minimize overdamped conditions and reflections caused by these
fast output switching times. This recommendation particularly applies to the address and data buses.
Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all
device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and
bypassing becomes especially critical in systems with higher capacitive loads because these loads create
higher transient currents in the VCC and GND circuits. Pull up all unused inputs or signals that will be
inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins.
Table 5 provides preliminary, estimated power dissipation for various configurations. Note that suitable
thermal management is required for conditions above PD = 3W (when the ambient temperature is 70° C or
greater) to ensure the junction temperature does not exceed the maximum specified value. Also note that
the I/O power should be included when determining whether to use a heat sink.
Table 5. Estimated Power Dissipation for Various Configurations 1
PINT(W) 2
Bus
(MHz)
1
2
CPM
Core CPU
Multiplier Multiplier
CPM
(MHz)
CPU
(MHz)
Vddl 1.8 Volts
Vddl 2.0 Volts
Nominal
Maximum
Nominal
Maximum
66.66
2
3
133
200
1.2
2
1.8
2.3
66.66
2.5
3
166
200
1.3
2.1
1.9
2.3
66.66
3
4
200
266
—
—
2.3
2.9
66.66
3
4.5
200
300
—
—
2.4
3.1
83.33
2
3
166
250
—
—
2.2
2.8
83.33
2
3
166
250
—
—
2.2
2.8
83.33
2.5
3.5
208
291
—
—
2.4
3.1
Test temperature = room temperature (25° C)
PINT = IDD x V DD Watts
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
11
Electrical and Thermal Characteristics
2.4
AC Electrical Characteristics
The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and
inputs for the 66 MHz MPC8250 device. Note that AC timings are based on a 50-pf load. Typical output
buffer impedances are shown in Table 6.
Table 6. Output Buffer Impedances 1
Output Buffers
Typical Impedance (Ω)
60x bus
40
Local bus
40
Memory controller
40
Parallel I/O
46
PCI
25
1
These are typical values at 65° C. The impedance may vary by
±25% with process and temperature.
Table 7 lists CPM output characteristics.
Table 7. AC Characteristics for CPM Outputs 1
Spec Number
Max Delay (ns)
Min Delay (ns)
Characteristic
1
Max
Min
66 MHz 83 MHz 66 MHz 83 MHz
sp36a
sp37a
FCC outputs—internal clock (NMSI)
6
5.5
1
1
sp36b
sp37b
FCC outputs—external clock (NMSI)
14
12
2
1
sp40
sp41
TDM outputs/SI
25
16
5
4
sp38a
sp39a
SCC/SMC/SPI/I2C outputs—internal clock (NMSI)
19
16
1
0.5
sp38b
sp39b
Ex_SCC/SMC/SPI/I2C outputs—external clock (NMSI)
19
16
2
1
sp42
sp43
TIMER/IDMA outputs
14
11
1
0.5
sp42a
sp43a
PIO outputs
14
11
0.5
0.5
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
Table 8 lists CPM input characteristics.
Table 8. AC Characteristics for CPM Inputs 1
Spec Number
Setup (ns)
Hold (ns)
Characteristic
Max
Min
66 MHz 83 MHz 66 MHz 83 MHz
sp16a
sp17a
FCC inputs—internal clock (NMSI)
10
8
0
0
sp16b
sp17b
FCC inputs—external clock (NMSI)
3
2.5
3
2
MPC8250 Hardware Specifications, Rev. 2
12
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 8. AC Characteristics for CPM Inputs 1
Spec Number
Setup (ns)
Hold (ns)
Characteristic
1
Max
Min
66 MHz 83 MHz 66 MHz 83 MHz
sp20
sp21
TDM inputs/SI
15
12
12
10
sp18a
sp19a
SCC/SMC/SPI/I2C inputs—internal clock (NMSI)
20
16
0
0
sp18b
sp19b
SCC/SMC/SPI/I2C inputs—external clock (NMSI)
5
4
5
4
sp22
sp23
PIO/TIMER/IDMA inputs
10
8
3
3
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.
Timings are measured at the pin.
Note that although the specifications generally reference the rising edge of the clock, the following AC
timing diagrams also apply when the falling edge is the active edge.
Figure 3 shows the FCC external clock.
Serial ClKin
sp17b
sp16b
FCC input signals
sp36b/sp37b
FCC output signals
Note: When GFMR[TCI] = 0
sp36b/sp37b
FCC output signals
Note: When GFMR[TCI] = 1
Figure 3. FCC External Clock Diagram
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
13
Electrical and Thermal Characteristics
Figure 4 shows the FCC internal clock.
BRG_OUT
sp17a
sp16a
FCC input signals
sp36a/sp37a
FCC output signals
Note: When GFMR.TCI = 0
sp36a/sp37a
FCC output signals
Note: When GFMR.TCI = 1
Figure 4. FCC Internal Clock Diagram
Figure 5 shows the SCC/SMC/SPI/I2C external clock.
Serial CLKin
sp18b
sp19b
SCC/SMC/SPI/I2C input signals
(See note.)
sp38b/sp39b
SCC/SMC/SPI/I2C output signals
(See note.)
Note: There are four possible timing conditions for SCC and SPI:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
Figure 5. SCC/SMC/SPI/I2C External Clock Diagram
MPC8250 Hardware Specifications, Rev. 2
14
Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 6 shows the SCC/SMC/SPI/I2C internal clock.
BRG_OUT
sp19a
sp18a
SCC/SMC/SPI/I2C input signals
(See note.)
sp38a/sp39a
SCC/SMC/SPI/I2C output signals
(See note.)
Note: There are four possible timing conditions for SCC and SPI:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
Figure 6. SCC/SMC/SPI/I2C Internal Clock Diagram
Figure 7 shows TDM input and output signals.
Serial CLKin
sp20
sp21
TDM input signals
sp40/sp41
TDM output signals
Note: There are four possible TDM timing conditions:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
Figure 7. TDM Signal Diagram
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
15
Electrical and Thermal Characteristics
Figure 8 shows PIO, timer, and DMA signals.
Sys clk
sp23
sp22
PIO/IDMA/TIMER[TGATE assertion] input signals
(See note)
sp23
sp22
TIMER input signal [TGATE deassertion]
(See note)
sp42/sp43
IDMA output signals
sp42/sp43
sp42a/sp43a
TIMER(sp42/43)/ PIO(sp42a/sp43a)
output signals
Note: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge.
Figure 8. PIO, Timer, and DMA Signal Diagram
Table 9 lists SIU input characteristics.
Table 9. AC Characteristics for SIU Inputs 1
Spec Number
Setup (ns)
Hold (ns)
Characteristic
1
Max
Min
66 MHz 83 MHz 66 MHz 83 MHz
sp11
sp10
AACK/ARTRY/TA/TS/TEA/DBG/BG/BR
6
5
0.5
0.5
sp12
sp10
Data bus in normal mode
5
4
0.5
0.5
sp13
sp10
Data bus in ECC and PARITY modes
8
6
0.5
0.5
sp14
sp10
DP pins
7
6
0.5
0.5
sp15
sp10
All other pins
5
4
0.5
0.5
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.
Timings are measured at the pin.
MPC8250 Hardware Specifications, Rev. 2
16
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 10 lists SIU output characteristics.
Table 10. AC Characteristics for SIU Outputs 1
Spec Number
Max Delay (ns)
Min Delay (ns)
Characteristic
1
Max
Min
66 MHz 83 MHz 66 MHz 83 MHz
sp31
sp30
PSDVAL/TEA/TA
7
6
0.5
0.5
sp32
sp30
ADD/ADD_atr./BADDR/CI/GBL/WT
8
6.5
0.5
0.5
sp33a
sp30
Data bus
6.5
6.5
0.5
0.5
sp33b
sp30
DP
8
7
0.5
0.5
sp34
sp30
Memory controller signals/ALE
6
5
0.5
0.5
sp35
sp30
All other signals
6
5.5
0.5
0.5
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
NOTE
Activating data pipelining (setting BRx[DR] in the memory controller)
improves the AC timing. When data pipelining is activated, sp12 can be
used for data bus setup even when ECC or PARITY are used. Also, sp33a
can be used as the AC specification for DP signals.
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
17
Electrical and Thermal Characteristics
Figure 9 shows the interaction of several bus signals.
CLKin
sp11
sp10
AACK/ARTRY/TA/TS/TEA/
DBG/BG/BR input signals
sp12
sp10
sp15
sp10
DATA bus normal mode
input signal
All other input signals
sp30
sp31
PSDVAL/TEA/TA output signals
sp32
sp30
sp33a
sp30
sp35
sp30
ADD/ADD_atr/BADDR/CI/
GBL/WT output signals
DATA bus output signals
All other output signals
Figure 9. Bus Signals
Figure 10 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).
CLKin
sp10
sp13
DATA bus, ECC, and PARITY mode input signals
sp10
sp14
DP mode input signal
sp33b/sp30
DP mode output signal
Figure 10. Parity Mode Diagram
MPC8250 Hardware Specifications, Rev. 2
18
Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 11 shows signal behavior in MEMC mode.
CLKin
V_CLK
sp34/sp30
Memory controller signals
Figure 11. MEMC Mode Diagram
NOTE
Generally, all MPC8250 bus and system output signals are driven from the
rising edge of the input clock (CLKin). Memory controller signals,
however, trigger on four points within a CLKin cycle. Each cycle is divided
by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising
edge, and T3 at the falling edge, of CLKin. However, the spacing of T2 and
T4 depends on the PLL clock ratio selected, as shown in Table 11.
Table 11. Tick Spacing for Memory Controller Signals
Tick Spacing (T1 Occurs at the Rising Edge of CLKin)
PLL Clock Ratio
T2
T3
T4
1:2, 1:3, 1:4, 1:5, 1:6
1/4 CLKin
1/2 CLKin
3/4 CLKin
1:2.5
3/10 CLKin
1/2 CLKin
8/10 CLKin
1:3.5
4/14 CLKin
1/2 CLKin
11/14 CLKin
Figure 12 is a graphical representation of Table 11.
for 1:2, 1:3, 1:4, 1:5, 1:6
CLKin
T1
T2
T3
T4
CLKin
for 1:2.5
T1
T2
T3
T4
CLKin
for 1:3.5
T1
T2
T3
T4
Figure 12. Internal Tick Spacing for Memory Controller Signals
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
19
Clock Configuration Modes
NOTE
The UPM machine outputs change on the internal tick determined by the
memory controller programming; the AC specifications are relative to the
internal tick. Note that SDRAM and GPCM machine outputs change on
CLKin’s rising edge.
3
Clock Configuration Modes
The MPC8250 has three clocking modes: local, PCI host, and PCI agent. The clocking mode is set
according to three input pins—PCI_MODE, PCI_CFG[0], PCI_MODCK—as shown in Table 12.
Table 12. MPC8250 Clocking Modes
Pins
PCI_CFG[0] PCI_MODCK 1
PCI_MODE
1
—
—
0
0
0
0
0
1
0
1
0
0
1
1
Clocking Mode
PCI Clock
Frequency Range
(MHZ)
Reference
Local bus
—
Table 13 and Table 14
50–66
PCI host
25–50
Table 15 and Table 16
50–66
PCI agent
1
25–50
Table 17 and Table 18
Determines PCI clock frequency range. Refer to Section 3.2, “PCI Mode.”
In each clocking mode, the configuration of bus, core, PCI, and CPM frequencies is determined by seven
bits during the power-up reset—three hardware configuration pins (MODCK[1–3]) and four bits from
hardware configuration word[28–31] (MODCK_H). Both the PLLs and the dividers are set according to
the selected MPC8250 clock operation mode as described in the following sections.
NOTE
Clock configurations change only after POR is asserted.
3.1
Local Bus Mode
Table 13 shows the eight basic clock configurations for the MPC8250. Another 49 configurations are
available by using the configuration pin (RSTCONF) and driving four pins on the data bus.
Table 13. Clock Default Configurations
MODCK[1–3]
Input Clock
Frequency
CPM Multiplication
Factor
CPM
Frequency
Core Multiplication
Factor
Core
Frequency
000
33 MHz
3
100 MHz
4
133 MHz
001
33 MHz
3
100 MHz
5
166 MHz
010
33 MHz
4
133 MHz
4
133 MHz
011
33 MHz
4
133 MHz
5
166 MHz
MPC8250 Hardware Specifications, Rev. 2
20
Freescale Semiconductor
Clock Configuration Modes
Table 13. Clock Default Configurations
MODCK[1–3]
Input Clock
Frequency
CPM Multiplication
Factor
CPM
Frequency
Core Multiplication
Factor
Core
Frequency
100
66 MHz
2
133 MHz
2.5
166 MHz
101
66 MHz
2
133 MHz
3
200 MHz
110
66 MHz
2.5
166 MHz
2.5
166 MHz
111
66 MHz
2.5
166 MHz
3
200 MHz
Table 14 describes all possible clock configurations when using the hard reset configuration sequence.
Note also that basic modes are shown in boldface type. The frequencies listed are for the purpose of
illustration only. Users must select a mode and input bus frequency so that the resulting configuration does
not exceed the frequency rating of the user’s device.
Table 14. Clock Configuration Modes 1
MODCK_H–MODCK[1–3]
Input Clock CPM Multiplication
Frequency2, 3
Factor2
Core Multiplication
CPM
Core
Factor2
Frequency2
Frequency2
0001_000
33 MHz
2
66 MHz
4
133 MHz
0001_001
33 MHz
2
66 MHz
5
166 MHz
0001_010
33 MHz
2
66 MHz
6
200 MHz
0001_011
33 MHz
2
66 MHz
7
233 MHz
0001_100
33 MHz
2
66 MHz
8
266 MHz
0001_101
33 MHz
3
100 MHz
4
133 MHz
0001_110
33 MHz
3
100 MHz
5
166 MHz
0001_111
33 MHz
3
100 MHz
6
200 MHz
0010_000
33 MHz
3
100 MHz
7
233 MHz
0010_001
33 MHz
3
100 MHz
8
266 MHz
0010_010
33 MHz
4
133 MHz
4
133 MHz
0010_011
33 MHz
4
133 MHz
5
166 MHz
0010_100
33 MHz
4
133 MHz
6
200 MHz
0010_101
33 MHz
4
133 MHz
7
233 MHz
0010_110
33 MHz
4
133 MHz
8
266 MHz
0010_111
33 MHz
5
166 MHz
4
133 MHz
0011_000
33 MHz
5
166 MHz
5
166 MHz
0011_001
33 MHz
5
166 MHz
6
200 MHz
0011_010
33 MHz
5
166 MHz
7
233 MHz
0011_011
33 MHz
5
166 MHz
8
266 MHz
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
21
Clock Configuration Modes
Table 14. Clock Configuration Modes 1 (continued)
MODCK_H–MODCK[1–3]
Input Clock CPM Multiplication
Frequency2, 3
Factor2
Core Multiplication
CPM
Core
Factor2
Frequency2
Frequency2
0011_100
33 MHz
6
200 MHz
4
133 MHz
0011_101
33 MHz
6
200 MHz
5
166 MHz
0011_110
33 MHz
6
200 MHz
6
200 MHz
0011_111
33 MHz
6
200 MHz
7
233 MHz
0100_000
33 MHz
6
200 MHz
8
266 MHz
0100_001
Reserved
0100_010
0100_011
0100_100
0100_101
0100_110
0100_111
Reserved
0101_000
0101_001
0101_010
0101_011
0101_100
0101_101
66 MHz
2
133 MHz
2
133 MHz
0101_110
66 MHz
2
133 MHz
2.5
166 MHz
0101_111
66 MHz
2
133 MHz
3
200 MHz
0110_000
66 MHz
2
133 MHz
3.5
233 MHz
0110_001
66 MHz
2
133 MHz
4
266 MHz
0110_010
66 MHz
2
133 MHz
4.5
300 MHz
0110_011
66 MHz
2.5
166 MHz
2
133 MHz
0110_100
66 MHz
2.5
166 MHz
2.5
166 MHz
0110_101
66 MHz
2.5
166 MHz
3
200 MHz
0110_110
66 MHz
2.5
166 MHz
3.5
233 MHz
0110_111
66 MHz
2.5
166 MHz
4
266 MHz
0111_000
66 MHz
2.5
166 MHz
4.5
300 MHz
MPC8250 Hardware Specifications, Rev. 2
22
Freescale Semiconductor
Clock Configuration Modes
Table 14. Clock Configuration Modes 1 (continued)
MODCK_H–MODCK[1–3]
Input Clock CPM Multiplication
Frequency2, 3
Factor2
Core Multiplication
CPM
Core
Factor2
Frequency2
Frequency2
0111_001
66 MHz
3
200 MHz
2
133 MHz
0111_010
66 MHz
3
200 MHz
2.5
166 MHz
0111_011
66 MHz
3
200 MHz
3
200 MHz
0111_100
66 MHz
3
200 MHz
3.5
233 MHz
0111_101
66 MHz
3
200 MHz
4
266 MHz
0111_110
66 MHz
3
200 MHz
4.5
300 MHz
0111_111
66 MHz
3.5
233 MHz
2
133 MHz
1000_000
66 MHz
3.5
233 MHz
2.5
166 MHz
1000_001
66 MHz
3.5
233 MHz
3
200 MHz
1000_010
66 MHz
3.5
233 MHz
3.5
233 MHz
1000_011
66 MHz
3.5
233 MHz
4
266 MHz
1000_100
66 MHz
3.5
233 MHz
4.5
300 MHz
1
Because of speed dependencies, not all of the possible configurations in Table 14 are applicable.
The user should choose the input clock frequency and the multiplication factors such that the frequency of the CPU
is equal to or greater than 133 MHz (150 MHz for extended temperature parts) and the CPM ranges between 66–233
MHz.
3 Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so that the
resulting configuration does not exceed the frequency rating of the user’s part.
2
3.2
PCI Mode
The PCI mode is selected according to three input pins, as shown in Table 12. In addition, note the
following:
NOTE: PCI_MODCK
In PCI mode only, PCI_MODCK comes from the LGPL5 pin and
MODCK_H[0–3] comes from {LGPL0, LGPL1, LGPL2, LGPL3}.
NOTE: Tval (Output Hold)
The minimum Tval = 2 when PCI_MODCK = 1, and the minimum Tval = 1
when PCI_MODCK = 0. Therefore, designers should use clock
configurations that fit this condition to achieve PCI-compliant AC timing.
NOTE
Clock configurations change only after POR is asserted.
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
23
Clock Configuration Modes
3.2.1
PCI Host Mode
The frequencies listed in Table 15 are for the purpose of illustration only. Users must select a mode and
input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s
device.
Table 15. Clock Default Configurations in PCI Host Mode (MODCK_HI = 0000)
Core
CPM
Input Clock
Core
PCI Division
CPM
PCI
Multiplication
MODCK[1–3]1 Frequency Multiplication
Frequency
Factor 2
Frequency
Frequency2
Factor
Factor
(Bus)
1
2
000
66 MHz
2
133 MHz
2.5
166 MHz
2/4
66/33 MHz
001
66 MHz
2
133 MHz
3
200 MHz
2/4
66/33 MHz
010
66 MHz
2.5
166 MHz
3
200 MHz
3/6
55/28 MHz
011
66 MHz
2.5
166 MHz
3.5
233 MHz
3/6
55/28 MHz
100
66 MHz
2.5
166 MHz
4
266 MHz
3/6
55/28 MHz
101
66 MHz
3
200 MHz
3
200 MHz
3/6
66/33 MHz
110
66 MHz
3
200 MHz
3.5
233 MHz
3/6
66/33 MHz
111
66 MHz
3
200 MHz
4
266 MHz
3/6
66/33 MHz
Assumes MODCK_HI = 0000.
The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic ‘1’), the PCI frequency is
divided by 2 (33 instead of 66 MHz, etc.) Refer to Table 12.
Table 16 describes all possible clock configurations when using the MPC8250’s internal PCI bridge in host
mode.
Table 16. Clock Configuration Modes in PCI Host Mode
MODCK_H
–
MODCK[1–
3]
Input Clock
Frequency 1
(Bus)
0001_000
33 MHz
3
100 MHz
5
166 MHz
3/6
33/16 MHz
0001_001
33 MHz
3
100 MHz
6
200 MHz
3/6
33/16 MHz
0001_010
33 MHz
3
100 MHz
7
233 MHz
3/6
33/16 MHz
0001_011
33 MHz
3
100 MHz
8
266 MHz
3/6
33/16 MHz
0010_000
33 MHz
4
133 MHz
5
166 MHz
4/8
33/16 MHz
0010_001
33 MHz
4
133 MHz
6
200 MHz
4/8
33/16 MHz
0010_010
33 MHz
4
133 MHz
7
233 MHz
4/8
33/16 MHz
0010_011
33 MHz
4
133 MHz
8
266 MHz
4/8
33/16 MHz
0011_000 3
33 MHz
5
166 MHz
5
166 MHz
5
33 MHz
3
33 MHz
5
166 MHz
6
200 MHz
5
33 MHz
0011_001
Core
CPM
Core
PCI Division
CPM
PCI
Multiplication
Multiplication
Frequency
Factor 2
Frequency
Frequency2
Factor
Factor
MPC8250 Hardware Specifications, Rev. 2
24
Freescale Semiconductor
Clock Configuration Modes
Table 16. Clock Configuration Modes in PCI Host Mode (continued)
MODCK_H
–
MODCK[1–
3]
Input Clock
Frequency 1
(Bus)
0011_0103
33 MHz
5
166 MHz
7
233 MHz
5
33 MHz
0011_0113
33 MHz
5
166 MHz
8
266 MHz
5
33 MHz
0100_0003
33 MHz
6
200 MHz
5
166 MHz
6
33 MHz
3
33 MHz
6
200 MHz
6
200 MHz
6
33 MHz
0100_0103
33 MHz
6
200 MHz
7
233 MHz
6
33 MHz
0100_0113
33 MHz
6
200 MHz
8
266 MHz
6
33 MHz
0101_000
66 MHz
2
133 MHz
2.5
166 MHz
2/4
66/33 MHz
0101_001
66 MHz
2
133 MHz
3
200 MHz
2/4
66/33 MHz
0101_010
66 MHz
2
133 MHz
3.5
233 MHz
2/4
66/33 MHz
0101_011
66 MHz
2
133 MHz
4
266 MHz
2/4
66/33 MHz
0101_100
66 MHz
2
133 MHz
4.5
300 MHz
2/4
66/33 MHz
0110_000
66 MHz
2.5
166 MHz
2.5
166 MHz
3/6
55/28 MHz
0110_001
66 MHz
2.5
166 MHz
3
200 MHz
3/6
55/28 MHz
0110_010
66 MHz
2.5
166 MHz
3.5
233 MHz
3/6
55/28 MHz
0110_011
66 MHz
2.5
166 MHz
4
266 MHz
3/6
55/28 MHz
0110_100
66 MHz
2.5
166 MHz
4.5
300 MHz
3/6
55/28 MHz
0111_000
66 MHz
3
200 MHz
2.5
166 MHz
3/6
66/33 MHz
0111_001
66 MHz
3
200 MHz
3
200 MHz
3/6
66/33 MHz
0111_010
66 MHz
3
200 MHz
3.5
233 MHz
3/6
66/33 MHz
0111_011
66 MHz
3
200 MHz
4
266 MHz
3/6
66/33 MHz
0111_100
66 MHz
3
200 MHz
4.5
300 MHz
3/6
66/33 MHz
1000_000
66 MHz
3
200 MHz
2.5
166 MHz
4/8
50/25 MHz
1000_001
66 MHz
3
200 MHz
3
200 MHz
4/8
50/25 MHz
1000_010
66 MHz
3
200 MHz
3.5
233 MHz
4/8
50/25 MHz
1000_011
66 MHz
3
200 MHz
4
266 MHz
4/8
50/25 MHz
1000_100
66 MHz
3
200 MHz
4.5
300 MHz
4/8
50/25 MHz
1001_000
66 MHz
3.5
233 MHz
2.5
166 MHz
4/8
58/29 MHz
0100_001
Core
CPM
Core
PCI Division
CPM
PCI
Multiplication
Multiplication
Frequency
Factor 2
Frequency
Frequency2
Factor
Factor
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
25
Clock Configuration Modes
Table 16. Clock Configuration Modes in PCI Host Mode (continued)
MODCK_H
–
MODCK[1–
3]
Input Clock
Frequency 1
(Bus)
1001_001
66 MHz
3.5
233 MHz
3
200 MHz
4/8
58/29 MHz
1001_010
66 MHz
3.5
233 MHz
3.5
233 MHz
4/8
58/29 MHz
1001_011
66 MHz
3.5
233 MHz
4
266 MHz
4/8
58/29 MHz
1001_100
66 MHz
3.5
233 MHz
4.5
300 MHz
4/8
58/29 MHz
1010_000
100 MHz
2
200 MHz
2
200 MHz
3/6
66/33 MHz
1010_001
100 MHz
2
200 MHz
2.5
250 MHz
3/6
66/33 MHz
1010_010
100 MHz
2
200 MHz
3
300 MHz
3/6
66/33 MHz
1010_011
100 MHz
2
200 MHz
3.5
350 MHz
3/6
66/33 MHz
1010_100
100 MHz
2
200 MHz
4
400 MHz
3/6
66/33 MHz
1011_000
100 MHz
2.5
250 MHz
2
200 MHz
4/8
62/31 MHz
1011_001
100 MHz
2.5
250 MHz
2.5
250 MHz
4/8
62/31MHz
1011_010
100 MHz
2.5
250 MHz
3
300 MHz
4/8
62/31 MHz
1011_011
100 MHz
2.5
250 MHz
3.5
350 MHz
4/8
62/31 MHz
1011_100
100 MHz
2.5
250 MHz
4
400 MHz
4/8
62/31 MHz
Core
CPM
Core
PCI Division
CPM
PCI
Multiplication
Multiplication
Frequency
Factor 2
Frequency
Frequency2
Factor
Factor
1
Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so that
the resulting configuration does not exceed the frequency rating of the user’s part.
2 The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic ‘1’), the PCI frequency is
divided by 2 (33 instead of 66 MHz, etc.). Refer to Table 12
3 In this mode, PCI_MODCK must be “0”.
3.2.2
PCI Agent Mode
The frequencies listed in Table 17 are for the purpose of illustration only. Users must select a mode and
input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s
device.
Table 17. Clock Default Configurations in PCI Agent Mode (MODCK_HI = 0000)
Core
Input Clock
CPM
Core
CPM
Bus Division 60x Bus
Multiplication
MODCK[1–3]1 Frequency Multiplication
Frequency 3
Frequency
Factor
Frequency 4
2
2
Factor
(PCI)
Factor
000
66/33 MHz
2/4
133 MHz
2.5
166 MHz
2
66 MHz
001
66/33 MHz
2/4
133 MHz
3
200 MHz
2
66 MHz
010
66/33 MHz
3/6
200 MHz
3
200 MHz
3
66 MHz
011
66/33 MHz
3/6
200 MHz
4
266 MHz
3
66 MHz
MPC8250 Hardware Specifications, Rev. 2
26
Freescale Semiconductor
Clock Configuration Modes
Table 17. Clock Default Configurations in PCI Agent Mode (MODCK_HI = 0000)
Core
Input Clock
CPM
Core
CPM
Bus Division 60x Bus
Multiplication
MODCK[1–3]1 Frequency Multiplication
3
Frequency
Frequency
Factor
Frequency 4
Factor
(PCI)2
Factor 2
100
66/33 MHz
3/6
200 MHz
3
240 MHz
2.5
80 MHz
101
66/33 MHz
3/6
200 MHz
3.5
280 MHz
2.5
80 MHz
110
66/33 MHz
4/8
266 MHz
3.5
300 MHz
3
88 MHz
111
66/33 MHz
4/8
266 MHz
3
300 MHz
2.5
100 MHz
1
Assumes MODCK_HI = 0000.
The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic ‘1’), the PCI frequency is divided
by 2 (33 instead of 66 MHz, etc.) and the CPM multiplication factor is multiplied by 2. Refer to Table 12
3
Core frequency = (60x bus frequency)(core multiplication factor)
4
Bus frequency = CPM frequency / bus division factor
2
Table 18 describes all possible clock configurations when using the MPC8250’s internal PCI bridge in
agent mode.
Table 18. Clock Configuration Modes in PCI Agent Mode
MODCK_H
Input Clock
Core
CPM
Core
–
CPM
Bus Division 60x Bus
Frequency Multiplication
Multiplication
Frequency 3
MODCK[1–
Frequency
Factor
Frequency 4
1,
2
1
(PCI)
Factor
Factor
3]
0001_001
66/33 MHz
2/4
133 MHz
5
166 MHz
4
33 MHz
0001_010
66/33 MHz
2/4
133 MHz
6
200 MHz
4
33 MHz
0001_011
66/33 MHz
2/4
133 MHz
7
233 MHz
4
33 MHz
0001_100
66/33 MHz
2/4
133 MHz
8
266 MHz
4
33 MHz
0010_001
50/25 MHz
3/6
150 MHz
3
180 MHz
2.5
60 MHz
0010_010
50/25 MHz
3/6
150 MHz
3.5
210 MHz
2.5
60 MHz
0010_011
50/25 MHz
3/6
150 MHz
4
240 MHz
2.5
60 MHz
0010_100
50/25 MHz
3/6
150 MHz
4.5
270 MHz
2.5
60 MHz
0011_000
66/33 MHz
2/4
133 MHz
2.5
110MHz
3
44 MHz
0011_001
66/33 MHz
2/4
133 MHz
3
132 MHz
3
44 MHz
0011_010
66/33 MHz
2/4
133 MHz
3.5
154 MHz
3
44 MHz
0011_011
66/33 MHz
2/4
133 MHz
4
176MHz
3
44 MHz
0011_100
66/33 MHz
2/4
133 MHz
4.5
198 MHz
3
44 MHz
0100_000
66/33 MHz
3/6
200 MHz
2.5
166 MHz
3
66 MHz
0100_001
66/33 MHz
3/6
200 MHz
3
200 MHz
3
66 MHz
0100_010
66/33 MHz
3/6
200 MHz
3.5
233 MHz
3
66 MHz
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
27
Clock Configuration Modes
Table 18. Clock Configuration Modes in PCI Agent Mode (continued)
MODCK_H
Input Clock
Core
CPM
Core
–
CPM
Bus Division 60x Bus
Frequency Multiplication
Multiplication
Frequency 3
MODCK[1–
Frequency
Factor
Frequency 4
1,
2
1
(PCI)
Factor
Factor
3]
0100_011
66/33 MHz
3/6
200 MHz
4
266 MHz
3
66 MHz
0100_100
66/33 MHz
3/6
200 MHz
4.5
300 MHz
3
66 MHz
0101_000 5
33 MHz
5
166 MHz
2.5
166 MHz
2.5
66 MHz
5
0101_001
33 MHz
5
166 MHz
3
200 MHz
2.5
66 MHz
0101_0105
33 MHz
5
166 MHz
3.5
233 MHz
2.5
66 MHz
0101_0115
33 MHz
5
166 MHz
4
266 MHz
2.5
66 MHz
5
0101_100
33 MHz
5
166 MHz
4.5
300 MHz
2.5
66 MHz
0110_000
50/25 MHz
4/8
200 MHz
2.5
166 MHz
3
66 MHz
0110_001
50/25 MHz
4/8
200 MHz
3
200 MHz
3
66 MHz
0110_010
50/25 MHz
4/8
200 MHz
3.5
233 MHz
3
66 MHz
0110_011
50/25 MHz
4/8
200 MHz
4
266 MHz
3
66 MHz
0110_100
50/25 MHz
4/8
200 MHz
4.5
300 MHz
3
66 MHz
0111_000
66/33 MHz
3/6
200 MHz
2
200 MHz
2
100 MHz
0111_001
66/33 MHz
3/6
200 MHz
2.5
250 MHz
2
100 MHz
0111_010
66/33 MHz
3/6
200 MHz
3
300 MHz
2
100 MHz
0111_011
66/33 MHz
3/6
200 MHz
3.5
350 MHz
2
100 MHz
1000_000
66/33 MHz
3/6
200 MHz
2
160 MHz
2.5
80 MHz
1000_001
66/33 MHz
3/6
200 MHz
2.5
200 MHz
2.5
80 MHz
1000_010
66/33 MHz
3/6
200 MHz
3
240 MHz
2.5
80 MHz
1000_011
66/33 MHz
3/6
200 MHz
3.5
280 MHz
2.5
80 MHz
1000_100
66/33 MHz
3/6
200 MHz
4
320 MHz
2.5
80 MHz
1000_101
66/33 MHz
3/6
200 MHz
4.5
360 MHz
2.5
80 MHz
1001_000
66/33 MHz
4/8
266 MHz
2.5
166 MHz
4
66 MHz
1001_001
66/33 MHz
4/8
266 MHz
3
200 MHz
4
66 MHz
1001_010
66/33 MHz
4/8
266 MHz
3.5
233 MHz
4
66 MHz
1001_011
66/33 MHz
4/8
266 MHz
4
266 MHz
4
66 MHz
1001_100
66/33 MHz
4/8
266 MHz
4.5
300 MHz
4
66 MHz
MPC8250 Hardware Specifications, Rev. 2
28
Freescale Semiconductor
Pinout
Table 18. Clock Configuration Modes in PCI Agent Mode (continued)
MODCK_H
Input Clock
Core
CPM
Core
–
CPM
Bus Division 60x Bus
Frequency Multiplication
Multiplication
Frequency 3
MODCK[1–
Frequency
Factor
Frequency 4
1,
2
1
(PCI)
Factor
Factor
3]
1
2
3
4
5
4
1010_000
66/33 MHz
4/8
266 MHz
2.5
222 MHz
3
88 MHz
1010_001
66/33 MHz
4/8
266 MHz
3
266 MHz
3
88 MHz
1010_010
66/33 MHz
4/8
266 MHz
3.5
300 MHz
3
88 MHz
1010_011
66/33 MHz
4/8
266 MHz
4
350 MHz
3
88 MHz
1010_100
66/33 MHz
4/8
266 MHz
4.5
400 MHz
3
88 MHz
1011_000
66/33 MHz
4/8
266 MHz
2
212MHz
2.5
106 MHz
1011_001
66/33 MHz
4/8
266 MHz
2.5
265 MHz
2.5
106 MHz
1011_010
66/33 MHz
4/8
266 MHz
3
318 MHz
2.5
106 MHz
1011_011
66/33 MHz
4/8
266 MHz
3.5
371 MHz
2.5
106 MHz
1011_100
66/33 MHz
4/8
266 MHz
4
424 MHz
2.5
106 MHz
The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic ‘1’), the PCI frequency is
divided by 2 (33 instead of 66 MHz, etc.) and the CPM multiplication factor is multiplied by 2. Refer to Table 12
Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so that
the resulting configuration does not exceed the frequency rating of the user’s part.
Core frequency = (60x bus frequency)(core multiplication factor)
Bus frequency = CPM frequency / bus division factor
In this mode, PCI_MODCK must be “1”.
Pinout
This section provides the pin assignments and pinout list for the MPC8250.
4.1
TBGA Package
The following figures and table represent the standard 480 TBGA package. For information on the
alternate package, refer to Section 4.2, “PBGA Package.”
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
29
Pinout
4.1.1
TBGA Pin Assignments
Figure 13 shows the pinout of the TBGA package as viewed from the top surface.
1
2
3
4 5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
A
A
B
B
C
C
D
E
D
E
F
F
G
H
G
H
J
J
K
K
L
M
L
M
N
N
P
R
P
R
T
U
T
U
V
V
W
W
Y
AA
Y
AA
AB
AB
AC
AC
AD
AE
AD
AE
AF
AF
AG
AH
AG
AH
AJ
AJ
1
2
3
4 5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Not to Scale
Figure 13. Pinout of the 480 TBGA Package as Viewed from the Top Surface
MPC8250 Hardware Specifications, Rev. 2
30
Freescale Semiconductor
Pinout
Figure 14 shows the side profile of the TBGA package to indicate the direction of the top surface view.
View
Copper Heat Spreader
(Oxidized for Insulation)
Etched
Cavity
Die
Attach
Polymide Tape
Pressure Sensitive
Adhesive
Die
Soldermask
Glob-Top Filled Area
Glob-Top Dam
Copper Traces
1.27 mm Pitch
Wire Bonds
Figure 14. Side View of the TBGA Package
Table 20 shows the pinout list of the TBGA package of the MPC8250. Table 19 defines the conventions
and acronyms used in Table 20.
Table 19. Symbol Legend
Symbol
Meaning
OVERBAR
Signals with overbars, such as TA, are active low.
MII
Indicates that a signal is part of the media independent interface.
Table 20. MPC8250 TBGA Package Pinout List
Pin Name
Ball
BR
W5
BG
F4
ABB/IRQ2
E2
TS
E3
A0
G1
A1
H5
A2
H2
A3
H1
A4
J5
A5
J4
A6
J3
A7
J2
A8
J1
A9
K4
A10
K3
A11
K2
A12
K1
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
31
Pinout
Table 20. MPC8250 TBGA Package Pinout List (continued)
Pin Name
Ball
A13
L5
A14
L4
A15
L3
A16
L2
A17
L1
A18
M5
A19
N5
A20
N4
A21
N3
A22
N2
A23
N1
A24
P4
A25
P3
A26
P2
A27
P1
A28
R1
A29
R3
A30
R5
A31
R4
TT0
F1
TT1
G4
TT2
G3
TT3
G2
TT4
F2
TBST
D3
TSIZ0
C1
TSIZ1
E4
TSIZ2
D2
TSIZ3
F5
AACK
F3
ARTRY
E1
DBG
V1
DBB/IRQ3
V2
D0
B20
D1
A18
MPC8250 Hardware Specifications, Rev. 2
32
Freescale Semiconductor
Pinout
Table 20. MPC8250 TBGA Package Pinout List (continued)
Pin Name
Ball
D2
A16
D3
A13
D4
E12
D5
D9
D6
A6
D7
B5
D8
A20
D9
E17
D10
B15
D11
B13
D12
A11
D13
E9
D14
B7
D15
B4
D16
D19
D17
D17
D18
D15
D19
C13
D20
B11
D21
A8
D22
A5
D23
C5
D24
C19
D25
C17
D26
C15
D27
D13
D28
C11
D29
B8
D30
A4
D31
E6
D32
E18
D33
B17
D34
A15
D35
A12
D36
D11
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
33
Pinout
Table 20. MPC8250 TBGA Package Pinout List (continued)
Pin Name
Ball
D37
C8
D38
E7
D39
A3
D40
D18
D41
A17
D42
A14
D43
B12
D44
A10
D45
D8
D46
B6
D47
C4
D48
C18
D49
E16
D50
B14
D51
C12
D52
B10
D53
A7
D54
C6
D55
D5
D56
B18
D57
B16
D58
E14
D59
D12
D60
C10
D61
E8
D62
D6
D63
C2
DP0/RSRV/EXT_BR2
B22
IRQ1/DP1/EXT_BG2
A22
IRQ2/DP2/TLBISYNC/EXT_DBG2
E21
IRQ3/DP3/CKSTP_OUT/EXT_BR3
D21
IRQ4/DP4/CORE_SRESET/EXT_BG3
C21
IRQ5/DP5/TBEN/EXT_DBG3
B21
IRQ6/DP6/CSE0
A21
IRQ7/DP7/CSE1
E20
MPC8250 Hardware Specifications, Rev. 2
34
Freescale Semiconductor
Pinout
Table 20. MPC8250 TBGA Package Pinout List (continued)
Pin Name
Ball
PSDVAL
V3
TA
C22
TEA
V5
GBL/IRQ1
W1
CI/BADDR29/IRQ2
U2
WT/BADDR30/IRQ3
U3
L2_HIT/IRQ4
Y4
CPU_BG/BADDR31/IRQ5
U4
CPU_DBG
R2
CPU_BR
Y3
CS0
F25
CS1
C29
CS2
E27
CS3
E28
CS4
F26
CS5
F27
CS6
F28
CS7
G25
CS8
D29
CS9
E29
CS10/BCTL1
F29
CS11/AP0
G28
BADDR27
T5
BADDR28
U1
ALE
T2
BCTL0
A27
PWE0/PSDDQM0/PBS0
C25
PWE1/PSDDQM1/PBS1
E24
PWE2/PSDDQM2/PBS2
D24
PWE3/PSDDQM3/PBS3
C24
PWE4/PSDDQM4/PBS4
B26
PWE5/PSDDQM5/PBS5
A26
PWE6/PSDDQM6/PBS6
B25
PWE7/PSDDQM7/PBS7
A25
PSDA10/PGPL0
E23
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
35
Pinout
Table 20. MPC8250 TBGA Package Pinout List (continued)
Pin Name
Ball
PSDWE/PGPL1
B24
POE/PSDRAS/PGPL2
A24
PSDCAS/PGPL3
B23
PGTA/PUPMWAIT/PGPL4/PPBS
A23
PSDAMUX/PGPL5
D22
LWE0/LSDDQM0/LBS0/PCI_CFG0
H28
LWE1/LSDDQM1/LBS1/PCI_CFG1
H27
LWE2/LSDDQM2/LBS2/PCI_CFG2
H26
LWE3/LSDDQM3/LBS3/PCI_CFG3
G29
LSDA10/LGPL0/PCI_MODCKH0
D27
LSDWE/LGPL1/PCI_MODCKH1
C28
LOE/LSDRAS/LGPL2/PCI_MODCKH2
E26
LSDCAS/LGPL3/PCI_MODCKH3
D25
LGTA/LUPMWAIT/LGPL4/LPBS
C26
LGPL5/LSDAMUX/PCI_MODCK
B27
LWR
D28
L_A14/PAR
N27
L_A15/FRAME/SMI
T29
L_A16/TRDY
R27
L_A17/IRDY/CKSTP_OUT
R26
L_A18/STOP
R29
L_A19/DEVSEL
R28
L_A20/IDSEL
W29
L_A21/PERR
P28
L_A22/SERR
N26
L_A23/REQ0
AA27
P29
L_A24/REQ1/HSEJSW
AA26
L_A25/GNT0
N25
L_A26/GNT1/HSLED
L_A27/GNT2/HSENUM
AA25
L_A28/RST/CORE_SRESET
AB29
L_A29/INTA
AB28
L_A30/REQ2
P25
L_A31/DLLOUT
AB27
LCL_D0/AD0
H29
MPC8250 Hardware Specifications, Rev. 2
36
Freescale Semiconductor
Pinout
Table 20. MPC8250 TBGA Package Pinout List (continued)
Pin Name
Ball
LCL_D1/AD1
J29
LCL_D2/AD2
J28
LCL_D3/AD3
J27
LCL_D4/AD4
J26
LCL_D5/AD5
J25
LCL_D6/AD6
K25
LCL_D7/AD7
L29
LCL_D8/AD8
L27
LCL_D9/AD9
L26
LCL_D10/AD10
L25
LCL_D11/AD11
M29
LCL_D12/AD12
M28
LCL_D13/AD13
M27
LCL_D14/AD14
M26
LCL_D15/AD15
N29
LCL_D16/AD16
T25
LCL_D17/AD17
U27
LCL_D18/AD18
U26
LCL_D19/AD19
U25
LCL_D20/AD20
V29
LCL_D21/AD21
V28
LCL_D22/AD22
V27
LCL_D23/AD23
V26
LCL_D24/AD24
W27
LCL_D25/AD25
W26
LCL_D26/AD26
W25
LCL_D27/AD27
Y29
LCL_D28/AD28
Y28
LCL_D29/AD29
Y25
LCL_D30/AD30
AA29
LCL_D31/AD31
AA28
LCL_DP0/C0/BE0
L28
LCL_DP1/C1/BE1
N28
LCL_DP2/C2/BE2
T28
LCL_DP3/C3/BE3
W28
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
37
Pinout
Table 20. MPC8250 TBGA Package Pinout List (continued)
Pin Name
Ball
IRQ0/NMI_OUT
T1
IRQ7/INT_OUT/APE
D1
TRST
AH3
TCK
AG5
TMS
AJ3
TDI
AE6
TDO
AF5
TRIS
AB4
PORESET
AG6
HRESET
AH5
SRESET
AF6
QREQ
AA3
RSTCONF
AJ4
MODCK1/AP1/TC0/BNKSEL0
W2
MODCK2/AP2/TC1/BNKSEL1
W3
MODCK3/AP3/TC2/BNKSEL2
W4
XFC
AB2
CLKIN1
AH4
PA0/RESTART1/DREQ3
AC29 1
PA1/REJECT1/DONE3
AC251
PA2/CLK20/DACK3
AE281
PA3/CLK19/DACK4/L1RXD1A2
AG291
PA4/REJECT2/DONE4
AG281
PA5/RESTART2/DREQ4
AG261
PA6
AE241
PA7/SMSYN2
AH251
PA8/SMRXD2
AF231
PA9/SMTXD2
AH231
PA10/MSNUM5
AE221
PA11/MSNUM4
AH221
PA12/MSNUM3
AJ211
PA13/MSNUM2
AH201
PA14/FCC1_RXD3
AG191
PA15/FCC1_RXD2
AF181
PA16/FCC1_RXD1
AF171
MPC8250 Hardware Specifications, Rev. 2
38
Freescale Semiconductor
Pinout
Table 20. MPC8250 TBGA Package Pinout List (continued)
Pin Name
Ball
PA17/FCC1_RXD0/FCC1_RXD
AE161
PA18/FCC1_TXD0/FCC1_TXD
AJ161
PA19/FCC1_TXD1
AG151
PA20/FCC1_TXD2
AJ131
PA21/FCC1_TXD3
AE131
PA22
AF121
PA23
AG111
PA24/MSNUM1
AH91
PA25/MSNUM0
AJ81
PA26/FCC1_MII_RX_ER
AH71
PA27/FCC1_MII_RX_DV
AF71
PA28/FCC1_MII_TX_EN
AD51
PA29/FCC1_MII_TX_ER
AF11
PA30/FCC1_MII_CRS/FCC1_RTS
AD31
PA31/FCC1_MII_COL
AB51
PB4/FCC3_TXD3/L1RSYNCA2/FCC3_RTS
AD281
PB5/FCC3_TXD2/L1TSYNCA2/L1GNTA2
AD261
PB6/FCC3_TXD1/L1RXDA2/L1RXD0A2
AD251
PB7/FCC3_TXD0/FCC3_TXD/L1TXDA2/L1TXD0A2
AE261
PB8/FCC3_RXD0/FCC3_RXD/TXD3
AH271
PB9/FCC3_RXD1/L1TXD2A2
AG241
PB10/FCC3_RXD2
AH241
PB11/FCC3_RXD3
AJ241
PB12/FCC3_MII_CRS/TXD2
AG221
PB13/FCC3_MII_COL/L1TXD1A2
AH211
PB14/FCC3_MII_TX_EN/RXD3
AG201
PB15/FCC3_MII_TX_ER/RXD2
AF191
PB16/FCC3_MII_RX_ER/CLK18
AJ181
PB17/FCC3_MII_RX_DV/CLK17
AJ171
PB18/FCC2_RXD3/L1CLKOD2/L1RXD2A2
AE141
PB19/FCC2_RXD2/L1RQD2/L1RXD3A2
AF131
PB20/FCC2_RXD1/L1RSYNCD2/L1TXD1A1
AG121
PB21/FCC2_RXD0/FCC2_RXD/L1TSYNCD2/L1GNTD2
AH111
PB22/FCC2_TXD0/FCC2_TXD/L1RXDD2
AH161
PB23/FCC2_TXD1/L1TXDD2
AE151
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
39
Pinout
Table 20. MPC8250 TBGA Package Pinout List (continued)
Pin Name
Ball
PB24/FCC2_TXD2/L1RSYNCC2
AJ91
PB25/FCC2_TXD3/L1TSYNCC2/L1GNTC2
AE91
PB26/FCC2_MII_CRS/L1RXDC2
AJ71
PB27/FCC2_MII_COL/L1TXDC2
AH61
PB28/FCC2_MII_RX_ER/FCC2_RTS/L1TSYNCB2/L1GNTB2/TXD1
AE31
PB29/L1RSYNCB2/FCC2_MII_TX_EN
AE21
PB30/FCC2_MII_RX_DV/L1RXDB2
AC51
PB31/FCC2_MII_TX_ER/L1TXDB2
AC41
PC0/DREQ1/BRGO7/SMSYN2/L1CLKOA2
AB261
PC1/DREQ2/BRGO6/L1RQA2
AD291
PC2/FCC3_CD/DONE2
AE291
PC3/FCC3_CTS/DACK2/CTS4
AE271
PC4/SI2_L1ST4/FCC2_CD
AF271
PC5/SI2_L1ST3/FCC2_CTS
AF241
PC6/FCC1_CD
AJ261
PC7/FCC1_CTS
AJ251
PC8/CD4/RENA4/SI2_L1ST2/CTS3
AF221
PC9/CTS4/CLSN4/SI2_L1ST1/L1TSYNCA2/L1GNTA2
AE211
PC10/CD3/RENA3
AF201
PC11/CTS3/CLSN3/L1TXD3A2
AE191
PC12/CD2/RENA2
AE181
PC13/CTS2/CLSN2
AH181
PC14/CD1/RENA1
AH171
PC15/CTS1/CLSN1/SMTXD2
AG161
PC16/CLK16/TIN4
AF151
PC17/CLK15/TIN3/BRGO8
AJ151
PC18/CLK14/TGATE2
AH141
PC19/CLK13/BRGO7/SPICLK
AG131
PC20/CLK12/TGATE1
AH121
PC21/CLK11/BRGO6
AJ111
PC22/CLK10/DONE1
AG101
PC23/CLK9/BRGO5/DACK1
AE101
PC24/CLK8/TOUT4
AF91
PC25/CLK7/BRGO4
AE81
PC26/CLK6/TOUT3/TMCLK
AJ61
MPC8250 Hardware Specifications, Rev. 2
40
Freescale Semiconductor
Pinout
Table 20. MPC8250 TBGA Package Pinout List (continued)
Pin Name
Ball
PC27/FCC3_TXD/FCC3_TXD0/CLK5/BRGO3
AG21
PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2
AF31
PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1
AF21
PC30/CLK2/TOUT1
AE11
PC31/CLK1/BRGO1
AD11
PD4/BRGO8/FCC3_RTS/SMRXD2
AC281
PD5/DONE1
AD271
PD6/DACK1
AF291
PD7/SMSYN1FCC1_TXCLAV2
AF281
PD8/SMRXD1/BRGO5
AG251
PD9/SMTXD1/BRGO3
AH261
PD10/L1CLKOB2/BRGO4
AJ271
PD11/L1RQB2
AJ231
PD12
AG231
PD13
AJ221
PD14/L1CLKOC2/I2CSCL
AE201
PD15/L1RQC2/I2CSDA
AJ201
PD16/SPIMISO
AG181
PD17/BRGO2/SPIMOSI
AG171
PD18/SPICLK
AF161
PD19/SPISEL/BRGO
AH151
PD20/RTS4/TENA4/L1RSYNCA2
AJ141
PD21/TXD4/L1RXD0A2/L1RXDA2
AH131
PD22/RXD4/L1TXD0A2/L1TXDA2
AJ121
PD23/RTS3/TENA3
AE121
PD24/TXD3
AF101
PD25/RXD3
AG91
PD26/RTS2/TENA2
AH81
PD27/TXD2
AG71
PD28/RXD2
AE41
PD29/RTS1/TENA1
AG11
PD30/TXD1
AD41
PD31/RXD1
AD21
VCCSYN
AB3
VCCSYN1
B9
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
41
Pinout
Table 20. MPC8250 TBGA Package Pinout List (continued)
Pin Name
Ball
GNDSYN
AB1
CLKIN2
AE11
SPARE4 2
U5
PCI_MODE 3
SPARE6
AF25
2
V4
THERMAL0
4
AA1
THERMAL1
4
AG4
I/O power
AG21, AG14, AG8, AJ1, AJ2, AH1,
AH2, AG3, AF4, AE5, AC27, Y27,
T27, P27, K26, G27, AE25, AF26,
AG27, AH28, AH29, AJ28, AJ29,
C7, C14, C16, C20, C23, E10, A28,
A29, B28, B29, C27, D26, E25, H3,
M4, T3, AA4, A1, A2, B1, B2, C3,
D4, E5
Core Power
U28, U29, K28, K29, A9, A19, B19,
M1, M2, Y1, Y2, AC1, AC2, AH19,
AJ19, AH10, AJ10, AJ5
Ground
AA5, AF21, AF14, AF8, AE7, AF11,
AE17, AE23, AC26, AB25, Y26,
V25, T26, R25, P26, M25, K27, H25,
G26, D7, D10, D14, D16, D20, D23,
C9, E11, E13, E15, E19, E22, B3,
G5, H4, K5, M3, P5, T4, Y5, AA2,
AC3
1
The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive
DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.
2 Must be pulled down or left floating.
3 If PCI is not desired, this pin should be pulled up or left floating.
4 For information on how to use this pin, refer to MPC8260 PowerQUICC II Thermal Resistor Guide (AN2271/D)
available at www.freescale.com.
4.2
PBGA Package
The following figures and table represent the alternate 516 PBGA package. For information on the
standard package for the MPC8250, refer to Section 4.1, “TBGA Package.”
MPC8250 Hardware Specifications, Rev. 2
42
Freescale Semiconductor
Pinout
4.2.1
PBGA Pin Assignments
Figure 15 shows the pinout of the PBGA package as viewed from the top surface.
1
2
3
4 5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
A
B
B
C
D
C
D
E
E
F
G
F
G
H
H
J
J
K
L
K
L
M
M
N
N
P
R
P
R
T
U
T
U
V
V
W
Y
W
Y
AA
AA
AB
AB
AC
AD
AC
AD
AE
AE
AF
AF
1
2
3
4 5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Not to Scale
Figure 15. Pinout of the 516 PBGA Package (View from Top)
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
43
Pinout
Figure 16 shows the side profile of the PBGA package to indicate the direction of the top surface view.
Die
attach
Transfer molding compound
Wire bonds
Ball bond
Screen-printed
solder mask
Plated substrate via
Cu substrate traces
DIE
BT resin glass epoxy
1 mm pitch
Figure 16. Side View of the PBGA Package
Table 22 shows the pinout list of the PBGA package of the MPC8250. Table 21 defines conventions and
acronyms used in Table 22.
Table 21. Symbol Legend
Symbol
Meaning
OVERBAR
Signals with overbars, such as TA, are active low.
MII
Indicates that a signal is part of the media independent interface.
Table 22. MPC8250 PBGA Package Pinout List
Pin Name
Ball
BR
C16
BG
D2
ABB/IRQ2
C1
TS
D1
A0
D5
A1
E8
A2
C4
A3
B4
A4
A4
A5
D7
A6
D8
A7
C6
A8
B5
A9
B6
A10
C7
A11
C8
A12
A6
A13
D9
MPC8250 Hardware Specifications, Rev. 2
44
Freescale Semiconductor
Pinout
Table 22. MPC8250 PBGA Package Pinout List (continued)
Pin Name
Ball
A14
F11
A15
B7
A16
B8
A17
C9
A18
A7
A19
B9
A20
E11
A21
A8
A22
D11
A23
B10
A24
C11
A25
A9
A26
B11
A27
C12
A28
D12
A29
A10
A30
B12
A31
B13
TT0
E7
TT1
B3
TT2
F8
TT3
A3
TT4
C3
TBST
F5
TSIZ0
E3
TSIZ1
E2
TSIZ2
E1
TSIZ3
E4
AACK
D3
ARTRY
C2
DBG
A14
DBB/IRQ3
C15
D0
W4
D1
Y1
D2
V1
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
45
Pinout
Table 22. MPC8250 PBGA Package Pinout List (continued)
Pin Name
Ball
D3
P4
D4
N3
D5
K5
D6
J4
D7
G1
D8
AB1
D9
U4
D10
U2
D11
N6
D12
N1
D13
L1
D14
J5
D15
G3
D16
AA2
D17
W1
D18
T3
D19
T1
D20
M2
D21
K2
D22
J1
D23
G4
D24
U5
D25
T5
D26
P5
D27
P3
D28
M3
D29
K3
D30
H2
D31
G5
D32
AA1
D33
V2
D34
U1
D35
P2
D36
M4
D37
K4
MPC8250 Hardware Specifications, Rev. 2
46
Freescale Semiconductor
Pinout
Table 22. MPC8250 PBGA Package Pinout List (continued)
Pin Name
Ball
D38
H3
D39
F2
D40
Y2
D41
U3
D42
T2
D43
N2
D44
M5
D45
K1
D46
H4
D47
F1
D48
W2
D49
T4
D50
R3
D51
N4
D52
M1
D53
J2
D54
H5
D55
F3
D56
V3
D57
R5
D58
R2
D59
N5
D60
L2
D61
J3
D62
H1
D63
F4
DP0/RSRV/EXT_BR2
AB3
IRQ1/DP1/EXT_BG2
W5
IRQ2/DP2/TLBISYNC/EXT_DBG2
AC2
IRQ3/DP3/CKSTP_OUT/EXT_BR3
AA3
IRQ4/DP4/CORE_SRESET/EXT_BG3
AD1
IRQ5/DP5/TBEN/EXT_DBG3
AC1
IRQ6/DP6/CSE0
AB2
IRQ7/DP7/CSE1
Y3
PSDVAL
D15
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
47
Pinout
Table 22. MPC8250 PBGA Package Pinout List (continued)
Pin Name
Ball
TA
Y4
TEA
D16
GBL/IRQ1
E15
CI/BADDR29/IRQ2
D14
WT/BADDR30/IRQ3
E14
L2_HIT/IRQ4
A17
CPU_BG/BADDR31/IRQ5
B14
CPU_DBG
F13
CPU_BR
B17
CS0
AC6
CS1
AD6
CS2
AE6
CS3
AB7
CS4
AF7
CS5
AC7
CS6
AD7
CS7
AF8
CS8
AE8
CS9
AD8
CS10/BCTL1
AC8
CS11/AP0
AB8
BADDR27
C13
BADDR28
A12
ALE
D13
BCTL0
AF4
PWE0/PSDDQM0/PBS0
AA5
PWE1/PSDDQM1/PBS1
AE4
PWE2/PSDDQM2/PBS2
AD4
PWE3/PSDDQM3/PBS3
AF3
PWE4/PSDDQM4/PBS4
AB4
PWE5/PSDDQM5/PBS5
AE3
PWE6/PSDDQM6/PBS6
AF2
PWE7/PSDDQM7/PBS7
AD3
PSDA10/PGPL0
AE2
PSDWE/PGPL1
AD2
MPC8250 Hardware Specifications, Rev. 2
48
Freescale Semiconductor
Pinout
Table 22. MPC8250 PBGA Package Pinout List (continued)
Pin Name
Ball
POE/PSDRAS/PGPL2
AE1
PSDCAS/PGPL3
AC3
PGTA/PUPMWAIT/PGPL4/PPBS
W6
PSDAMUX/PGPL5
AA4
LWE0/LSDDQM0/LBS0/PCI_CFG0
AC9
LWE1/LSDDQM1/LBS1/PCI_CFG1
AD9
LWE2/LSDDQM2/LBS2/PCI_CFG2
AE9
LWE3/LSDDQM3/LBS3/PCI_CFG3
AF9
LSDA10/LGPL0/PCI_MODCKH0
AB6
LSDWE/LGPL1/PCI_MODCKH1
AF5
LOE/LSDRAS/LGPL2/PCI_MODCKH2
AE5
LSDCAS/LGPL3/PCI_MODCKH3
AD5
LGTA/LUPMWAIT/LGPL4/LPBS
AC5
LGPL5/LSDAMUX/PCI_MODCK
AB5
LWR
AF6
L_A14/PAR
AE13
L_A15/FRAME/SMI
AD15
L_A16/TRDY
AF16
L_A17/IRDY/CKSTP_OUT
AF15
L_A18/STOP
AE15
L_A19/DEVSEL
AE14
L_A20/IDSEL
AC17
L_A21/PERR
AD14
L_A22/SERR
AF13
L_A23/REQ0
AE20
L_A24/REQ1/HSEJSW
AC14
L_A25/GNT0
AC19
L_A26/GNT1/HSLED
AD13
L_A27/GNT2/HSENUM
AF21
L_A28/RST/CORE_SRESET
AF22
L_A29/INTA
AE21
L_A30/REQ2
AB14
L_A31/DLLOUT
AD20
LCL_D0/AD0
AB9
LCL_D1/AD1
AB10
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
49
Pinout
Table 22. MPC8250 PBGA Package Pinout List (continued)
Pin Name
Ball
LCL_D2/AD2
AC10
LCL_D3/AD3
AD10
LCL_D4/AD4
AE10
LCL_D5/AD5
AF10
LCL_D6/AD6
AF11
LCL_D7/AD7
AB12
LCL_D8/AD8
AB11
LCL_D9/AD9
AF12
LCL_D10/AD10
AE11
LCL_D11/AD11
AC13
LCL_D12/AD12
AC12
LCL_D13/AD13
AB13
LCL_D14/AD14
AD12
LCL_D15/AD15
AF14
LCL_D16/AD16
AF17
LCL_D17/AD17
AE16
LCL_D18/AD18
AD16
LCL_D19/AD19
AC16
LCL_D20/AD20
AB16
LCL_D21/AD21
AF18
LCL_D22/AD22
AE17
LCL_D23/AD23
AD17
LCL_D24/AD24
AB17
LCL_D25/AD25
AE18
LCL_D26/AD26
AD18
LCL_D27/AD27
AC18
LCL_D28/AD28
AE19
LCL_D29/AD29
AF20
LCL_D30/AD30
AD19
LCL_D31/AD31
AB18
LCL_DP0/C0/BE0
AE12
LCL_DP1/C1/BE1
AA13
LCL_DP2/C2/BE2
AC15
LCL_DP3/C3/BE3
AF19
IRQ0/NMI_OUT
A11
MPC8250 Hardware Specifications, Rev. 2
50
Freescale Semiconductor
Pinout
Table 22. MPC8250 PBGA Package Pinout List (continued)
Pin Name
Ball
IRQ7/INT_OUT/APE
E5
TRST
F22
TCK
A24
TMS
C24
TDI
A25
TDO
B24
TRIS
C19
PORESET
B25
HRESET
D24
SRESET
E23
QREQ
D18
RSTCONF
E24
MODCK1/AP1/TC0/BNKSEL0
B16
MODCK2/AP2/TC1/BNKSEL1
F16
MODCK3/AP3/TC2/BNKSEL2
A15
XFC
A18
CLKIN1
G22
PA0/RESTART1/DREQ3
AC20 1
PA1/REJECT1/DONE3
AC211
PA2/CLK20/DACK3
AF251
PA3/CLK19/DACK4/L1RXD1A2
AE241
PA4/REJECT2/DONE4
AA211
PA5/RESTART2/DREQ4
AD251
PA6
AC241
PA7/SMSYN2
AA221
PA8/SMRXD2
AA231
PA9/SMTXD2
Y261
PA10/MSNUM5
W221
PA11/MSNUM4
W231
PA12/MSNUM3
V261
PA13/MSNUM2
V251
PA14/FCC1_RXD3
T221
PA15/FCC1_RXD2
T251
PA16/FCC1_RXD1
R241
PA17/FCC1_RXD0/FCC1_RXD
P221
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
51
Pinout
Table 22. MPC8250 PBGA Package Pinout List (continued)
Pin Name
Ball
PA18/FCC1_TXD0/FCC1_TXD
N261
PA19/FCC1_TXD1
N231
PA20/FCC1_TXD2
K261
PA21/FCC1_TXD3
L231
PA22
K231
PA23
H261
PA24/MSNUM1
F251
PA25/MSNUM0
D261
PA26/FCC1_MII_RX_ER
D251
PA27/FCC1_MII_RX_DV
C251
PA28/FCC1_MII_TX_EN
C221
PA29/FCC1_MII_TX_ER
B211
PA30/FCC1_MII_CRS/FCC1_RTS
A201
PA31/FCC1_MII_COL
A191
PB4/FCC3_TXD3/L1RSYNCA2/ FCC3_RTS
AD211
PB5/FCC3_TXD2/L1TSYNCA2/ L1GNTA2
AD221
PB6/FCC3_TXD1/L1RXDA2/L1RXD0A2
AC221
PB7/FCC3_TXD0/FCC3_TXD/ L1TXDA2/L1TXD0A2
AE261
PB8/FCC3_RXD0/FCC3_RXD/TXD3
AB231
PB9/FCC3_RXD1/L1TXD2A2
AC261
PB10/FCC3_RXD2
AB261
PB11/FCC3_RXD3
AA251
PB12/FCC3_MII_CRS/TXD2
W261
PB13/FCC3_MII_COL/L1TXD1A2
W251
PB14/FCC3_MII_TX_EN/RXD3
V241
PB15/FCC3_MII_TX_ER/RXD2
U241
PB16/FCC3_MII_RX_ER/CLK18
R221
PB17/FCC3_MII_RX_DV/CLK17
R231
PB18/FCC2_RXD3/L1CLKOD2/ L1RXD2A2
M231
PB19FCC2_RXD2/L1RQD2/L1RXD3A2
L241
PB20/FCC2_RXD1/L1RSYNCD2/ L1TXD1A1
K241
PB21/FCC2_RXD0/FCC2_RXD/ L1TSYNCD2/L1GNTD2
L211
PB22/FCC2_TXD0/FCC2_TXD/ L1RXDD2
P251
PB23/FCC2_TXD1/L1TXDD2
N251
PB24/FCC2_TXD2/L1RSYNCC2
E261
MPC8250 Hardware Specifications, Rev. 2
52
Freescale Semiconductor
Pinout
Table 22. MPC8250 PBGA Package Pinout List (continued)
Pin Name
Ball
PB25/FCC2_TXD3/L1TSYNCC2/ L1GNTC2
H231
PB26/FCC2_MII_CRS/L1RXDC2
C261
PB27/FCC2_MII_COL/L1TXDC2
B261
PB28/FCC2_MII_RX_ER/FCC2_RTS/ L1TSYNCB2/L1GNTB2/TXD1
A221
PB29/L1RSYNCB2/ FCC2_MII_TX_EN
A211
PB30/FCC2_MII_RX_DV/L1RXDB2
E201
PB31/FCC2_MII_TX_ER/L1TXDB2
C201
PC0/DREQ1/BRGO7/SMSYN2/ L1CLKOA2
AE221
PC1/DREQ2/BRGO6/L1RQA2
AA191
PC2/FCC3_CD/DONE2
AF241
PC3/FCC3_CTS/DACK2/CTS4
AE251
PC4/SI2_L1ST4/FCC2_CD
AB221
PC5/SI2_L1ST3/FCC2_CTS
AC251
PC6/FCC1_CD
AB251
PC7/FCC1_CTS
AA241
PC8/CD4/RENA4/SI2_L1ST2/CTS3
Y241
PC9/CTS4/CLSN4/SI2_L1ST1/ L1TSYNCA2/L1GNTA2
U221
PC10/CD3/RENA3
V231
PC11/CTS3/CLSN3/L1TXD3A2
U231
PC12/CD2/RENA2
T261
PC13/CTS2/CLSN2
R261
PC14/CD1/RENA1
P261
PC15/CTS1/CLSN1/SMTXD2
P241
PC16/CLK16/TIN4
M261
PC17/CLK15/TIN3/BRGO8
L261
PC18/CLK14/TGATE2
M241
PC19/CLK13/BRGO7/SPICLK
L221
PC20/CLK12/TGATE1
K251
PC21/CLK11/BRGO6
J251
PC22/CLK10/DONE1
G261
PC23/CLK9/BRGO5/DACK1
F261
PC24/CLK8/TOUT4
G241
PC25/CLK7/BRGO4
E251
PC26/CLK6/TOUT3/TMCLK
G231
PC27/FCC3_TXD/FCC3_TXD0/CLK5/ BRGO3
B231
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
53
Pinout
Table 22. MPC8250 PBGA Package Pinout List (continued)
Pin Name
Ball
PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2
E221
PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1
E211
PC30/CLK2/TOUT1
D211
PC31/CLK1/BRGO1
B201
PD4/BRGO8/FCC3_RTS/SMRXD2
AF231
PD5/DONE1
AE231
PD6/DACK1
AB211
PD7/SMSYN1/FCC1_TXCLAV2
AD231
PD8/SMRXD1/BRGO5
AD261
PD9/SMTXD1/BRGO3
Y221
AB241
PD10/L1CLKOB2/BRGO4
Y231
PD11/L1RQB2
PD12
AA261
PD13
W241
PD14/L1CLKOC2/I2CSCL
V221
PD15/L1RQC2/I2CSDA
U261
PD16/SPIMISO
T231
PD17/BRGO2/SPIMOSI
R251
PD18/SPICLK
P231
PD19/SPISEL/BRGO1
N221
PD20/RTS4/TENA4/L1RSYNCA2
M251
PD21/TXD4/L1RXD0A2/L1RXDA2
L251
PD22/RXD4L1TXD0A2/L1TXDA2
J261
PD23/RTS3/TENA3
K221
PD24/TXD3
G251
PD25/RXD3
H241
PD26/RTS2/TENA2
F241
PD27/TXD2
H221
PD28/RXD2
B221
PD29/RTS1/TENA1
D221
PD30/TXD1
C211
PD31/RXD1
E191
VCCSYN
D19
VCCSYN1
K6
GNDSYN
B18
MPC8250 Hardware Specifications, Rev. 2
54
Freescale Semiconductor
Package Description
Table 22. MPC8250 PBGA Package Pinout List (continued)
Pin Name
Ball
CLKIN2
SPARE4
K21
2
C14
PCI_MODE 3
AD24
SPARE62
B15
4
E17
4
C23
THERMAL0
THERMAL1
I/O power
E6, F6, H6, L5, L6, P6, T6, U6, V5,
Y5, AA6, AA8, AA10, AA11, AA14,
AA16, AA17, AB19, AB20, W21,
U21, T21, P21, N21, M22, J22,
H21, F21, F19, F17, E16, F14,
E13, E12, F10, E10, E9
Core Power
L3, V4, W3, AC11, AD11, AB15,
U25, T24, J24, H25, F23, B19,
D17, C17, D10, C10
Ground
A2, B1, B2, A5, C5, C18, D4, D6,
G2, L4, P1, R1, R4, AC4, AE7,
AC23, Y25, N24, J23, A23, D23,
D20, E18, A13, A16, K10, K11,
K12, K13, K14, K15, K16, K17,
L10, L11, L12, L13, L14, L15, L16,
L17, M10, M11, M12, M13, M14,
M15, M16, M17, N10, N11, N12,
N13, N14, N15, N16, N17, P10,
P11, P12, P13, P14, P15, P16,
P17, R10, R11,R12, R13, R14,
R15, R16, R17, T10, T11, T12,
T13, T14, T15, T16, T17, U10,
U11, U12, U13, U14, U15, U16,
U17
1
The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive
DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.
2 Must be pulled down or left floating.
3
If PCI is not desired, must be pulled up or left floating.
4 For information on how to use this pin, refer to MPC8260 PowerQUICC II Thermal Resistor Guide (AN2271/D).
5
Package Description
The following sections provide the package parameters and mechanical dimensions.
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
55
Package Description
5.1
Package Parameters
Package parameters are provided in Table 23.
Table 23. Package Parameters
Package
ZU
Devices
MPC8250
Outline
(mm)
Type
Interconnects
Pitch
(mm)
Nominal Unmounted
Height (mm)
37.5 × 37.5
TBGA
480
1.27
1.55
516
1
2.25
VV
ZO
VR
5.2
TBGA (Pb free)
27 × 27
PBGA
PBGA (Pb free)
Mechanical Dimensions
This section discusses the TBGA and PBGA package dimensions.
MPC8250 Hardware Specifications, Rev. 2
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Freescale Semiconductor
Package Description
5.2.1
TBGA Package Dimensions
Figure 17 provides the mechanical dimensions and bottom surface nomenclature of the 480 TBGA
package.
Notes:
1. Dimensions and Tolerancing per
ASME Y14.5M-1994.
2. Dimensions in millimeters.
3. Dimension b is measured at the
Millimeters
Dim
Min
Max
A
1.45
1.65
A1
0.60
0.70
A2
0.85
0.95
A3
0.25
—
b
0.65
0.85
D
37.50 BSC
D1
35.56 REF
e
1.27 BSC
E
37.50 BSC
E1
35.56 REF
Figure 17. Mechanical Dimensions and Bottom Surface Nomenclature—480 TBGA
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
57
Package Description
5.2.2
PBGA Package Dimensions
Figure 18 provides the mechanical dimensions and bottom surface nomenclature of the 516 PBGA
package.
Figure 18. Mechanical Dimensions and Bottom Surface Nomenclature—516 PBGA
MPC8250 Hardware Specifications, Rev. 2
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Freescale Semiconductor
Ordering Information
6
Ordering Information
Figure 19 provides an example of the Freescale part numbering nomenclature for the MPC8250. In
addition to the processor frequency, the part numbering scheme also consists of a part modifier that
indicates any enhancement(s) in the part from the original production design. Each part number also
contains a revision code that refers to the die mask revision number and is specified in the part numbering
scheme for identification purposes only. For more information, contact your local Freescale sales office.
MPC 8250 A C ZU XXX X
Product Code
Die Revision Level
Device Number
Processor Frequency
(CPU/CPM/Bus)
Process Technology
(A = 0.25 micron)
Package
ZU = 480 TBGA
VV = 480 TBGA (Pb free)
ZO = 516 PBGA
VR = 516 PBGA (Pb free)
Temperature Range
(Blank = 0 to 105 °C
C = –40 to 105 °C)
Figure 19. Freescale Part Number Key
7
Document Revision History
Table 24 provides a revision history for this template.
Table 24. Document Revision History
Revision
Date
Substantive Changes
2
7/2009
Updated TBGA and PBGA packaging information.
1
3/2005
Document template update
0.9
8/2003
•
•
•
•
•
•
•
•
•
•
•
0.8
11/2002 Table 22, “VR Pinout”: Addition of C18 to the Ground (GND) pin list (page 53)
0.7
10/2002 Table 22, “VR Pinout”: Addition of L3 to the Core (VDDx) pin list (page 53)
Table 2: Modification to supply voltage ranges reflected in notes 2, 3, and 4
Addition of VCCSYN to “Note: Core, PLL, and I/O Supply Voltages” following Table 2
Addition of Figure 2
Addition of note 1 to Table 3
Table 4: Changes to θJA. Addition of θJB and θJC
Table 7, Figure 8: Addition of sp42a/sp43a
Figure 3 through Figure 8: Addition of notes or modifications
Table 9: Change to sp10
Table 14, Table 16, and Table 18: Removal of PLL bypass mode from clock tables
Table 20 and Table 22: Addition of note 1
Addition of SPICLK to PC19 in Table 20 and Table 22. It is documented correctly in the
MPC8260 PowerQUICC II™ Family Reference Manual but had previously been omitted from
Table 20 and Table 22.
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
59
Document Revision History
Table 24. Document Revision History (continued)
Revision
Date
Substantive Changes
0.6
10/2002 Table 22, “VR Pinout”: corrected ball assignment for the following pins—A12–A17, TA, PD5, PC2.
0.5
9/2002
Addition of VR (516 PBGA) package information. Refer to sections 2.2, 4.2, and 5.
0.4
5/2002
•
•
•
•
•
0.3
3/2002
• Table 20: modified note to pin AF25.
0.2
3/2202
• Table 20: modified notes to pins AE11 and AF25.
• Table 20: added note to pins AA1 and AG4 (Therm0 and Therm1).
0.1
2/2002
• Note 2 for Table 4 (changes in italics): “...greater than or equal to 266 MHz, 200 MHz CPM...”
• Table 18: core and bus frequency values for the following ranges of MODCK_HMODCK:
0011_000 to 0011_100 and 1011_000 to 1011_1000
• Table 20: footnotes added to pins at AE11, AF25, U5, and V4.
0
Table 2: Notes 2 and 3
Addition of note on page 8:VDDH and VDD tracking
Table 14: Note 3
Table 16: Note 1
Table 18: Note 3
11/2001 Initial version
MPC8250 Hardware Specifications, Rev. 2
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Document Revision History
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MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
61
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Rev. 2
07/2009
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