FUJITSU SEMICONDUCTOR DATA SHEET DS04-27234-1E ASSP For Power Supply Applications (Secondary Battery) DC/DC Converter IC for Charging Li-ion Battery with Synchronous Rectifier MB39A107 ■ DESCRIPTION The MB39A107 is a DC/DC converter IC suitable for down-conversion, using pulse-width modulation (PWM) charging and enabling output voltage to be set to any desired level from 1 cell to 4 cells. The MB39A107 adopts output for Nch MOS drive of synchronous rectification type. The MB39A107 can be used to monitor the current in an AC adapter or battery, as it contains a current amplifier that can set an offset voltage. It can also be used for applications such as setting the charging voltages for 2 batteries. The MB39A107 provides a broad power supply voltage range and low standby current as well as high efficiency, making it ideal for use as a built-in charging device in products such as notebook PC. ■ FEATURES • • • • • • Built-in low-current control circuits in two systems (supporting dynamically controlled charging) The charge current value can be analog controlled (+INE1 and +INE2 terminal) Built-in synchronous rectification system output for Nch MOS FET Built-in charge pump for driving high-side Nch MOS, providing 100% on-duty support Built-in AC adapter detection function Output voltage setting accuracy : 4.2 V ± 0.74 % (Ta = − 10 °C to + 85 °C) (Continued) ■ PACKAGE 30-pin plastic TSSOP (FPT-30P-M04) MB39A107 (Continued) • Built-in high accuracy current detection amplifier : ± 5 % (input voltage difference at 100 mV) : ±15 % (input voltage difference at 20 mV) • Output voltage setting using external resistor : 1 cell to 4 cells • Oscillation frequency range : 100 kHz to 1 MHz • In standby mode, leave output voltage setting resistor open to prevent inefficient current loss. • Built-in standby current function : 0 µA (Typ) • Built-in soft-start function independent of loads 2 MB39A107 ■ PIN ASSIGNMENT (TOP VIEW) VCC 1 30 VB +INUV 2 29 CB OUTC1 3 28 OUT-1 −INC1 4 27 VS +INC1 5 26 OUT-2 IOFA1 6 25 PGND +INE1 7 24 OUT-CP −INE1 8 23 CTL-2 FB1 9 22 CTL-1 OUTC2 10 21 GND −INC2 11 20 VREF +INC2 12 19 RT +INE2 13 18 CS −INE2 14 17 OUTD FB23 15 16 −INE3 (FPT-30P-M04) 3 MB39A107 ■ PIN DESCRIPTION 4 Pin No. Symbol I/O Descriptions 1 VCC 2 + INUV I Low input voltage detection comparater (UV Comp.) input terminal 3 OUTC1 O Current detection amplifier (Current Amp1) output terminal 4 − INC1 I Current detection amplifier (Current Amp1) input terminal 5 + INC1 I Current detection amplifier (Current Amp1) input terminal 6 IOFA1 I Current detection amplifier (Current Amp1) offset voltage input terminal 7 + INE1 I Error amplifier (Error Amp1) non-inverted input terminal 8 − INE1 I Error amplifier (Error Amp1) inverted input terminal 9 FB1 O Error amplifier (Error Amp1) output terminal 10 OUTC2 O Current detection amplifier (Current Amp2) output terminal 11 − INC2 I Current detection amplifier (Current Amp2) input terminal 12 + INC2 I Current detection amplifier (Current Amp2) input terminal 13 + INE2 I Error amplifier (Error Amp2) non-inverted input terminal 14 − INE2 I Error amplifier (Error Amp2) inverted input terminal 15 FB23 O Error amplifier (Error Amp2, 3) output terminal 16 − INE3 I Error amplifier (Error Amp3) inverted input terminal 17 OUTD O With IC in standby mode, this terminal is set to Hi-Z to prevent loss of current through output voltage setting resistance. Set CTL terminal to “H” level to output “L” level. 18 CS Soft-start capacitor connection terminal 19 RT Triangular waveform oscillation frequency setting resistor connection terminal 20 VREF O Reference voltage output terminal 21 GND Ground terminal 22 CTL-1 I DC/DC converter block power supply control terminal 23 CTL-2 I Current detection amplifier (Current Amp1) power supply control terminal 24 OUT-CP O External main-side FET charge pump output terminal for driving gate 25 PGND Ground teriminal 26 OUT-2 O External synchronous rectification-side FET output terminal for driving gate 27 VS External main-side FET source connection terminal 28 OUT-1 O External main-side FET output terminal for driving gate 29 CB This terminal generates a voltage of “VCC + about 5 V” with a capacitor and an SBD connected to the OUT-CP, VB, and CB terminals. 30 VB O Output circuit bias output terminal Reference voltage, control circuit power supply terminal MB39A107 ■ BLOCK DIAGRAM +INUV 2 OUTC1 3 <Current Amp1> +INC1 5 −INC1 4 IOFA1 6 VCC 1 <UV Comp.> + + ×25 − − 4.05 V/4.20 V Offset adjustment VREF − −INE1 8 +INE1 7 <Error Amp1> − + + + 30 VB VB Reg. <−INE Comp.> (6.0 V) + 29 CB 3.92 V/4.00 V 4.2 V <PWM Comp.> + + − 9 −INE2 14 OUTC2 10 +INC2 12 −INC2 11 <Current Amp2> + ×25 − Drv -1 Dead Time Modulation FB1 27 VS VREF Drv -2 26 OUT-2 Drv -CP 24 OUT-CP −2.5 V −1.5 V <Error Amp2> − + + +INE2 13 28 OUT-1 25 PGND H : UVLO, UV release FB23 15 UVLO −INE3 16 <Error Amp3> − + + OUTD 17 VB UVLO VREF UVLO 4.2 V Current Amp1 ON/OFF <SOFT> VREF 23 CTL-2 VCC 10 µA <OSC> CS 18 CT 45 pF 4.2 V bias <REF> <CTL> DC/DC ON/OFF 22 CTL-1 VREF 5.0 V 19 RT 20 VREF 21 GND 5 MB39A107 ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Power supply voltage VCC Boot voltage VCB Control input voltage VCTL Output current IoUT Power dissipation PD Storage temperature TSTG Rating Unit Min Max 27 V CB terminal 32 V CTL-1 terminal, CTL-2 terminal 27 V 60 mA 1390* mW − 55 +125 °C Ta ≤ +25 °C * : The packages are mounted on the dual-sided epoxy board (10 cm × 10 cm) . WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 6 MB39A107 ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Power supply voltage VCC Boot voltage VCB Reference voltage output current Bias output current Value Unit Min Typ Max 7 25 V CB terminal 30 V IREF VREF terminal −1 0 mA IVB VB terminal −1 0 mA VINE + INE1, + INE2, + INE3, − INE1, − INE2 terminal 0 VCC − 1.8 V VINC + INC1, + INC2, − INC1, − INE2 terminal 0 VCC V VINUV + INUV terminal 0 VCC V IOFA1 terminal input voltage VIOFA1 0 5 V OUTD terminal output voltage VOUTD 0 17 V OUTD terminal output current IOUTD 0 2 mA CTL terminal input voltage VCTL 0 25 V Output current IOUT − 45 + 45 mA Input voltage IOUT Main side Duty ≤ 5% (t = 1/fosc × Duty) − 800 + 800 mA IOUT Synchronous rectification side Duty ≤ 5% (t = 1/fosc × Duty) − 1200 + 1200 mA Peak output current Oscillation frequency fOSC 100 500 1000 kHz Timing resistor RT 22 47 200 kΩ Soft-start capacitor CS 0.022 1.0 µF Charge pump capacitor CCP 0.33 µF CB terminal capacitor CCB 0.47 1.0 µF Bias output capacitor CVB 0.47 1.0 µF Reference voltage output capacitor CREF 0.1 1.0 µF Ta − 30 + 25 + 85 °C Operating ambient temperature WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 7 MB39A107 ■ ELECTRICAL CHARACTERISTICS (VCC = 19 V, VB = 0 mA, VREF = 0 mA, Ta = + 25 °C) Parameter Triangular Wave Oscillator Block [OSC] VREF1 20 VREF2 Conditions Value Unit Typ Max Ta = + 25 °C 4.967 5.000 5.041 V 20 Ta = − 10 °C to + 85 °C 4.95 5.00 5.05 V Line 20 VCC = 7 V to 25 V 3 10 mV Load 20 VREF = 0 mA to − 1 mA 1 10 mV los 20 VREF = 1 V − 50 − 25 − 12 mA VTLH 30 VB = 3.80 4.00 4.20 V VTHL 30 VB = 3.10 3.30 3.50 V VH 30 0.49 0.70 0.91 V VTLH 20 VREF = 2.6 2.8 3.0 V VTHL 20 VREF = 2.4 2.6 2.8 V Hysteresis width VH 20 0.05 0.20 0.35 V Charge current ICS 18 − 14 − 10 −6 µA Oscillation frequency fOSC 28 RT = 47 kΩ 450 500 550 kHz ∆fOSC/ fOSC 28 Ta = − 30 °C to +85 °C 1* % VTH1 8, 9 FB1 = 2 V, Ta = +25 °C 4.179 4.200 4.221 V VTH2 8, 9 FB1 = 2 V, Ta = − 10 °C to +85 °C 4.169 4.200 4.231 V VIO 7, 8 FB1 = 2 V 1 5 mV IB 7, 8 − INE1 = + INE1 = 0 V − 100 − 30 nA AV 7, 8, DC 9 100* dB BW 7, 8, AV = 0 dB 9 1.2* MHz Reference Voltage Input stability Block Load stability [Ref] Short-circuit output current Soft-start Circuit Block [SOFT] Pin No. Min Output voltage Under Voltage (VCC) Lockout Circuit Block [UVLO] Symbol Threshold voltage Hysteresis width Threshold voltage Frequency temperature variation Threshold voltage Input offset voltage Input bias current Error Amp Block Voltage gain [Error Amp1] Frequency bandwidth Output voltage Output source current Output sink current VFBH 9 4.8 5.0 V VFBL 9 0.8 0.9 V ISOURCE 9 FB1 = 2 V − 120 − 60 µA ISINK 9 FB1 = 2 V 2.0 4.0 mA * : Standard design value (Continued) 8 MB39A107 (VCC = 19 V, VB = 0 mA, VREF = 0 mA, Ta = + 25 °C) Symbol Pin No. VIO 13, 14 FB23 = 2 V Input bias current IB 13, 14 − INE2 = + INE2 = 0 V Voltage gain AV 13, 14, 15 BW 13, 14, 15 VFBH 15 Parameter Input offset voltage Error Amp Block [Error Frequency bandwidth Amp2] Output voltage Output source current Output sink current Error Amp Frequency bandwidth Block [Error Output voltage Amp3] Unit Min Typ Max 1 5 mV − 100 − 30 nA DC 100* dB AV = 0 dB 1.2* MHz 4.8 5.0 V VFBL 15 0.8 0.9 V 15 FB23 = 2 V − 120 − 60 µA ISINK 15 FB23 = 2 V 2.0 4.0 mA VTH1 15, 16 FB23 = 2 V, Ta = +25 °C 4.179 4.200 4.221 V VTH2 15, 16 FB23 = 2 V, Ta = − 10 °C to +85 °C 4.169 4.200 4.231 V AV 15, 16 DC 100* dB BW 15, 16 AV = 0 dB 1.2* MHz VFBH 15 4.8 5.0 V VFBL 15 0.8 0.9 V ISOURCE 15 FB23 = 2 V − 120 − 60 µA Output sink current ISINK 15 FB23 = 2 V 2.0 4.0 mA OUTD terminal output leakage current ILEAK 17 OUTD = 17 V 0 1 µA OUTD terminal output ON resistor RON 17 OUTD = 1 mA 35 50 Ω VOUTC1 3 + INC1 = 9 V to VCC, 2.375 ∆VIN = − 100 mV, IOFA1 = 0 V 2.5 2.625 V VOUTC2 3 + INC1 = 9 V to VCC, ∆VIN = − 20 mV, IOFA1 = 0 V 0.425 0.5 0.575 V VOUTC3 3 + INC1 = 0 V to 9 V, ∆VIN = − 100 mV, IOFA1 = 0 V 2.25 2.5 2.75 V VOUTC4 3 + INC1 = 0 V to 9 V, ∆VIN = − 100 mV, IOFA1 = 0 V 0.25 0.5 0.75 V 24.25 25 25.75 V/V Output source current Current Detection Amp Block [Current Amp1] Value ISOURCE Threshold voltage Voltage gain Conditions Current detection voltage Voltage gain AV 3, 4, + INC1 = 3 V to VCC, 5 ∆VIN = − 20 mV, IOFA1 = 0 V * : Standard design value (Continued) 9 MB39A107 (VCC = 19 V, VB = 0 mA, VREF = 0 mA, Ta = + 25 °C) Symbol Pin No. IINC1 4, 5 IINC2 4, 5 Frequency bandwidth BW 3, 4, AV = 0 dB 5 IOFA1 terminal input current IOFA1 6 VOUTCH 3 VOUTCL 3 Output source current ISOURCE 3 Output sink current ISINK Parameter Unit Typ Max + INC1 = − INC1 = 19 V 50 75 µA CTL-2 = 0 V, + INC1 = − INC1 = 19 V 0 1 µA 0.2* MHz − 100 − 30 nA 5.3 5.6 V 20 200 mV OUTC = 2 V −2 −1 mA 3 OUTC = 2 V 150 300 µA VOUTC1 10 + INC2 = 9 V to VCC, 2.375 ∆VIN = − 100 mV, IOFA1 = 0 V 2.5 2.625 V VOUTC2 10 + INC2 = 9 V to VCC, ∆VIN = − 20 mV, IOFA1 = 0 V 0.425 0.5 0.575 V VOUTC3 10 + INC2 = 0 V to 9 V, ∆VIN = − 100 mV, IOFA1 = 0 V 2.25 2.5 2.75 V VOUTC4 10 + INC2 = 0 V to 9 V, ∆VIN = − 100 mV, IOFA1 = 0 V 0.25 0.5 0.75 V AV 10, 11, 12 + INC2 = 3 V to VCC, ∆VIN = − 100 mV 24.25 25 25.75 V/V IINC1 11, 12 + INC2 = − INC2 = 19 V 50 75 µA IINC2 11, 12 CTL-1 = 0 V, + INC2 = − INC2 = 19 V 0 1 µA BW 10, 11, 12 AV = 0 dB 0.2* MHz VOUTCH 10 5.3 5.6 V VOUTCL 10 20 200 mV Output source current ISOURCE 10 OUTC2 = 2 V −2 −1 mA Output sink current 10 OUTC2 = 2 V 150 300 µA Output voltage Current detection voltage Current Detection Amp Block [Current Amp2] Value Min Input current Current Detection Amp Block [Current Amp1] Conditions Voltage gain Input current Frequency bandwidth Output voltage PWM Comparator Block Threshold voltage [PWM Comp.] ISINK IOFA1 = 2.5 V VTL 9, 15 Duty cycle = 0% 1.4 1.5 V VTH 9, 15 Duty cycle = 100% 2.5 2.6 V * : Standard design value (Continued) 10 MB39A107 (Continued) (VCC = 19 V, VB = 0 mA, VREF = 0 mA, Ta = + 25 °C) Parameter Symbol Pin No. Conditions ISOURCE 28 ISOURCE Value Unit Min Typ Max Main side, Duty ≤ 5% (t = 1/fOSC × Duty) − 600* mA 26 Synchronous rectification side, Duty ≤ 5% (t = 1/fOSC × Duty) − 800* mA ISINK 28 Main side, Duty ≤ 5% (t = 1/fOSC × Duty) 800* mA ISINK 26 Synchronous rectification side, Duty ≤ 5% (t = 1/fOSC × Duty) 1000* mA tD1 26, 28 100* ns tD2 26, 28 100* ns ROH 24 OUT-CP = − 45 mA 2 10 Ω ISINK 24 OUT-CP = 10 V 200* mA Low Input Threshold voltage Voltage Detection Comparator Hysteresis width Block Input bias current [UV Comp.] VTLH 2, 28 + INUV = 4.12 4.2 4.28 V VTHL 2, 28 + INUV = 3.97 4.05 4.13 V VH 2, 28 0.15 V IINUV 2 + INUV = 0 V − 200 − 100 nA Battery Threshold voltage Voltage Detection Comparator Block Hysteresis width [ − INE Comp.] VTLH 16 − INE3 = 3.89 3.93 3.97 V VTHL 16 − INE3 = 3.85 3.89 3.93 V VH 16 0.04 V Output voltage VB 30 5.9 6 6.1 V ON condition VON 22, 23 CTL-1, CTL-2 terminal 2 25 V OFF condition VOFF 22, 23 CTL-1, CTL-2 terminal 0 0.8 V ICTLH 22, 23 CTL-1 = CTL-2 = 5 V 100 150 µA ICTLL 22, 23 CTL-1 = CTL-2 = 0 V 0 1 µA Output source current Output Block [Drv-1, 2] Output sink current Dead time Charge Output ON resistor Pump Block Output sink current [Drv-CP] Bias Voltage Block [VB] Control Block [CTL] Input current Standby current General Power supply current ICCS 1 CTL-1 = CTL-2 = 0 V 0 10 µA ICC1 1 CTL-1 = CTL-2 = 5 V 12 18 mA ICC2 1 CTL-1 = 5 V, CTL-2 = 0 V 10.5 15.8 mA ICC3 1 CTL-1 = 0 V, CTL-2 = 5 V 2.1 3.2 mA * : Standard design value 11 MB39A107 ■ TYPICAL CHARACTERISTICS Power supply current ICC (mA) 10 8 6 4 Ta = +25 °C CTL1 = 5 V CTL2 = 5 V RT = OPEN 2 0 0 5 10 15 20 25 Power Supply Current vs. Power Supply Voltage Power supply current ICC (mA) Power Supply Current vs. Power Supply Voltage 10 8 6 4 Ta = +25 °C CTL1 = 5 V CTL2 = 0 V RT = OPEN 2 0 0 Power supply voltage VCC (V) 5 10 15 20 25 Power supply voltage VCC (V) Power supply current ICC (mA) Power Supply Current vs. Power Supply Voltage 10 Ta = +25 °C CTL1 = 0 V CTL2 = 5 V RT = OPEN 8 6 4 2 0 0 5 10 15 20 25 Power supply voltage VCC (V) 800 9 8 700 7 600 6 VREF 500 5 400 4 300 3 ICTL 200 2 100 1 0 0 30 0 5 10 15 20 25 CTL1 terminal voltage VCTL (V) 1000 10 Ta = +25 °C VCC = 19 V VREF = 0 mA 900 800 700 9 8 7 600 6 VREF 500 5 400 4 300 3 ICTL 200 2 100 1 0 0 5 10 15 20 25 0 30 Reference voltage VREF (V) 10 Ta = +25 °C VCC = 19 V VREF = 0 mA 900 CTL2 terminal current ICTL (µA) 1000 CTL2 Terminal Current, Reference Voltage vs. CTL2 Terminal Voltage Reference voltage VREF (V) CTL1 terminal current ICTL (µA) CTL1 Terminal Current, Reference Voltage vs. CTL1 Terminal Voltage CTL2 terminal voltage VCTL (V) (Continued) 12 MB39A107 Reference Voltage vs. Load Current Reference Voltage vs. Power Supply Voltage 10 Reference voltage VREF (V) Reference voltage VREF (V) 10 Ta = +25 °C CTL1 = 5 V CTL2 = 5 V VREF = 0 mA 8 6 4 2 0 0 5 10 15 20 Ta = +25 °C VCC = 19 V CTL1 = 5 V CTL2 = 5 V 8 6 4 2 0 25 0 5 Power supply voltage VCC (V) 5.02 5.00 4.98 4.96 4.94 4.92 −40 −20 0 20 40 60 80 100 Triangular wave oscillation frequency fOSC (kHz) Reference voltage VREF (V) 5.04 20 25 10000 VCC = 19 V CTL1 = 5 V CTL2 = 5 V VREF = 0 mA 5.06 15 30 35 Triangular Wave Oscillation Frequency vs. Timing Resistor Reference Voltage vs. Ambient Temperature 5.08 10 Load current IREF (mA) Ta = +25 °C VCC = 19 V CB = 25 V CTL1 = 5 V CTL2 = 5 V 1000 100 Ambient temperature Ta ( °C) 10 1 10 100 1000 Timing resistor RT (kΩ) Triangular Wave Oscillation Frequency vs. Power Supply Voltage 560 VCC = 19 V CB = 25 V CTL1 = 5 V CTL2 = 5 V RT = 47 kΩ 540 520 500 480 460 440 −40 −20 0 20 40 60 Ambient temperature Ta ( °C) 80 100 560 Triangular wave oscillation frequency fOSC (kHz) Triangular wave oscillation frequency fOSC (kHz) Triangular Wave Oscillation Frequency vs. Ambient Temperature Ta = +25 °C CB = VCC + 6 V CTL1 = 5 V CTL2 = 5 V RT = 47 kΩ 540 520 500 480 460 440 0 5 10 15 20 25 30 Power supply voltage VCC (V) (Continued) 13 MB39A107 Error Amplifier 3 Threshold Voltage vs. Ambient Temperature Error Amplifier 1 Threshold Voltage vs. Ambient Temperature 4.25 VCC = 19 V CTL1 = 5 V CTL2 = 5 V 4.24 4.23 Error amplifier 3 threshold voltage VTH (V) Error amplifier 1 threshold voltage VTH (V) 4.25 4.22 4.21 4.20 4.19 4.18 4.17 4.16 4.15 −40 −20 0 20 40 60 80 4.23 4.22 4.21 4.20 4.19 4.18 4.17 4.16 4.15 −40 100 VCC = 19 V CTL1 = 5 V CTL2 = 5 V 4.24 Ambient temperature Ta ( °C) −20 0 20 40 60 80 100 Ambient temperature Ta ( °C) Error Amplifer, Gain and Phase vs. Frequency Ta = +25 °C VCC = 19 V 40 180 240 kΩ φ 90 10 AV 0 0 −10 −90 −20 10 kΩ 1 µF + Gain AV (dB) 20 Phase φ (deg) 30 IN 8 2.4 kΩ (14) 7 10 kΩ (13) − 9 (15) OUT + + 4.2 V (CS) −30 Error Amp1 (Error Amp2) −180 −40 1k 10 k 100 k 1M 10 M Frequency f (Hz) Error Amplifier, Gain and Phase vs. Frequency Ta = +25 °C VCC = 19 V 40 180 240 kΩ 90 10 AV 0 0 −10 −90 −20 Phase φ (deg) φ 20 −30 10 kΩ 1 µF + Gain AV (dB) 30 16 2.4 kΩ 10 kΩ IN − + + 15 OUT Error Amp3 CS 4.2 V −180 − 40 1k 10 k 100 k 1M 10 M Frequency f (Hz) (Continued) 14 MB39A107 (Continued) s Current Detection Amplifier, Gain and Phase vs. Frequency Ta = +25 °C VCC = 19 V 40 180 VCC = 19 V AV 10 0 0 −10 φ −90 −20 Phase φ (deg) 90 20 10 kΩ 1 µF + 10 kΩ IN 5 + 100 mV (12) 4 − (11) Current Amp1 (IOFA1 = 0 V) (Current Amp2) −180 − 40 1k 10 k 100 k 1M 3 (10) OUT 12.6 V −30 10 M Frequency f (Hz) Power Dissipation vs. Ambient Temperature Power dissipation PD (mW) Gain AV (dB) 30 800 740 700 600 500 400 300 200 100 0 −40 −20 0 20 40 60 80 100 Ambient temperature Ta ( °C) 15 MB39A107 ■ FUNCTIONAL DESCRIPTION 1. DC/DC Converter Functions (1) Reference voltage block (REF) The reference voltage circuit generates a temperature-compensated reference voltage (5.0 V Typ) using the voltage supplied from the VCC terminal (pin 1) . The voltage is used as the reference voltage for the IC’s internal circuit. The reference voltage can be used to supply a load current of up to 1 mA to an external device through the VREF terminal (pin 20) . (2) Triangular wave oscillator block (OSC) The triangular wave oscillator incorporates a triangular oscillation frequency setting capacitor connected respectively to the RT terminal (pin 19) to generate triangular oscillation waveforms. The triangular oscillation waveforms are input to the IC’s internal PWM comparator. (3) Error amplifier block (Error Amp1) The error amplifier detects output signal of current detection amplifier (Current Amp2) and outputs PWM control signal by comparison with +INE1 terminal (pin 7), also controls charge current. Charge current controls by this amplifier and by the error amplifier (Error Amp2) allow two constant current values to be set to offer fail-safe control. By connecting a feedback resistor and capacitor between FBI terminal (pin 9) and − INE1 terminal (pin 8), it is possible to create any desired level of loop gain, thereby providing stable phase compensation to the system. Also, it is possible to prevent rush current at power supply start-up by connecting a soft-start capacitor with the CS terminal (pin 18). The use of Error amplifier for soft-start detection makes it possible for a system to operate on a fixed soft-start time that is independent of the output load. The amplifier can serve for constant current control in combination with the current detection amplifier (Current Amp1) . (4) Error amplifier block (Error Amp2) The error amplifier detects output signal of current detection amplifier (Current Amp2) and outputs PWM control signal by comparison with +INE2 terminal (pin 13), also controls charge current. By connecting a feedback resistor and capacitor between FB23 terminal (pin 15) and − INE2 terminal (pin 14), it is possible to create any desired level of loop gain, thereby providing stable phase compensation to the system. Also, it is possible to prevent rush current at power supply start-up by connecting a soft-start capacitor with the CS terminal (pin 18). The use of Error amplifier for soft-start detection makes it possible for a system to operate on a fixed soft-start time that is independent of the output load. 16 MB39A107 (5) Error amplifier block (Error Amp3) The error amplifier (Error Amp3) detects the DC/DC converter output voltage and outputs PWM control signals. An arbitrary output voltage can be set for 1 to 4 cells by connecting external output voltage setting resistors to the error amplifier inverting input pins. By connecting a feedback resistor and capacitor between FB23 terminal (pin 15) and − INE3 terminal (pin 16), it is possible to create any desired level of loop gain, thereby providing stable phase compensation to the system. Also, it is possible to prevent rush current at power supply start-up by connecting a soft-start capacitor with the CS terminal (pin 18). The use of Error amplifier for soft-start detection makes it possible for a system to operate on a fixed soft-start time that is independent of the output load. (6) Current detection amplifier block (Current Amp1) The current detection amplifier (Current Amp1) uses the +INC1 terminal (pin 5) and −INC1 terminal (pin 4) to detect a voltage drop which occurs between both ends of the sense resistor (RS2) due to the flow of the AC adapter current and outputs the signal amplified 25 times to the OUTC1 terminal (pin 3) . It is also possible to set an offset voltage equal to the voltage applied to the IOFA1 terminal (pin 6) . (7) Current detection amplifier block (Current Amp2) The current detection amplifier (Current Amp2) uses the +INC2 terminal (pin 12) and −INC2 terminal (pin 11) to detect a voltage drop which occurs between both ends of the output sense resistor (RS1) due to the flow of the charge current and outputs the signal amplified 25 times to the OUTC2 terminal (pin 10) . (8) PWM comparator block (PWM Comp.) The PWM comparator is a voltage-pulse width modulator that controls the output duty depending on the output voltage of error amplifier (Error Amp1, Error Amp2 and Error Amp3). The PWM comparator compares the triangular wave voltage generated by the triangular wave oscillator with the error amplifier output voltage. Then it turns on the output transistor on the main side and turns off the output transistor on the synchronous rectification side during the interval in which the triangular wave voltage is lower than the error amplifier output voltage. (9) Output block (Drv-1, Drv-2) The output circuit on the main side and on the synchronous rectification side are both in the totem pole configuration, capable of driving an external Nch MOS FET. (10) Charge pump block (Drv-CP) The CB terminal is a power supply terminal of output circuit (Drv-1) for the main side external Nch MOS FET drive. The CB terminal generates “VCC + about 5 V” in the OUT-CP terminal (pin 24) , VB terminal (pin 30) , and CB terminal (pin 29) by connecting the capacitor with SBD. 17 MB39A107 (11) Power supply control block Setting the CTL-1 terminal (pin 22) and CTL-2 terminal (pin 23) “L” level in the standby mode. (The supply current is 10 µA at maximum in the standby mode.) Setting the CTL-1 and CTL-2 terminals “H” level allows the DC/DC converter and current detection amplifier (Current Amp1) to operate independently of each other. CTL function table CTL-1 CTL-2 DC/DC converter block Current Amp1 L L OFF OFF H L ON OFF L H OFF ON H H ON ON (12) Bias voltage block 6 V (Typ) is as a power supply of the output circuit and potential for the charge pump output voltage setting. (13) Battery voltage detection comparator block ( − INEComp.) At least 95% of the battery set voltage is detected to turn off the output transistor of the output block (Drv-2) on the synchronous rectification side. 2. Protection Functions (1) Under voltage lockout protection circuit block (VREF-UVLO) The momentary decrease in internal reference voltage (VREF) may cause malfunctions in the control IC, resulting in breakdown or degradation of the system. To prevent such malfunctions, under voltage lockout protection circuit detects internal reference voltage drop and fixes OUT-1 terminal (pin 28) and OUT-2 terminal (pin 26) to "L" level. The system restores voltage supply when the internal reference voltage reaches the threshold voltage of the under voltage lockout protection circuit. Protection circuit (VREF-UVLO)operation function table At UVLO operating (VRFE voltage is lower than UVLO threshold voltage.) The logic of following terminal is fixed. OUTD OUT-1 OUT-2 OUT-CP Hi-Z L L L CS VB L L (2) Under voltage lockout protection circuit (VB-UVLO) The transient state or a momentary decrease in supply voltage, which occurs when the bias voltage (VB) for output circuit is turned on, may cause malfunction in the control IC, resulting in breakdown or degradation of the system. To prevent such malfunctions, under voltage lockout protection circuit detects a bias voltage drop, and fixes OUT1 terminal (pin 28) and OUT-2 terminal (pin 26) to "L" level. The system restores voltage supply when the power supply voltage or the internal reference voltage reaches the threshold voltage of the under voltage lockout protection circuit. 18 MB39A107 Protection circuit (VB-UVLO)operation function table At UVLO operating (VB voltage is lower than UVLO threshold voltage.) The logic of following terminals is fixed. OUT-1 OUT-2 OUT-CP L L L CS L (3) Under input voltage detection comparator block (UVComp.) Decrease of input voltage is detected and OUT-1 terminal (pin 28) and OUT-2 terminal (pin 26) are fixed to “L” level. In addition, an arbitrary detection voltage value can be set with an external resistor. The system restores voltage supply when the input voltage reaches or exceeds the threshold voltage of the under input voltage detection comparator. Protection circuit (UVComp.)operation function table At under input voltage detection (Input voltage is lower than UVComp. threshold voltage.) The logic of following terminals is fixed. OUT-1 OUT-2 OUT-CP L L L CS L 3. Soft-start function Soft-start block (SOFT) Connecting a capacitor to the CS terminal (pin 18) prevents rush currents from flowing upon activation of the power supply. Using the error amplifier to detect a soft-start allows to soft-start at constant setting time intervals independent of the output load of the DC/DC converter. 19 MB39A107 ■ SETTING THE CHARGING VOLTAGE The charging voltage (DC/DC output voltage) can be set by connecting an external output voltage setting resistors (R1, R2) to the −INE3 terminal (pin 16) . Select a resistance value at which the ON resistance (35 Ω at 1 mA) of the built-in FET connected to the OUTD terminal (pin 17) can be ignored. Battery charging voltage : Vo R1 + R2 × − INE3 (V) Vo (V) = R2 VO B <Error Amp3> R1 −INE3 16 − + + R2 17 4.2 V OUTD 18 CS ■ SETTING THE CHARGING CURRENT The charge current value (output limit current) can be set depending on the voltage value at the +INE2 terminal (pin 13) . If a current exceeding the setting value attempts to flow, the charging voltage drops according to the setting current value. Battery charge current setting voltage : + INE2 + INE2 (V) = 25 × Ichg (A) × RS (Ω) ■ SETTING THE TRIANGULAR WAVE OSCILLATION FREQUENCY The triangular wave oscillation frequency can be set by the timing resistor (RT) connected to the RT terminal (pin 19) . Triangular oscillation frequency : fOSC 23500 fOSC (kHz) =: RT (kΩ) 20 MB39A107 ■ SETTING THE SOFT-START TIME (1) Setting constant voltage mode soft-start For preventing rush current upon activation of IC, the IC allows soft-start using the capacitor (CS) connected to the CS terminal (pin 18) . When the CTL-1 terminal (pin 22) is placed under “H” level and IC is activated (threshold voltage of VCC ≥ UVLO) , and Q2 is turned off and the external soft-start capacitor (CS) connected to the CS terminal is charged at 10 µA. The Error Amp3 output (FB23 terminal (pin 15) ) is determined by comparison between the lower voltage of the two non-inverted input terminal voltages (4.2 V and − CS terminal voltage) , and the inverted input terminal voltage (at the −INE3 terminal (pin 16) ) . FB23 during soft-start intervals (CS terminal voltage < 4.2 V) is therefore determined through comparison between the −INE3 terminal voltage and CS terminal voltage and the DC/DC converter output voltage is proportional to the CS terminal voltage rising as the external soft-start capacitor connected to the CS terminal is charged. The soft-start time is obtained by the following formula. Soft start time : ts (time to output voltage 100%) ts (s) =: 0.42 × Cs (µF) CS terminal voltage Comparison voltage with Error Amp block − INE3 voltage =: 4.9 V =: 4.2 V =: 0 V t Soft-start time : ts • Soft-start circuit VREF 10 µA 10 µA −INE3 <Error Amp3> − 16 + + CS 18 4.2 V CS Q2 UVLO 21 MB39A107 (2) Setting constant current mode soft-start For preventing rush current upon activation of IC, the IC allows soft-start using the capacitor (CS) connected to the CS terminal (pin 18) . When the CTL-1 terminal (pin 22) is placed under “H” level and IC is activated (threshold voltage of VCC ≥ UVLO) , and Q2 is turned off and the external soft-start capacitor (CS) connected to the CS terminal is charged at 10 µA. The error Amp2 output (FB23 terminal (pin 15) ) is determined by comparison between the lower voltage of the two non-inverted input terminal voltages (at the +INE2 terminal (pin 13) and CS terminal) , and the inverted input terminal voltage (at the −INE2 terminal (pin 14) ) . FB23 during soft-start intervals (CS terminal voltage < +INE2) is therefore determined through comparison between the −INE2 terminal voltage and CS terminal voltage and the DC/DC converter output current is proportional to the CS terminal voltage rising as the external soft-start capacitor connected to the CS terminal is charged. The soft-start time is obtained by the following formula. Soft start time : ts (time to output voltage 100%) + INE2 ts (s) =: × Cs (µF) 10 µA CS terminal voltage Comparison voltage with =: 4.9 V + INE2 Error Amp block − INE2 voltage =: 0 V t Soft-start time : ts • Soft-start circuit VREF 10 µA 10 µA <Error Amp2> −INE2 − 14 + + CS 18 +INE2 CS 22 13 Q2 UVLO MB39A107 ■ PROCESSING WITHOUT USING OF THE SOFT-START FUNCTION When soft-start function is not used, leave the CS terminal (pin 18) open. • When no soft-start function is specified “Open” CS 18 23 MB39A107 ■ I/O EQUIVALENT CIRCUIT 〈〈 Reference voltage block 〉〉 〈〈 Control block 〉〉 VCC 1 CTL-2 23 1.23 V ESD protection element + − CTL-1 22 20 VREF 37.65 kΩ 12.3 kΩ GND 21 〈〈 Soft-start block 〉〉 ESD protection element 33.1 kΩ 33.1 kΩ 51 kΩ 51 kΩ GND 〈〈 Triangular wave oscillator block 〉〉 〈〈 Error amplifier block (Error Amp1) 〉〉 VREF (5.0 V) VCC VREF (5.0 V) VREF (5.0 V) 18 CS 1.22 V + − −INE1 8 CS 19 RT GND 9 FB1 4.2 V GND GND 7 +INE1 〈〈 Error amplifier block (Error Amp2) 〉〉 〈〈 Error amplifier block (Error Amp3) 〉〉 VCC VCC VREF (5.0 V) −INE2 14 −INE3 16 4.2 V 15 FB23 GND CS FB23 4.2V GND 13 +INE2 〈〈 Current detection amplfier block (Current Amp1) 〉〉 〈〈 Current detection amplfier block (Current Amp1 offset adjustment block) 〉〉 VCC VCC +INC1 5 −IN 3 OUTC1 6 IOFA1 GND GND 4 −INC1 (Continued) 24 MB39A107 (Continued) 〈〈 Current detection amplfier block (Current Amp2) 〉〉 〈〈 PWM comparator block 〉〉 VCC VCC +INC2 12 FB1 10 OUTC2 CT FB23 GND GND 11 −INC2 〈〈 Output block (synchronous rectification-side) 〉〉 〈〈 Output block (Main side) 〉〉 CB 29 〈〈 Charge pump block 〉〉 VB 30 VCC 28 OUT-1 24 OUT-CP 26 OUT-2 PGND VS 27 PGND 25 GND 〈〈 Under input voltage detection comparator block 〉〉 〈〈 Battery voltage detection comparator block 〉〉 VCC VCC VREF (5.0 V) VREF (5.0 V) 2 +INUV GND −INE3 GND 〈〈 Prevent inefficient current block 〉〉 〈〈 Bias voltage block 〉〉 VCC 30 VB 17 OUTD 1.23 V GND GND 25 26 7 V to 25 V Chg_ctr R5 6.2 kΩ C7 6800 pF R11 51 kΩ 15 mΩ R7 R17 100 kΩ FB1 +INE1 −INE1 IOFA1 −INC1 +INC1 7 8 6 4 5 13 15 R28 100 kΩ R27 200 kΩ −INE3 16 R35 1 kΩ FB23 +INE2 C10 0.022 µF CS 18 C18 C9 10 2200 OUTD pF pF 17 R21 R22 R18 R26 18 1.3 47 100 kΩ kΩ kΩ kΩ R25 51 kΩ C19 10 pF 9 R16 10 kΩ −INE2 14 C8 6800 pF OUTC2 R24 10 R23 10 kΩ 100 kΩ 12 A +INC2 B 11 −INC2 R14 47 kΩ 12 kΩ SW3 SW4 10 kΩ R12 51 kΩ R19 R20 33 200 kΩ kΩ R6 100 kΩ D1 OUTC1 10 µA <SOFT> VREF VREF VREF 4.2 V − + + CT 45 pF <ErrorAmp3> − + + <ErrorAmp2> 4.2 V <ErrorAmp1> − + + + Offset adjustment <CurrentAmp2> + ×25 − + ×25 − <CurrentAmp1> 3 To Microprocessor 3.92 V/4.00 V + − <−INEComp.> RT R30 47 kΩ 19 <OSC> 4.2 V bias VREF 5.0 V C11 0.1 µF VCC Drv -CP Drv -2 Drv -1 (6.0 V) C6 0.1 µF 20 GND 21 <CTL> VCC DC/DC ON/OFF CurrentAmp1 ON/OFF VREF UVLO VB UVLO H : UVLO, UV release <REF> VREF −2.5 V −1.5 V 1 VB Reg. UVLO <UVComp.> 4.05 V/4.20 V − + +INUV <PWMComp.> + + − 2 Dead Time Modulation R4 R5 22 23 25 24 26 CTL-1 CTL-2 PGND OUT-CP C12 0.47 µF OUT-2 D3 C14 D4 0.47 µF 0.47 OUT-1 µF 28 VS 27 CB 29 C13 VB 30 C15 1 µF C1 2.2 µF C2 2.2 µF Q1 Q2 D5 2.2 µF C3 2.2 µF C4 Output voltage (Battery voltage) is adjustable. D2 5.2 µH L1 Ichg B 2.2 µF Battery R8 33 mΩ C5 A VO MB39A107 ■ APPLICATION EXAMPLE 1 MB39A107 ■ PARTS LIST 1 COMPONENT ITEM SPECIFICATION VENDOR PARTS No. Q1, Q2, Nch FET VDS = 30 V, ID = 8.0 A NEC µPA2752 D1 D2, D5 D3, D4 Diode Diode Diode L1 Inductor 5.2 µH 5.5 A, 22 mΩ SUMIDA CDRH104R-5R2 C1, C2 C3 to C5 C6, C11 C7, C8 C9 C10 C12 C13, C14 C15 C18, C19 Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser 2.2 µF 2.2 µF 0.1 µF 6800 pF 2200 pF 0.022 µF 0.47 µF 0.47 µF 1 µF 10 pF 25 V 25 V 50 V 50 V 50 V 50 V 25 V 50 V 25 V 50 V TDK TDK TDK TDK TDK TDK TDK TDK TDK TDK C3216JB1E225K C3225JB1H225K C1608JB1H104K C1608JB1H682K C1608JB1H222K C1608JB1H223K C3216JB1E474K C3216JB1H474K C3216JB1E105K C1608JB1H100K R4 R5 R6 R7 R8 R11, R12 R14 R15 R16, R24 R17, R23, R26 R18, R30 R19 R20 R21 R22 R25 R27 R28 R35 Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor 33 kΩ 200 kΩ 100 kΩ 15 mΩ 33 mΩ 51 kΩ 47 kΩ 12 kΩ 10 kΩ 100 kΩ 47 kΩ 10 kΩ 6.2 kΩ 18 kΩ 1.3 kΩ 51 kΩ 200 kΩ 100 kΩ 1 kΩ 0.5% 0.5% 0.5% 1% 1% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% ssm ssm ssm KOA KOA ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm RR0816P-333-D RR0816P-204-D RR0816P-104-D SL1TTE15LOF SL1TTE33LOF RR0816P-513-D RR0816P-473-D RR0816P-123-D RR0816P-103-D RR0816P-104-D RR0816P-473-D RR0816P-103-D RR0816P-622-D RR0816P-183-D RR0816P-132-D RR0816P-513-D RR0816P-204-D RR0816P-104-D RR0816P-102-D VF = 0.4 V (Max) , At IF = 2.5 A SHINDENGEN VF = 0.42 V (Max) , At IF = 3 A ROHM VF = 0.45 V (Max) , At IF = 100 mA ORIGIN DEP5PC3 RB053L-30 FQ4JP3 Note : NEC : NEC corporation SHINDENGEN : Shindengen Electric Manufacturing. Co., Ltd. ROHM ORIGIN SUMIDA TDK ssm KOA : ROHM CO., LTD : Origin Electric Co., Ltd. : SUMIDA Corporation : TDK Corporation : SUSUMU CO., LTD : KOA Corporation 27 28 7 V to 25 V R2 6.2 kΩ 7 8 6 4 5 R25 51 kΩ C19 10 pF 13 15 R28 100 kΩ R27 200 kΩ −INE3 16 R35 1 kΩ FB23 +INE2 C10 0.022 µF CS 18 C18 C9 10 2200 OUTD pF pF 17 R21 R22 R18 R26 18 1.3 47 100 kΩ kΩ kΩ kΩ SW3 SW4 10 kΩ R19 R20 C7 6800 pF +INE1 −INE1 IOFA1 −INC1 +INC1 FB1 9 R16 10 kΩ −INE2 14 C8 6800 pF OUTC2 R24 10 R23 10 kΩ 100 kΩ 12 A +INC2 B 11 −INC2 R33 30 kΩ D1 56 180 kΩ kΩ R3 47 kΩ R1 20 kΩ R34 33 200 kΩ kΩ R6 100 kΩ R5 OUTC1 10 µA <SOFT> VREF VREF VREF 4.2 V − + + CT 45 pF <ErrorAmp3> − + + <ErrorAmp2> 4.2 V <ErrorAmp1> − + + + Offset adjustment <CurrentAmp2> + ×25 − + ×25 − <CurrentAmp1> 3 3.92 V/4.00 V + − <−INEComp.> RT R30 47 kΩ 19 <OSC> 4.2 V bias VREF 5.0 V C11 0.1 µF VCC Drv -CP Drv -2 Drv -1 (6.0 V) C6 0.1 µF 20 GND 21 <CTL> VCC DC/DC ON/OFF CurrentAmp1 ON/OFF VREF UVLO VB UVLO H : UVLO, UV release <REF> VREF −2.5 V −1.5 V 1 VB Reg. UVLO <UVComp.> 4.05 V/4.20 V − + +INUV <PWMComp.> + + − 2 Dead Time Modulation R4 22 23 25 24 26 CTL-1 CTL-2 PGND OUT-CP C12 0.47 µF OUT-2 D3 C14 D4 0.47 µF 0.47 OUT-1 µF 28 VS 27 CB 29 C13 VB 30 C15 1 µF C1 2.2 µF C2 2.2 µF Q1 Q2 D5 2.2 µF C3 2.2 µF C4 Output voltage (Battery voltage) is adjustable. D2 5.2µH L1 Ichg B 2.2 µF Battery R8 33 mΩ C5 A VO MB39A107 ■ APPLICATION EXAMPLE 2 MB39A107 ■ PARTS LIST 2 COMPONENT ITEM SPECIFICATION VENDOR PARTS No. Q1, Q2 Nch FET VDS = 30 V, ID = 8.0 A NEC µPA2752 D1 D2, D5 D3, D4 Diode Diode Diode L1 Inductor 5.2 µH 5.5 A, 22 mΩ SUMIDA CDRH104R-5R2 C1, C2 C3 to C5 C6, C11 C7, C8 C9 C10 C12 C13, C14 C15 C18, C19 Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser 2.2 µF 2.2 µF 0.1 µF 6800 pF 2200 pF 0.022 µF 0.47 µF 0.47 µF 1 µF 10 pF 25 V 25 V 50 V 50 V 50 V 50 V 25 V 50 V 25 V 50 V TDK TDK TDK TDK TDK TDK TDK TDK TDK TDK C3216JB1E225K C3225JB1H225K C1608JB1H104K C1608JB1H682K C1608JB1H222K C1608JB1H223K C3216JB1E474K C3216JB1H474K C3216JB1E105K C1608JB1H100K R1 R2 R3 R4 R5 R6 R8 R16, R24 R18, R30 R19 R20 R21 R22 R23, R26 R25 R27 R28 R33 R34 R35 Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor 56 kΩ 180 kΩ 47 kΩ 33 kΩ 200 kΩ 100 kΩ 33 mΩ 10 kΩ 47 kΩ 10 kΩ 6.2 kΩ 18 kΩ 1.3 kΩ 100 kΩ 51 kΩ 200 kΩ 100 kΩ 30 kΩ 20 kΩ 1 kΩ 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 1% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% ssm ssm ssm ssm ssm ssm KOA ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm RR0816P-563-D RR0816P-184-D RR0816P-473-D RR0816P-333-D RR0816P-204-D RR0816P-104-D SL1TTE33LOF RR0816P-103-D RR0816P-473-D RR0816P-103-D RR0816P-622-D RR0816P-183-D RR0816P-132-D RR0816P-104-D RR0816P-513-D RR0816P-204-D RR0816P-104-D RR0816P-303-D RR0816P-203-D RR0816P-102-D VF = 0.4 V (Max) , At IF = 2.5 A SHINDENGEN VF = 0.42 V (Max) , At IF = 3 A ROHM VF = 0.45 V (Max) , At IF = 100 mA ORIGIN DEP5PC3 RB053L-30 FQ4JP3 Note : NEC : NEC corporation SHINDENGEN : Shindengen Electric Manufacturing. Co., Ltd. ROHM ORIGIN SUMIDA TDK ssm KOA : ROHM CO., LTD : Origin Electric Co., Ltd. : SUMIDA Corporation : TDK Corporation : SUSUMU CO., LTD : KOA Corporation 29 MB39A107 ■ REFERENCE DATA Conversion efficiency η (%) Conversion Efficiency vs. Charge Current (constant voltage mode) 100 95 90 85 Ta = + 25 °C VIN = 19 V Charge voltage = 16.8 V setting SW1 = ON SW2 = ON SW3 = OFF SW4 = OFF TOTAL efficiency η (%) = (Vo × Io) / (VIN × IIN) × 100 80 75 70 65 60 55 50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Charge current Io (A) Conversion efficiency η (%) Conversion Efficiency vs. Charge Voltage (constant current mode) 100 95 90 85 Ta = + 25 °C VIN = 19 V Charge current = 4.5 A setting SW1 = ON SW2 = ON SW3 = OFF SW4 = OFF TOTAL efficiency η (%) = (Vo × Io) / (VIN × IIN) × 100 80 75 70 65 60 55 50 0 2 4 6 8 10 12 14 16 Charge voltage Vo (V) Charge Voltage vs. Charge Current (16.8 V setting) Charge voltage Vo (V) 18 16 14 SW3 = OFF SW4 = ON 12 SW3 = OFF SW4 = OFF 10 8 6 4 2 0 0.0 SW3 = ON SW4 = OFF Ta = + 25 °C VIN = 19 V Charge voltage = 16.8 V setting SW1 = ON SW2 = ON 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Charge current Io (A) (Continued) 30 MB39A107 (Continued) • Switching Waveform (constant voltage mode) Vs(V) 3 Ta = +25 ˚C VIN = 19 V CTL1 = 5 V CTL2 = 5 V SW3 = OFF SW4 = OFF Vo = 16.8 V Io = 2 A 2 Vs 1 0 OUT1 OUT1(V) 20 OUT2(V) 10 10 0 5 OUT2 0 0.2 0.4 0 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 (ms) • Switching Waveform (constant current mode) Vs(V) 3 Ta = +25 ˚C VIN = 19 V CTL1 = 5 V CTL2 = 5 V SW3 = OFF SW4 = OFF Vo = 10 V Io = 4.5 A 2 Vs 1 0 OUT1 OUT1(V) 20 OUT2(V) 10 10 0 5 OUT2 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 (ms) 31 MB39A107 • CTL function • CTL1, CTL2 = L→H constant voltage mode VO (V) VIN = 19 V Setting VO = 10 Ω 15 VO 10 5 OUTC1 (V) 0 5 OUTC1 0 CTL-1 (V) CTL-1 5 CTL-2 (V) CTL2 5 0 3 0 0 2 4 6 8 10 12 14 16 18 20 (ms) • CTL1, CTL2 = H→L constant voltage mode VO (V) 15 VIN = 19 V Setting VO = 10 Ω VO 10 5 OUTC1 (V) 0 5 OUTC1 0 CTL-1 (V) CTL-1 5 CTL-2 (V) CTL2 0 5 0 0 2 4 6 8 10 12 14 16 18 20 (ms) (Continued) 32 MB39A107 (Continued) • CTL1, CTL2 = L→H constant current mode VO (V) VIN = 19 V Setting VO = 3 Ω 15 10 VO 5 OUTC1 (V) 0 5 OUTC1 0 CTL-1 (V) CTL-1 5 CTL-2 (V) CTL2 0 5 0 0 2 4 6 8 10 12 14 16 18 20 (ms) • CTL1, CTL2 = H→L constant current mode VO (V) VIN = 19 V Setting VO = 3 Ω 15 10 VO 5 OUTC1 (V) 0 5 OUTC1 0 CTL-1 (V) CTL-1 5 CTL-2 (V) CTL2 0 5 0 0 2 4 6 8 10 12 14 16 18 20 (ms) 33 MB39A107 ■ SELECTION OF COMPONENTS • Nch MOS FET The Nch MOS FET for switching use should be rated for at least + 20% more than the maximum input voltage. To minimize continuity loss, use a FET with low RDS (ON) between the drain and source. For high input voltage and high frequency operation, on/off-cycle switching loss will be higher so that power dissipation must be considered. In this application, the µPA2752 (NEC products) is used. Continuity loss, on/off switching loss and total loss are determined by the following formulas. The selection must ensure that peak drain current does not exceed rated values. Continuity loss : Pc PC = ID2 × RDS (ON) × Duty On-cycle switching loss : PS (ON) PS (ON) = VD (Max) × ID × tf × fOSC 6 Off-cycle switching loss : PS (OFF) PS (OFF) = VD (Max) × ID (Max) × tf × fOSC 6 Total loss : PT PT = PC + PS (ON) + PS (OFF) Example) Using the µPA2752 Setting 16.8V Main side Input voltage VIN (Max) = 25 V, output voltage VO = 16.8 V, drain current ID = 4.5 A, oscillation frequency fOSC = 500 kHz, L = 5.2 µH, drain-source on resistance RDS (ON) =: 20 mΩ, tr = 6.2 ns, tf = 5.8 ns Drain current (Max) : ID (Max) ID (Max) = Io + = 4.5 + VIN (Max) − Vo 2L ton 25 − 16.8 2 × 5.2 × 10 −6 × 1 500 × 103 × 0.672 =: 5.56 A Drain current (Min) : ID (Min) ID (Min) = Io − = 4.5 − =: 3.44 A 34 VIN (Max) − Vo 2L ton 25 − 16.8 2 × 5.2 × 10 − 6 × 1 500 × 103 × 0.672 MB39A107 PC = ID2 × RDS (ON) × Duty = 4.52 × 0.02 × 0.672 =: 0.272 W PS (ON) = = VD (Max) × ID × tr × fOSC 6 25 × 4.5 × 6.2 × 10 − 9 × 500 × 103 6 =: 0.058 W PS (OFF) = = VD (Max) × ID (Max) × tf × fOSC 6 25 × 5.56 × 5.8 × 10 − 9 × 500 × 103 6 =: 0.067 W = PC + PS (ON) + PS (OFF) PT =: 0.272 + 0.058 + 0.067 =: 0.397 W The above power dissipation figures for the µPA2752 are satisfied with ample margin at 2 W (Ta = + 25 °C). Synchronous rectification side Input voltage VIN (Max) = 25 V, output voltage Vo = 16.8 V, drain current ID = 4.5 A, oscillation frequency fOSC = 500 kHz, L = 5.2 µH, drain-source on resistance RDS (ON) =: 20 mΩ, tr = 6.2 ns, tf = 5.8 ns Drain current (Max) : ID (Max) ID (Max) = Io + = 4.5 + Vo 2L toff 16.8 2 × 5.2 × 10 − 6 × 1 500 × 103 × (1 − 0.672) =: 5.56 A Drain current (Min) : ID (Min) ID (Min) = Io − = 4.5 − =: Vo 2L toff 16.8 2 × 5.2 × 10 −6 × 1 500 × 103 × (1 − 0.672) 3.44 A 35 MB39A107 PC = ID2 × RDS (ON) × Duty (OFF) = 4.52 × 0.02 × (1 − 0.672) =: 0.133 W PS (ON) = = VF × ID × tr × fOSC 6 0.45 × 4.5 × 6.2 × 10 − 9 × 500 × 103 6 =: 0.001 W PS (OFF) = = VF × ID (Max) × tf × fOSC 6 0.45 × 5.56 × 5.8 × 10 − 9 × 500 × 103 6 =: 0.001 W PT = PC + PS (ON) + PS (OFF) =: 0.133 + 0.001 + 0.001 =: 0.135 W The above power dissipation figures for the µPA2752 are satisfied with ample margin at 2 W (Ta = + 25 °C). Setting 12.6V Main side Input voltage VIN (Max) = 20 V, output voltage Vo = 12.6 V, drain current ID = 4.5 A, oscillation frequency fOSC = 500 kHz, L = 5.2 µH, drain-source on resistance RDS (ON) =: 20 mΩ, tr = 6.2 ns, tf = 5.8 ns Drain current (Max) : ID (Max) ID (Max) = Io + = 4.5 + VIN (Max) − Vo ton 2L 20 − 12.6 2 × 5.2 × 10 − 6 × 1 500 × 103 × 0.63 =: 5.40 A Drain current (Min) : ID (Min) ID (Min) = Io − = 4.5 − =: 3.60 A 36 VIN (Max) − Vo ton 2L 20 − 12.6 2 × 5.2 × 10 −6 × 1 500 × 103 × 0.63 MB39A107 PC = ID2 × RDS (ON) × Duty = 4.52 × 0.02 × 0.63 =: 0.255 W PS (ON) = = VD (Max) × ID × tr × fOSC 6 20 × 4.5 × 6.2 × 10 − 9 × 500 × 103 6 =: 0.047 W PS (OFF) = = VD (Max) × ID (Max) × tf × fOSC 6 20 × 5.40 × 5.8 × 10 − 9 × 500 × 103 6 =: 0.052 W PT = PC + PS (ON) + PS (OFF) =: 0.255 + 0.047 + 0.052 =: 0.354 W The above power dissipation figures for the µPA2752 are satisfied with ample margin at 2 W (Ta = + 25 °C). Synchronous rectification side Input voltage VIN (Max) = 20 V, output voltage Vo = 12.6 V, drain current ID = 4.5 A, oscillation frequency fOSC = 500 kHz, L = 5.2 µH, drain-source on resistance RDS (ON) =: 20 mΩ, tr = 6.2 ns, tf = 5.8 ns Drain current (Max) : ID (Max) ID (Max) = Io + = 4.5 + Vo 2L toff 12.6 2 × 5.2 × 10 − 6 × 1 500 × 103 × (1 − 0.63) × (1 − 0.63) =: 5.40 A Drain current (Min) : ID (Min) ID (Min) = Io − = 4.5 − Vo 2L toff 12.6 2 × 5.2 × 10 −6 × 1 500 × 103 =: 3.60 A 37 MB39A107 PC = ID2 × RDS (ON) × Duty (OFF) = 4.52 × 0.02 × (1 − 0.63) =: 0.150 W PS (ON) = = VF × ID × tr × fOSC 6 0.45 × 4.5 × 6.2 × 10 − 9 × 500 × 103 6 =: 0.001 W PS (OFF) = = VF × ID (Max) × tf × fOSC 6 0.45 × 5.40 × 5.8 × 10 − 9 × 500 × 103 6 =: 0.001 W = PC + PS (ON) + PS (OFF) PT =: 0.15 + 0.001 + 0.001 =: 0.152 W The above power dissipation figures for the µPA2752 are satisfied with ample margin at 2 W (Ta = + 25 °C). • Inductor In selecting inductors, it is of course essential not to apply more current than the rated capacity of the inductor, but also to note that the lower limit for ripple current is a critical point that if reached will cause discontinuous operation and a considerable drop in efficiency. This can be prevented by choosing a higher inductance value, which will enable continuous operation under light loads. Note that if the inductance value is too high, however, direct current resistance (DCR) is increased and this will also reduce efficiency. The inductance must be set at the point where efficiency is greatest. Note also that the DC superimposition characteristic become worse as the load current value approaches the rated current value of the inductor, so that the inductance value is reduced and ripple current increases, causing loss of efficiency. The selection of rated current value and inductance value will vary depending on where the point of peak efficiency lies with respect to load current. Inductance values are determined by the following formulas. The L value for all load current conditions is set so that the peak to peak value of the ripple current is 1/2 the load current or less. Inductance value : L L≥ 38 2 (VIN − VO) IO ton MB39A107 16.8 V output Example : 2 (VIN (Max) − VO) L≥ ton IO ≥ 2 × (25 − 16.8) 1 × 4.5 × 500 × 103 0.672 ≥ 4.9 µH 12.6 V output Example : 2 (VIN (Max) − VO) L≥ ton Io ≥ 2 × (20 − 12.6) 4.5 × 1 × 0.63 500 × 103 ≥ 4.1 µH Inductance values derived from the above formulas are values that provide sufficient margin for continuous operation at maximum load current, but at which continuous operation is not possible at light loads. It is therefore necessary to determine the load level at which continuous operation becomes possible. In this application, the SUMIDA CDRH104R-5R2 is used. The following formula is available to obtain the load current as a continuous current condition when 5.2 µH is used. Load current value under continuous operating conditions : Io IO ≥ VO 2L toff Example : Using the CDRH104R-5R2 5.2 µH (tolerance ± 20% ), rated current = 5.5 A 16.8 V output VO IO ≥ toff 2L ≥ 16.8 2 × 5.2 × 10 − 6 × 1 500 × 103 × (1 − 0.672) ≥ 1.06 A 39 MB39A107 12.6 V output VO IO ≥ toff 2L ≥ 12.6 2 × 5.2 × 10 −6 × 1 500 × 103 × (1 − 0.63) ≥ 0.897A To determine whether the current through the inductor is within rated values, it is necessary to determine the peak value of the ripple current as well as the peak-to-peak values of the ripple current that affect the output ripple voltage. The peak value and peak-to-peak value of the ripple current can be determined by the following formulas. Peak Value : IL IL ≥ Io + VIN − VO 2L ton Peak-Peak Value : ∆IL ∆IL = VIN − VO L ton Example : Using the CDRH104R-5R2 5.2 µH (tolerance ± 20% ), rated current = 5.5 A Peak Value 16.8 V output IL ≥ Io + ≥ 4.5 + VIN (Max) − VO 2L ton 25 − 16.8 2 × 5.2 × 10 − 6 × 1 500 × 103 × 0.672 ≥ 5.56 A 12.6 V output IL ≥ IO + ≥ 4.5 + ≥ 5.40 A 40 VIN (Max) − VO 2L ton 20 − 12.6 2 × 5.2 × 10 − 6 × 1 500 × 103 × 0.63 MB39A107 Peak-Peak Value 16.8 V output VIN (Max) − Vo ∆IL = L = 25 − 16.8 5.2 × 10 −6 ton × 1 500 × 103 × 0.672 =: 2.12 A 12.6 V output VIN (Max) − Vo ∆IL = L = 20 − 12.6 5.2 × 10 −6 ton × 1 500 × 103 × 0.63 =: 1.79 A • Diode for charge pump Using a low-leak diode increases efficiency a little; but using a signal diode is satisfactory. It is recommended to use a low-VF one. Also, use a capacitor for the charge pump, which is sufficiently larger value than the gate capacitor for the main-side FET. It is recommended to use a component between 0.1 µF to 1.0 µF. 41 MB39A107 ■ NOTES ON USE • Take account of common impedance when designing the earth line on a printed wiring board. • Take measures against static electricity. • For semiconductors, use antistatic or conductive containers. • When storing or carrying a printed circuit board after chip mounting, put it in a conductive bag or container. • The work table, tools, and measuring instruments must be grounded. • The worker must put on a grounding device containing 250 kΩ to 1 MΩ resistors in series. • Do not apply a negative voltage. • Applying a negative voltage of −0.3 V or less to an LSI may generate a parasitic transistor, resulting in malfunction. 42 MB39A107 ■ ORDERING INFORMATION Part number MB39A107PFT Package Remarks 30-pin plastic TSSOP (FPT-30P-M04) 43 MB39A107 ■ PACKAGE DIMENSION 30-pin plastic TSSOP (FPT-30P-M04) 7.80±0.10(.307±.004) "A" Details of "A" part 0~8° 1.10(.043) MAX 0.60±0.10 (.024±.004) +0.20 4.40 –0.10 6.40±0.10 +.008 .173 –.004 (.252±.004) INDEX 0.25(.010) 0.10±0.05 (.004±.002) 0.50(.020) 0.20±0.03 (.008±.001) 0.10(.004) 7.00(.276) C 0.3865(.0152) 0.127±0.03 (.005±.001) 0.90±0.05 (.035±.002) 0.3865(.0152) 2001 FUJITSU LIMITED F30007SC-1-1 Dimensions in mm (inches) Note : The values in parentheses are reference values. 44 MB39A107 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. 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