FUJITSU MB39C308BGF

FUJITSU MICROELECTRONICS
DATA SHEET
DS04-27261-6E
ASSP for Power Management Applications of
Ultra Mobile PC
6ch DC/DC Converter IC
for LPIA Platform VR
MB39C308
■ DESCRIPTION
The MB39C308 is a 6ch DC/DC buck converter LSI, which integrates all of necessary power supplies for UltraMobile PC powered by 2-cell Li-ion battery. And the MB39C308 uses current mode topology with N-channel
synchronous rectification to realize high conversion efficiency.
The MB39C308 is the Power Management IC supporting the LPIA(Low Power Intel Architecture) which Intel
Corporation proposes as the low power consumption platform for UMPC.
The CH1 and CH2 are flexible to adopt the output current capability by selection of external FETs and easy to
optimize efficiency. The CH3, CH4, CH5 and CH6 integrate the switching FETs capable of high current for downsizing the power supply solution.
The MB39C308 uses Fujitsu’s LDMOS process technology and supplies all power without dispersing power from
a lithium-ion battery.
■ FEATURES
•
•
•
•
•
•
Input voltage range
: 5.5 V to 12.6 V
Topology
: Current Mode
Integrated FET Driver for external MOSFETs : CH1, CH2
Integrated Switching MOSFETs
: CH3, CH4, CH5, CH6
Fixed Preset Output Voltage
: CH1, CH2, CH5
Selectable Preset Output Voltage
: CH3, CH4, CH6
Output
voltage
Output
current
Remarks
CH1
5V
2 A*
⎯
CH2
3.3 V
4.5 A*
⎯
CH3
1.8 V/1.5 V
Max : 2.7 A
CH4
0.9 V/0.75 V
Max : 1.5 A
CH5
1.5 V
Max : 2.5 A
CH6
1.1 V/1.05 V
Max : 3.5 A
Channel
DDR2/DDR3 are selectable.
⎯
Two values are selectable.
* : It is the reference value at the typical EVB.
(Continued)
Copyright©2007-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.9
MB39C308
(Continued)
• PWM switching frequency
: 0.7 MHz
(CH4 : 0.7 MHz/0.35 MHz)
• Various protection
- Over current protection (OCP)
- Input over voltage protection (IVP)
- Output short circuit protection (SCP) - Under voltage lock out protection (UVLO)
- Output over voltage protection (OVP) - Over temperature protection (OTP)
• POWERGOOD function
• Soft start function independent from output loads.
• Soft stop function independent from output loads.
• High conversion efficiency in wide range of load current.
• Packaged in a compact package
: PFBGA-208 (9.00 mm × 9.00 mm × 1.30 mm)
■ APPLICATIONS
• UMPC (Ultra Mobile PC)
• MID (Mobile Internet Device)
• Mobile equipment
2
etc.
DS04-27261-6E
MB39C308
■ PIN ASSIGNMENT
(BOTTOM VIEW)
CH3
CH2
CH1
16
NC
LX3C
LX3A
PVDD3G PVDD3D PVDD3A PVDD2
CB2
LX2
PGND2 PGND1
LX1
CB1
PVDD1
SS1
NC
15
LX3G
LX3D
LX3B
PVDD3H PVDD3E PVDD3B OUT2H OUT2L
FB2
FB1
LX3H
LX3E
CB3
PVDD3I PVDD3F PVDD3C
PG3
PG4
LX3I
LX3F
FB3
OUT1L OUT1H
CTL1
CTL2
SS2
AVDD
ALLPG
CTL34
AGND
VREF
CTL5
CTL6
PGND7
FSEL4
DIN
VB
14
PG1
PG2
PG5
PG6
Common
13
PGND3GPGND3D PGND3A
12
11
PGND3H PGND3E PGND3B
VSEL34 DVSEL6 PVDD7
10
PGND3I PGND3F PGND3C
FB6
PVDD6E PVDD6A
9
PGND4F PGND4C PGND4A
PVDD6I PVDD6F PVDD6B
PGND4GPGND4D PGND4B
PVDD6J PVDD6G PVDD6C
8
7
LX4F
LX4C
FB4
CB6
CH6
CH4
PGND4H PGND4E
LX4A
PVDD6H PVDD6D
6
LX6G
LX6D
LX6A
5
LX4G
LX4D
LX4B
LX6H
LX6E
LX6B
LX6I
LX6F
LX6C
Thermal PIn
LX4H
LX4E
4
CH5
CB4
3
PVDD4F PVDD4C PVDD4A PVDD5E PVDD5B
FB5
LX5G
LX5D
LX5A PGND5GPGND5D PGND5A PGND6H LX6J
PGND6C PGND6A
PVDD4G PVDD4D PVDD4B PVDD5F PVDD5C
CB5
LX5H
LX5E
LX5B
PGND5H PGND5E PGND5B PGND6I PGND6F PGND6D PGND6B
LX5I
LX5F
LX5C
PGND5I PGND5F PGND5C PGND6J PGND6G PGND6E
K
J
H
2
1
NC
T
PVDD4E PVDD5H PVDD5G PVDD5D PVDD5A
R
P
N
M
L
G
F
E
D
C
B
NC
A
(BGA-208P-M02)(156-pin + Thermal 52-pin)
DS04-27261-6E
3
MB39C308
■ PIN DESCRIPTIONS
Block
CH1
CH2
CH3
CH4
Pin Name
I/O
Description
FB1
I
PVDD1
⎯
Power supply pin of the CH1 output block.
CB1
O
Internal power supply pin of the CH1 gate driver block.
LX1
⎯
CH1 inductor connection pin.
OUT1H
O
CH1 High-side N-ch FET drive output pin.
OUT1L
O
CH1 Low-side N-ch FET drive output pin.
PGND1
⎯
Ground pin of the CH1 output block.
FB2
I
PVDD2
⎯
Power supply pin of the CH2 output block.
CB2
O
Internal power supply pin of the CH2 gate driver block.
LX2
⎯
CH2 inductor connection pin.
OUT2H
O
CH2 High-side N-ch FET drive output pin.
OUT2L
O
CH2 Low-side N-ch FET drive output pin.
PGND2
⎯
Ground pin of the CH2 output block.
FB3
I
PVDD3A
to
PVDD3I
⎯
Power supply pins of the CH3 output block.
CB3
O
Internal power supply pin of the CH3 gate driver block.
LX3A
to
LX3I
⎯
CH3 inductor connection pins.
PGND3A
to
PGND3I
⎯
Ground pins of the CH3 output block.
FB4
I
PVDD4A
to
PVDD4G
⎯
Power supply pins of the CH4 output block.
CB4
O
Internal power supply pin of the CH4 gate driver block.
LX4A
to
LX4H
⎯
CH4 inductor connection pins.
PGND4A
to
PGND4H
⎯
Ground pins of the CH4 output block.
CH1 Error amplifier input pin, being connected to output of CH1.
CH2 Error amplifier input pin, being connected to output of CH2.
CH3 Error amplifier input pin, being connected to output of CH3.
CH4 Error amplifier input pin, being connected to output of CH4.
(Continued)
4
DS04-27261-6E
MB39C308
Block
Pin Name
I/O
FB5
I
PVDD5A
to
PVDD5H
⎯
Power supply pins of the CH5 output block.
CB5
O
Internal power supply pin of the CH5 gate driver block.
LX5A
to
LX5I
⎯
CH5 inductor connection pins.
PGND5A
to
PGND5I
⎯
Ground pins of the CH5 output block.
FB6
I
PVDD6A
to
PVDD6J
⎯
Power supply pins of the CH6 output block.
CB6
O
Internal power supply pin of the CH6 gate driver block.
LX6A
to
LX6J
⎯
CH6 inductor connection pins.
PGND6A
to
PGND6J
⎯
Ground pins of the CH6 output block.
CTL1
I
CH1 Control input pin. (L : Standby / H : Normal operation)
CTL2
I
CH2 Control input pin. (L : Standby / H : Normal operation)
CTL34
I
CH3 and CH4 control input pin. (L : Standby / H : Normal operation)
CTL5
I
CH5 Control input pin. (L : Standby / H : Normal operation)
CTL6
I
CH6 Control input pin. (L : Standby / H : Normal operation)
PG1
O
CH1 POWERGOOD output pin. (N-ch MOS open drain output)
PG2
O
CH2 POWERGOOD output pin. (N-ch MOS open drain output)
PG3
O
CH3 POWERGOOD output pin. (N-ch MOS open drain output)
PG4
O
CH4 POWERGOOD output pin. (N-ch MOS open drain output)
PG5
O
CH5 POWERGOOD output pin. (N-ch MOS open drain output)
PG6
O
CH6 POWERGOOD output pin. (N-ch MOS open drain output)
ALLPG
O
POWERGOOD output pin (The ALLPG pin outputs “H”, When channels CH3,
CH4, CH5 and CH6 are the power good).
FSEL4
I
CH4 switching frequency setting pin.
FSEL4 = “H” : 700 kHz
FSEL4 = “L” : 0.35 MHz (Shown in the “■ ELECTRICAL CHARACTERISTICS” )
CH5
CH6
Common
Description
CH5 Error amplifier input pin, being connected to output of CH5.
CH6 Error amplifier input pin, being connected to output of CH6.
(Continued)
DS04-27261-6E
5
MB39C308
(Continued)
Block
Pin Name
I/O
VSEL34
I
Preset output voltage setting pin for CH3/CH4.
VSEL34 = “H” : Vout_CH3 =1.8 V, Vout_CH4 = 0.9 V
VSEL34 = “L” : Vout_CH3 =1.5 V, Vout_CH4 = 0.75 V
DVSEL6
I
Preset output voltage setting pin for CH6 dynamically.
DVSEL6 = “H” : Vout_CH6 = 1.1 V
DVSEL6 = “L” : Vout_CH6 = 1.05 V
I
Soft-Start and Soft-Stop time setting pin (Shown in the “■ DESCRIPTION OF
SOFT-START AND SOFT-STOP OPERATION • Soft-Start/Soft-Stop time
(tson/tsoff) Setting Conditions”).
VB
O
Bias voltage output pin for bootstrap and low-side N-ch gate driver of all
channels.
DIN
I
Bias voltage input pin for bootstrap.
DIN pin should be connected with VB pin.
(Shown in the “■ BLOCK DIAGRAM”)
PVDD7
⎯
Power supply pin of VB block.
PGND7
⎯
Ground pin of VB block.
AVDD
⎯
Power supply pin for common block.
VREF
O
Reference voltage output pin.
AGND
⎯
Ground pin of common block.
SS1
SS2
Common
6
Description
DS04-27261-6E
MB39C308
■ BLOCK DIAGRAM
Used in 2-cell Li-Ion power system
MB39C308
System
PVDD1
FB1
OUT1H
Pull up
resistor
Vo1
VIN
(5.5 V to 12.6 V)
Pull up
resistor
Vo2
PG1
CTL1
FB1
PG2
CTL2
FB2
( CH1 5.0 V )
CB1
LX1
OUT1L
C-mode step-down
PGND1
PVDD2
OUT2H
( CH2 3.3 V )
C-mode step-down
Vo1
To 5.0 V system
FB2
Vo2
CB2
LX2
OUT2L
To 3.3 V system
PGND2
DDR
Pull up
resistor
Vo3
PG3
CTL34
VSEL34
FB3
PVDD3A to
PVDD3I
( CH3 1.8 V / 1.5 V )
CB3
C-mode step-down
LX3A to LX3I
PGND3A to
PGND3I
PVDD4A to
PVDD4G
Pull up
resistor
VREF
Vo4
PG4
FSEL4
( CH4 0.9 V / 0.75 V )
CB4
C-mode step-down
LX4A to LX4H
FB3
Vo3
To DDR2/DDR3
FB4
Vo4
To DDR2/DDR3 termination
PGND4A to
PGND4H
FB4
Chip set
Pull up
resistor
Vo5
Pull up
resistor
Vo6
Pull up
resistor
Connecting to
VB/VREF/GND
PG5
CTL5
FB5
PG6
CTL6
DVSEL6
FB6
PVDD5A to
PVDD5H
( CH5 1.5 V )
C-mode step-down
C-mode step-down
To 1.5 V chipset
FB6
Vo6
LX6A to LX6J
To 1.05 V/1.1 V chipset
AVDD
SS1
SS2
CB6
PGND6A to
PGND6J
ALLPG
Vo5
LX5A to LX5I
PGND5A to
PGND5I
PVDD6A to
PVDD6J
( CH6 1.1 V / 1.05 V )
FB5
CB5
Protection
Common
PVDD7
DIN
VB
PGND7
AGND VREF
DS04-27261-6E
7
MB39C308
CURRENT MODE TOPOLOGY
A DC/DC regulation block of Current-mode (C-mode) is illustrated in the “• DC/DC topology, Current mode
operation”.
In this C-mode, the High-side FET is turned ON while the SR-FF is set at every clock cycle generated by on
chip oscillator. During ON period (ton), the current is supplied by VIN, then Inductor current(IL) is increased.
Besides a current (IL/m), which senses the inductor current(IL), flows across a resistor (Rs) then the resister
voltage (Vs) is increased. When the Vs reaches Eout , which is an output of the Error amp, the SR-FF is reset
and the High-side FET is turned OFF (toff) until the next rising clock comes.
The voltage regulation is done by controlling a peak current of the inductor current (IL).
• DC/DC topology, Current mode operation
CB
Bias
Power
Supply
VIN
High-side
Driver
R1
FB
Eout
SR-FF
R2
R
Q
S
VREF
OSC
Drive
Control
Logic
Vs
Bias
Current
Sense
IL
Vo
Low-side
Driver
1 × IL
m
Rs
OSC
IL
Eout
Vs
toff
ton
8
DS04-27261-6E
MB39C308
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
Min
Max
Unit
Power supply voltage
VDD
AVDD, PVDD1 to PVDD7 pin
−0.3
+ 13.5
V
CB voltage
VCB
CB1 to CB6 pin
−0.3
+ 18.5
V
LX voltage
VLX
LX1 to LX6 pin
−0.3
VDD
V
−0.3
+7
V
CB to LX voltage
VCBLX
CB pin to LX pin
OUTH voltage
VOUTH
OUT1H, OUT2H pin
VLX − 0.3
VCB
V
OUTL voltage
VOUTL
OUT1L, OUT2L pin
−0.3
+7
V
DIN voltage
VDIN
DIN pin
−0.3
+7
V
VB voltage
VVB
VB pin
−0.3
+7
V
VREF voltage
VVREF
VREF pin
−0.3
+7
V
CTL voltage
VCTL
CTL1 to CTL6 pin
−0.3
+ 13.5
V
VSEL voltage
VSEL
VSEL34, DVSEL6 pin
−0.3
+7
V
FSEL voltage
VFSEL
FSEL4 pin
−0.3
+7
V
FB voltage
VFB
FB1 to FB6 pin
−0.3
+7
V
PG voltage
VPG
PG1 to PG6, ALLPG pin
−0.3
+7
V
SS voltage
VSS
−0.3
+7
V
Package power dissipation
PD
Ta ≤ + 25 °C
⎯
2940*
mW
Ta = + 85 °C
⎯
1180*
mW
Operating ambient temperature
Ta
⎯
−40
+ 85
°C
TSTG
⎯
−55
+ 125
°C
Storage temperature
⎯
* : See the diagram of “■ TYPICAL CHARACTERISTICS • Maximum Power Dissipation vs. Operating Ambient
Temperature”, for the package power dissipation of Ta from + 25 °C to + 85 °C.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
WARNING: The use of negative voltage below −0.3 Volts on the GND pins (AGND, PGND1 to PGND7) may activate
parasitic transistors on the silicon, which can introduce abnormal operation.
Connecting the LX pin to either VDD pins (AVDD, PVDD1 to PVDD7) or GND pins (AGND, PGND1
to PGND7) directly may cause permanently damage to the device.
DS04-27261-6E
9
MB39C308
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Value
Min
Typ
Max
Unit
Power supply voltage
VDD
AVDD = PVDD1 to PVDD7 pin
5.5
⎯
12.6
V
Input capacitor
CIN
VDD to GND pin
⎯
4.7
⎯
μF
CB to LX capacitor
CCB
CB to LX pin
⎯
0.1
⎯
μF
L1
LX1 pin
⎯
3.3
⎯
μH
L2
LX2 pin
⎯
3.3
⎯
μH
L3
LX3 pin
⎯
1.5
⎯
μH
LX4 pin, FSEL4 pin = H
fosc = 0.7 MHz
⎯
1.5
⎯
LX4 pin, FSEL4 pin = L
fosc = 0.35 MHz
⎯
1.5
⎯
L5
LX5 pin
⎯
1.5
⎯
μH
L6
LX6 pin
⎯
1.5
⎯
μH
IO1
Vo1 (5 V), DC, when RonH1 = 32 mΩ
⎯
1
2*
A
IO2
Vo2 (3.3 V), DC, when RonH2 = 16 mΩ
⎯
2.25
4.5*
A
IO3
Vo3 (1.8 V/1.5 V), DC
⎯
1.35
2.7*
A
IO4
Vo4 (0.9 V/0.75 V), DC
⎯
1
1.5*
A
IO5
Vo5 (1.5 V), DC
⎯
1.25
2.5*
A
IO6
Vo6 (1.1 V/1.05 V), DC
⎯
1.75
3.5*
A
CO1
Vo1 (5 V), when RonH1 = 32 mΩ,
L = 3.3 μH, SS1,SS2 pin = GND
⎯
100
300
μF
CO2
Vo2 (3.3 V), when RonH1 = 16 mΩ,
L = 3.3 μH, SS1,SS2 pin = GND
⎯
100
700
μF
CO3
Vo3 (1.8 V), when L = 1.5 μH,
SS1, SS2 pin = GND
⎯
100
300
μF
CO4
Vo4 (0.9 V), when L = 1.5 μH,
SS1, SS2 pin = GND
⎯
100
500
μF
CO5
Vo5 (1.5 V), when L = 1.5 μH,
SS1, SS2 pin = GND
⎯
100
300
μF
CO6
Vo6 (1.05 V), when L = 1.5 μH,
SS1, SS2 pin = GND
⎯
200
500
μF
RonH1
CH1 High-side FET connected to
OUT1H pin
⎯
32
⎯
mΩ
RonL1
CH1 Low-side FET connected to
OUT1L pin
⎯
32
⎯
mΩ
RonH2
CH2 High-side FET connected to
OUT2H pin
12
16
20
mΩ
RonL2
CH2 Low-side FET connected to
OUT2L pin
⎯
16
⎯
mΩ
LX inductor
Output current
L4
Output capacitor
External FET
On-resistance
μH
(Continued)
10
DS04-27261-6E
MB39C308
(Continued)
Parameter
VB output capacitor
Symbol
CVB
Condition
Value
Unit
Min
Typ
Max
VB pin
⎯
1
⎯
μF
VREF output capacitor
CVREF
VREF pin
⎯
4.7
⎯
μF
VREF output current
IVREF
VREF pin
−1
⎯
0
mA
PG input voltage
VPG
PG1 to PG6, ALLPG pin
⎯
⎯
6
V
PG sink current
IPG
PG1 to PG6, ALLPG pin
⎯
⎯
2
mA
CTL input voltage
VCTL
CTL1 to CTL6 pin
⎯
⎯
AVDD
V
VSEL input voltage
VSEL
VSEL34, DVSEL6 pin
⎯
⎯
6
V
FSEL input voltage
VFSEL
FSEL4 pin
⎯
⎯
6
V
SS1, SS2 pin
⎯
⎯
VB
V
SS input voltage
VSS
* : The MB39C308 is designed with assumed operating conditions, which is 60% of the maximum output current
on the each channel and being operated with recommended input voltage range.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS04-27261-6E
11
MB39C308
■ ELECTRICAL CHARACTERISTICS
(Ta = + 25 °C, AVDD = PVDD1 to PVDD7 = 7.2 V)
Parameter
Reference
voltage
Reference voltage
block
[VREF]
Symbol
VREF
Condition
Value
Unit
Min
Typ
Max
VREF pin = 0 mA
2.45
2.5
2.55
V
Line regulation
VREF
Line
AVDD pin = 5.5 V to 12.6 V
−10
⎯
+ 10
mV
Load regulation
VREF
Load
VREF pin = 0 mA to −1 mA
−15
⎯
+ 15
mV
VVB
5.5 V ≤ AVDD ≤ 12.6 V
VB pin = 0 mA
4.8
5
5.2
V
Load regulation
VB
Load
VB pin = 0 mA to −1 mA
−15
⎯
+ 15
mV
Under-voltage
lockout protection
circuit block
[ UVLO ]
Threshold
voltage
VTLH
AVDD pin
4.5
5.0
5.2
V
Hysteresis
width
VHU
AVDD pin
0.05
0.1
0.4
V
Over-temperature
protection circuit
block
[OTP]
Shutdown
temperature
TOTPH
⎯
+ 150*1
⎯
°C
Hysteresis
width
TH
⎯
+ 25*1
⎯
°C
Threshold
voltage
VIVPH
AVDD pin
12.6
13.0
13.4
V
Release
voltage
VIVPL
AVDD pin
12.5
12.85
13.3
V
Hysteresis
width
VHI
AVDD pin
⎯
0.15
⎯
V
Oscillation
frequency*2
fosc
CH1 to CH3, CH5, CH6
CH4 : FSEL4 pin = “H” Level
0.56
0.7
0.84
MHz
CH4 : FSEL4 pin = “L” Level
0.28
0.35
0.42
MHz
Output on level
VIH
CTL1 to CTL6 pin
2
⎯
⎯
V
Output off level
VIL
CTL1 to CTL6 pin
⎯
⎯
0.8
V
ICTLH
CTL1 to CTL6 pin = 3 V
23
30
43
μA
ICTLL
CTL1 to CTL6 pin = 0 V
⎯
⎯
1
μA
Bias voltage block
[VB]
Input over voltage
protection circuit
block
[IVP]
Oscillator block
[OSC]
Control block
[CTL1 to CTL6]
Bias voltage
Input current
(Continued)
12
DS04-27261-6E
MB39C308
(Ta = + 25 °C, AVDD = PVDD1 to PVDD7 = 7.2 V)
Parameter
Output voltage
select block
[VSEL34,
DVSEL6]
Power good
detection
circuit block
[PG1 to PG6,
ALLPG]
Common block
Condition
Value
Min
Typ
Max
Unit
VSEL34, “H” level
VLGH
VSEL34, DVSEL6 pin
2
⎯
⎯
V
VSEL34, “L” level
VLGL
VSEL34, DVSEL6 pin
⎯
⎯
0.8
V
ISELH
VSEL34, DVSEL6
pin = 3 V
23
30
43
μA
ISELL
VSEL34, DVSEL6
pin = 0 V
⎯
⎯
1
μA
Low side threshold
voltage
VPGL
FB1 to FB6 pin
PG1 to PG6 pin
Vo ×
0.85
Vo ×
0.9
Vo ×
0.95
V
High side threshold
voltage
VPGH
FB1 to FB6 pin
PG1 to PG6 pin
Vo ×
1.05
Vo ×
1.1
Vo ×
1.15
V
⎯
Vo ×
0.03
⎯
V
Input current
⎯
Hysteresis width
VH
PG output low
voltage
VOL
PG1 to PG6, ALLPG pin =
1 mA
⎯
0.1
0.3
V
PG leak current
ILKPG
PG1 to PG6, ALLPG pin =
6V
⎯
⎯
1
μA
AVDD standby
current
IAVDDS
CTL1 to CTL6 pin = 0 V,
AVDD pin = 12.6 V
⎯
⎯
1
μA
AVDD power supply
current
IAVDD
CTL1 to CTL6 pin = 3 V
⎯
0.25
⎯
mA
CH1 output voltage
Vo1
FB1 pin
4.75
5
5.25
V
PVDD1 standby
current
CH1 efficiency
CH1 block
[CH1]
Symbol
OUT1H source
current
OUT1H sink current
OUT1L source
current
IPVDD1S
CTL1 pin = 0 V,
PVDD1 pin = 12.6 V
⎯
⎯
15
μA
ηL1
0.05 × Io (Max) < Io <
0.3 × Io (Max)
87*3
⎯
⎯
%
ηT1
0.3 × Io (Max) < Io <
0.6 × Io (Max)
92*3
⎯
⎯
%
ηF1
0.6 × Io (Max) < Io< Io (Max)
92*3
⎯
⎯
%
Duty ≤ 5%, CB1 pin = 5 V,
IsourceH1 LX1 pin = 0 V,
OUT1H pin = 0 V
⎯
−400*1
⎯
mA
Duty ≤ 5%, CB1 pin = 5 V,
LX1 pin = 0 V,
OUT1H pin = 5 V
⎯
400*1
⎯
mA
⎯
−400*1
⎯
mA
IsinkH1
Duty ≤ 5%, VB pin = 5 V,
IsourceN1 LX1 pin = 0 V,
OUT1L pin = 0 V
(Continued)
DS04-27261-6E
13
MB39C308
(Ta = + 25 °C, AVDD = PVDD1 to PVDD7 = 7.2 V)
Parameter
Value
Unit
Typ
Max
Duty ≤ 5%, VB pin = 5 V,
LX1 pin = 0 V,
OUT1L pin = 5 V
⎯
400*1
⎯
mA
ROH1
OUT1H pin = −15 mA
⎯
12
18
Ω
ROL1
OUT1H pin = 15 mA
⎯
12
18
Ω
ROH1
OUT1L pin = −15 mA
⎯
12
18
Ω
ROL1
OUT1L pin = 15 mA
⎯
12
18
Ω
Vo1 output over voltage
threshold
Vo1
FB1 pin
5.9*1
6*1
6.1*1
V
Vo1 over current limit
IOCP1
Io1
RonH1 = 32 mΩ, L = 3.3 μH
3.4*1
4.0*1
4.6*1
A
FB1 input resistance
RFB1
FB1 pin
⎯
340
⎯
kΩ
Soft Start time
SS1
FB1 pin
SS1 = SS2 = AGND pin
1.19
1.4
1.61
ms
CH2 output voltage
Vo2
FB2 pin
3.135
3.3
3.465
V
OUT1H on resistance
OUT1L on resistance
PVDD2 standby current
CH2 efficiency
OUT2H source current
CH2 block
[CH2]
Condition
Min
OUT1L sink current
CH1 block
[CH1]
Symbol
OUT2H sink current
OUT2L source current
OUT2L sink current
OUT2H on resistance
OUT2L on resistance
IsinkN1
IPVDD2S
CTL2 pin = 0 V,
PVDD2 pin = 12.6 V
⎯
⎯
15
μA
ηL2
0.05 × Io (Max) < Io <
0.3 × Io (Max)
87*3
⎯
⎯
%
ηT2
0.3 × Io (Max) < Io <
0.6 × Io (Max)
92*3
⎯
⎯
%
ηF2
0.6 × Io (Max) < Io < Io (Max)
92*3
⎯
⎯
%
Duty ≤ 5%, CB2 pin = 5 V,
IsourceH2 LX2 pin = 0 V,
OUT2H pin = 0 V
⎯
− 400
⎯
mA
Duty ≤ 5%, CB2 pin = 5 V,
LX2 pin = 0 V,
OUT2H pin = 5 V
⎯
400
⎯
mA
Duty ≤ 5%, VB pin = 5 V,
IsourceN2 LX2 pin = 0 V,
OUT2L pin = 0 V
⎯
− 400
⎯
mA
Duty ≤ 5%, VB pin = 5 V,
LX2 pin = 0 V,
OUT2L pin = 5 V
⎯
400
⎯
mA
ROH2
OUT2H pin = −15 mA
⎯
12
18
Ω
ROL2
OUT2H pin = 15 mA
⎯
12
18
Ω
ROH2
OUT2L pin = −15 mA
⎯
12
18
Ω
ROL2
OUT2L pin = 15 mA
⎯
12
18
Ω
IsinkH2
IsinkN2
(Continued)
14
DS04-27261-6E
MB39C308
(Ta = + 25 °C, AVDD = PVDD1 to PVDD7 = 7.2 V)
Parameter
CH2 block
[CH2]
Symbol
Condition
Vo2 output over voltage
threshold
Vo2
FB2 pin
Vo2 over current limit
IOCP2
IO2
RonH1 = 16 mΩ, L = 3.3 μH
FB2 input resistance
RFB2
FB2 pin
Soft start time
SS2
CH3 output voltage
Vo3
Value
Min
Typ
Max
3.894*1 3.96*1 4.026*1
Unit
V
6.7*1
7.9*1
9.0*1
A
⎯
220
⎯
kΩ
FB2 pin
SS1 = SS2 = AGND pin
1.19
1.4
1.61
ms
VSEL34 = “H” Level,
FB3 pin
1.71
1.8
1.89
V
VSEL34 = “L” Level,
FB3 pin
1.425
1.5
1.575
V
High-side FET
on-resistance
RONH3
LX3 pin = −100 mA,
VGS = 5 V
⎯
65*1
⎯
mΩ
Low-side FET
on-resistance
RONL3
LX3 pin = 100 mA,
VGS = 5 V
⎯
40*1
⎯
mΩ
PVDD3 standby current
IPVDD3S
CTL34 pin = 0 V,
PVDD3 pin = 12.6 V
⎯
⎯
15
μA
ηL31
VSEL34 pin = “H” Level,
Vo3 = 1.8 V
0.05 × Io (Max) < Io <
0.3 × Io (Max)
85*3
⎯
⎯
%
ηL32
VSEL34 pin = “L” Level,
Vo3 = 1.5 V
0.05 × Io (Max) < Io <
0.3 × Io (Max)
82*3
⎯
⎯
%
ηT31
VSEL34 pin = “H” Level,
Vo3 = 1.8 V
0.3 × Io (Max) < Io <
0.6 × Io (Max)
87*3
⎯
⎯
%
ηT32
VSEL34 pin = “L” Level,
Vo3 = 1.5 V
0.3 × Io (Max) < Io <
0.6 × Io (Max)
85*3
⎯
⎯
%
ηF31
VSEL34 pin = “H” Level,
Vo3 = 1.8 V
0.6 × Io (Max) < Io < Io
(Max)
87*3
⎯
⎯
%
ηF32
VSEL34 pin = “L” Level,
Vo3 = 1.5 V
0.6 × Io (Max) < Io < Io
(Max)
85*3
⎯
⎯
%
CH3 block
[CH3]
CH3 efficiency
(Continued)
DS04-27261-6E
15
MB39C308
(Ta = + 25 °C, AVDD = PVDD1 to PVDD7 = 7.2 V)
Parameter
CH3 block
[CH3]
Symbol
Condition
Value
Unit
Min
Typ
Max
VSEL34 pin = “H” Level,
Vo3 = 1.8 V, FB3 pin
2.124*1
2.16*1
2.196*1
V
VSEL34 pin = “L” Level,
Vo3 = 1.5 V, FB3 pin
1.77*1
1.8*1
1.83*1
V
3.0*1
3.75*1
4.5*1
A
⎯
250
⎯
kΩ
Vo3 output over
voltage threshold
VOVP3
Vo3 over current limit
IOCP3
Io3,
L = 1.5 μH
FB3 input resistance
RFB3
FB3 pin
Soft start time
SS3
FB3 pin
SS1 = SS2 = AGND pin
1.19
1.4
1.61
ms
VSEL34 pin = “H” Level,
FB4 pin
0.855
0.9
0.945
V
VSEL34 pin = “L” Level,
FB4 pin
0.7125
0.75
0.7875
V
CH4 output voltage
Vo4
High-side FET
on-resistance
RONH4
LX4 pin = −100 mA,
VGS = 5 V
⎯
130*1
⎯
mΩ
Low-side FET
on-resistance
RONL4
LX4 pin = 100 mA,
VGS = 5 V
⎯
55*1
⎯
mΩ
PVDD4 standby
current
IPVDD4S
CTL34 pin = 0 V,
PVDD4 pin = 12.6 V
⎯
⎯
15
μA
ηT41
VSEL34 pin = “H” Level,
FSEL4 pin =“H” Level,
Vo4 = 0.9 V
0.3 × Io (Max) < Io <
0.6 × Io (Max)
80*3
⎯
⎯
%
ηT42
VSEL34 pin = “L” Level,
FSEL4 pin =“H” Level,
Vo4 = 0.75 V
0.3 × Io (Max) < Io <
0.6 × Io (Max)
80*3
⎯
⎯
%
ηF41
VSEL34 pin = “H” Level,
FSEL4 pin =“H” Level,
Vo4 = 0.9 V
0.6 × Io (Max) < Io < Io (Max)
83*3
⎯
⎯
%
ηF42
VSEL34 pin = “L” Level,
FSEL4 pin =“H” Level,
Vo4 = 0.75 V
0.6 × Io (Max) < Io < Io (Max)
83*3
⎯
⎯
%
VSEL34 pin = “H” Level,
Vo4 = 0.9 V, FB4 pin
1.035*1
1.08*1
1.125*1
V
VSEL34 pin = “L” Level,
Vo4 = 0.75 V, FB4 pin
0.862*1
0.90*1
0.938*1
V
CH4 block
[CH4]
CH4 efficiency
Vo4 output over
voltage threshold
VOVP4
(Continued)
16
DS04-27261-6E
MB39C308
(Ta = + 25 °C, AVDD = PVDD1 to PVDD7 = 7.2 V)
Parameter
CH4 block
[CH4]
IOCP4
Io4,
L = 1.5 μH,fosc = 700 kHz
FB4 input resistance
RFB4
FB4 pin
Soft start time
SS4
FB4 pin,
SS1 = SS2 = AGND pin
Value
Unit
Min
Typ
Max
1.92*1
2.4*1
2.88*1
A
⎯
750
⎯
kΩ
1.19
1.4
1.61
ms
FSEL4, “H” level
VFLGH4
FSEL4 pin
2
⎯
⎯
V
FSEL4, “L” level
VFLGL4
FSEL4 pin
⎯
⎯
0.8
V
IFSELH4
FSEL4 pin = 3 V
23
30
43
μA
IFSELL4
FSEL4 pin = 0 V
⎯
⎯
1
μA
1.425
1.5
1.575
V
CH5 output voltage
Vo5
FB5 pin
High-side FET
on-resistance
RONH5
LX5 pin = −100 mA,
VGS = 5 V
⎯
65*1
⎯
mΩ
Low-side FET
on-resistance
RONL5
LX5 pin = 100 mA,
VGS = 5 V
⎯
40*1
⎯
mΩ
PVDD5 standby
current
IPVDD5S
CTL5 pin = 0 V,
PVDD5 pin = 12.6 V
⎯
⎯
15
μA
ηL5
0.05 × Io (Max) < Io <
0.3 × Io (Max)
82*3
⎯
⎯
%
ηT5
0.3 × Io (Max) < Io <
0.6 × Io (Max)
85*3
⎯
⎯
%
ηF5
0.6 × Io (Max) < Io < Io (Max)
85*3
⎯
⎯
%
Vo5 output over
voltage threshold
VOVP5
FB5 pin
1.77*1
1.8*1
1.83*1
V
Vo5 over current limit
IOCP5
Io5,
L = 1.5 μH
2.8*1
3.5*1
4.2*1
A
FB5 input resistance
RFB5
FB5 pin
⎯
250
⎯
kΩ
Soft start time
SS5
FB5 pin,
SS1 = SS2 = AGND pin
1.19
1.4
1.61
ms
DVSEL6 = “H” Level,
FB6 pin
1.045
1.1
1.155
V
DVSEL6 = “L” Level,
FB6 pin
0.9975
1.05
1.1025
V
CH5 efficiency
CH6 output voltage
CH6 block
[CH6]
Condition
Vo4 over current limit
FSEL4 input current
CH5 block
[CH5]
Symbol
Vo6
High-side FET
on-resistance
RONH6
LX6 pin = −100 mA,
VGS = 5 V
⎯
61*1
⎯
mΩ
Low-side FET
on-resistance
RONL6
LX6 pin = 100 mA,
VGS = 5 V
⎯
35*1
⎯
mΩ
PVDD6 standby
current
IPVDD6S
CTL6 pin = 0 V,
PVDD6 pin = 12.6 V
⎯
⎯
15
μA
(Continued)
DS04-27261-6E
17
MB39C308
(Continued)
(Ta = + 25 °C, AVDD = PVDD1 to PVDD7 = 7.2 V)
Parameter
Symbol
Condition
Value
Unit
Min
Typ
Max
ηL61
DVSEL6 pin = “H” Level,
Vo6 = 1.1 V
0.05 × Io (Max) < Io <
0.3 × Io (Max)
80*3
⎯
⎯
%
ηL62
DVSEL6 pin = “L” Level,
Vo6 = 1.05 V
0.05 × Io (Max) < Io <
0.3 × Io (Max)
80*3
⎯
⎯
%
ηT61
DVSEL6 pin = “H” Level,
Vo6 = 1.1 V
0.3 × Io (Max) < Io <
0.6 × Io (Max)
82*3
⎯
⎯
%
ηT62
DVSEL6 pin = “L” Level,
Vo6 = 1.05 V
0.3 × Io (Max) < Io <
0.6 × Io (Max)
82*3
⎯
⎯
%
ηF61
DVSEL6 pin = “H” Level,
Vo6 = 1.1 V
0.6 × Io (Max) < Io < Io (Max)
81*3
⎯
⎯
%
ηF62
DVSEL6 pin = “L” Level,
Vo6 = 1.05 V
0.6 × Io (Max) < Io < Io (Max)
81*3
⎯
⎯
%
CH6 efficiency
CH6 block
[CH6]
DVSEL6 pin = “H” Level,
Vo6 = 1.1 V, FB6 pin
1.298*1 1.32*1 1.342*1
V
DVSEL6 pin = “L” Level,
Vo6 = 1.05 V, FB6 pin
1.239*1 1.26*1 1.281*1
V
Vo6 output over
voltage threshold
VOVP6
Vo6 over
current limit
IOCP6
IO6,
L = 1.5 μH
FB6 input resistance
RFB6
FB6 pin
Soft start time
SS6
FB6 pin,
SS1 = SS2 = AGND pin
4.0*1
5.0*1
6.0*1
A
⎯
350
⎯
kΩ
1.19
1.4
1.61
ms
*1 : This parameter isn't be specified. This should be used as a reference to support designing the circuits.
*2 : FSEL4 pin is typically recommended to set to “H” level for fosc = 700 kHz setting. When Vo4 is preset to
0.75 V, the ON duty becomes so small at high input voltage. Then, there is a case CH4 output regulation
becomes worse at light load condition. In that case, please set FSEL4 pin to “L” level for fosc = 350 kHz setting.
*3 : This is a reference value, which is evaluated by the recommended EVB circuit. This should be used as a
reference to support designing the circuits.
18
DS04-27261-6E
MB39C308
■ CHANNEL CONTROL FUNCTION
The each channel is turned on and off depending on the voltage levels at the CTL1 pin, CTL2 pin, CTL34 pin,
CTL5 pin and CTL6 pin.
• Channel On/Off Setting Conditions
CTL1
CTL2 CTL34 CTL5
CTL6
CH1
CH2
CH3
CH4
CH5
CH6
L
L
L
L
L
OFF
OFF
OFF
OFF
OFF
OFF
H
L
L
L
L
ON
OFF
OFF
OFF
OFF
OFF
L
H
L
L
L
OFF
ON
OFF
OFF
OFF
OFF
L
L
H
L
L
OFF
OFF
ON
ON
OFF
OFF
L
L
L
H
L
OFF
OFF
OFF
OFF
ON
OFF
L
L
L
L
H
OFF
OFF
OFF
OFF
OFF
ON
H
H
H
H
H
ON
ON
ON
ON
ON
ON
■ POWER GOOD FUNCTION
The Power Good function is shown in the following figure. The ALLPG pin and the PGx pins are connected to
the open drain of the NMOS, and are used by connecting the resistor. When the CTLx pin is turned on, and the
output voltage becomes within 7% of the preset voltage, the PGx pin is changed from “L” to “H”. PGx = “H”
means the status of Power Good. When the change of the output voltage exceeds 10% of the preset voltage,
the PGx pin becomes “L”. And when the output voltage becomes within 7% of the preset voltage, the PGx pin
becomes “H”. Moreover, when all of the channels from CH3 to CH6 are the Power Good, the ALLPG pin becomes
“H”.
Soft Start
Soft Stop
Operation
CTLx
PGx
+10%
Preset Output Voltage
Vox
-7%
+7%
-10%
-7%
PGx
DS04-27261-6E
19
MB39C308
■ PROTECTION
<1> Under Voltage Lock Out Protection (UVLO)
The UVLO prevents IC malfunctions or system damage and the degradation caused by the excessive voltage
or instantaneous voltage drop of the power supply voltage (AVDD), bias voltage (VB), internal reference voltage
(VREF).
The UVLO turns off all the high- and low-side FETs of CH1 to CH6 when the AVDD pin drops below 5.0 V(Typ).
The UVLO is released when the AVDD pin is above 5.1 V (Typ). This is the non-latch type protection.
<2> Input Over Voltage Protection (IVP)
The circuit prevents IC malfunctions or system damage and the degradation caused by the excessive voltage
or instantaneous voltage drop of the power supply voltage (AVDD).
The IVP turns off all the high- and low-side FETs of CH1 to CH6 when the AVDD pin exceeds 13.0 V(Typ). The
IVP is released when the AVDD pin drops below 12.85 V (Typ). This is the non-latch type protection.
<3> Over Temperature Protection (OTP)
The OTP prevents thermal damages on ICs. The IVP function turns off all the high- and low-side FETs of CH1
to CH6 when the junction temperature exceeds +150 °C (Typ). The OPT is released when the temperature drops
below +125 °C (Typ). This is the non-latch type protection.
<4> Output Short Circuit Protection (SCP)
The SCP function stops outputting data when the output voltage falls and protects the devices connected to
outputs.
The SCP timer will start to count when either of output voltages CH1 to CH6 falls due to the output short-circuit
to GND or excessive currents. The SCP function starts to operate the latch protection and turns off all the highand low-side FETs when the output voltage continues to fall to 1.4 ms (Typ).
Follow either of the steps to release the latch of output short circuit protection.
- After all of CTL signals from CH1 to CH6 are set to “L” level, turn on the each CTL signal again.
- When the voltage of the AVDD pin is below the threshold voltage of the UVLO, and then the voltage of the
AVDD pin becomes higher than the threshold voltage of UVLO again, the each output will start up.
<5> Output Over Voltage Protection (OVP)
The OVP protects the devices which are connected to outputs when the output voltage rises. When either output
voltage of the CH1 to CH6 is higher than 120% of each channel's preset voltage (Typ), the OVP turns off all the
high- and low-side FETs of the channels (However, the only CH4 is turned off the high-side FET and turned on
the low-side FET. The CH4 logic is different from other channels as it is controlled with PWM). The OVP is
released when the output voltage is below 103% of the preset voltage (Typ). This is the non-latch type protection.
<6> Over Current Protection (OCP)
The OCP function controls the output current. When drain-to-source current excessively increases, the OCP
controls the output current to the preset value for each channel. Then, because of the OCP functions, the output
voltage usually drops. As a result, the SCP stop the all outputs with the latch setting.
The OCP functions only for the corresponding channels only, however, the SCP stops all of the channels in the
end.
20
DS04-27261-6E
MB39C308
■ DESCRIPTION OF SOFT-START AND SOFT-STOP OPERATION
Soft-start function is featured to avoid inrush current when each channels is turned-on. When the CTL1, CTL2,
CTL34, CTL5 and CTL6 are set to “H” level, ramped-up voltage is fed on an inverting input of an error amplifier
of a channel. Start-time of the soft-start can be predefined and the start time is kept constant independent from
a load of the output of the channels. When the CTL1, CTL2, CTL34, CTL5 and CTL6 are set to “L” level, rampeddown voltage is fed on an inverting input of an error amplifier of a channel then the output voltage goes low.
Stop-time of the Soft-stop can be predefined and the stop-time is kept constant independent from a load of the
output of the channel.
The time of both soft-start and soft-stop can be predefined with combination of the level on the SS1 and the
SS2 pins as shown in the “• Soft-Start/Soft-Stop time (tson/tsoff) Setting Conditions”, and external capacitors
and resistors aren't required
• Soft-Start/Soft-Stop time (tson/tsoff) Setting Conditions
SS1 pin
SS2 pin
Soft-Start time
(tson) (Typ) *
Soft-Stop time
(tsoff) (Typ) *
Unit
Connecting to AGND pin
Connecting to AGND pin
1.4
1.4
ms
Connecting to AGND pin
Connecting to VREF pin
2.2
2.2
ms
Connecting to AGND pin
Connecting to VB pin
2.9
2.9
ms
Connecting to VREF pin
Connecting to AGND pin
3.5
3.5
ms
Connecting to VREF pin
Connecting to VREF pin
4.1
4.1
ms
Connecting to VREF pin
Connecting to VB pin
5.1
5.1
ms
Connecting to VB pin
Connecting to AGND pin
5.9
5.9
ms
Connecting to VB pin
Connecting to VREF pin
7.3
7.3
ms
Connecting to VB pin
Connecting to VB pin
8.2
8.2
ms
* : Accuracy : Typ ±15%
DS04-27261-6E
21
MB39C308
<< Trace of the Output voltage on each channel, during Soft-Start/Soft-Stop operations>>
The sequence of turning on/off different output channels is defined by the CTL1, CTL2, CTL34, CTL5 and CTL6
pins.
(1) When CTLX and CTLY are set to “H” or “L” simultaneously.
CTLX
CTLY
VoX
VoX
(CHX* Output)
VoY
VoY
(CHY* Output)
tson
tsoff
VoX and VoY start their SOFT-START/STOP
operations simultaneously.
(2) When CTLY is set to “H” or “L” after completion
of SOFT-START or -STOP on VoX .
* : CHY and CHX are different CH.
(3) When CTLY is set to “H” or “L” after VoX has
started its SOFT-START or -STOP operation.
CTLX
CTLX
CTLY
CTLY
VoX
VoX
(CHX Output)
VoX
VoX
(CHX Output)
tsoff
tson
VoY
VoY
VoY
(CHY Output)
(CHY Output)
tson
tsoff
tson
VoY
tson
tsoff
tsoff
VoX and VoY start their SOFT-START/STOP
operations simultaneously.
22
DS04-27261-6E
MB39C308
(4) When CTL34 is set to “H” or “L”.
CTL34
Vo3 (1.8 V/1.5 V)
(1.8 V/1.5 V)
(CH3 Output)
Vo4 (0.9 V/0.75 V)
(0.9 V/0.75 V)
(CH4 Output)
Vo3 and Vo4 starts its SOFT-START
/STOP operation simultaneously.
tson
tsoff
■ PRESET FUNCTION OF CH3/CH4/CH6 OUTPUT VOLTAGE
The preset output voltage of CH3 and CH4 are selected by VSEL34 pin condition. Please refer the following table.
The preset output voltage of CH6 is selected by DVSEL6 pin condition. Please refer the following table.
• CH3/CH4/CH6 Preset Output Voltage Conditions
CONNECTION
VREF
GND
VSEL34
Vo3 = 1.8 V setting
Vo4 = 0.9 V setting
Vo3 = 1.5 V setting
Vo4 = 0.75 V setting
DVSEL6
Vo6 = 1.1 V setting
Vo6 = 1.05 V setting
DS04-27261-6E
23
MB39C308
■ TYPICAL CHARACTERISTICS
• Maximum Power Dissipation vs. Operating Ambient Temperature
Power Dissipation vs. Operating Ambient Temperature
4
Power Dissipation PD (W)
Air flow: 0 m/s
3
2
1
0
-50
-25
0
+25
+50
+75
+100
Operating Ambient Temperature Ta ( °C)
The Allowable power dissipation is shown in the “• Maximum Power Dissipation vs. Operating Ambient Temperature”. The maximum power dissipation depends on the thermal capability of the given package, and the ambient
temperature.
Sum of power dissipation of each channel (CH1 to CH6) should not exceed the maximum rating. Expected power
loss of the each channel's over load current are shown in the “• Power Loss Curve for each channel”.
• The condition of the thermal model
Air flow : 0 m/s
MB39C308
(9 mm × 9 mm × 1.3 mm)
Printed circuit board
(FR4 : 117 mm × 84 mm × 0.8 mm)
24
DS04-27261-6E
MB39C308
• Power Loss Curve for each channel
CH1 Output Current vs. Power Loss
CH2 Output Current vs. Power Loss
1.8
VIN=7.2 V
Vo1=5.0 V
Si7212DN using
1.5
1.2
CH2 Power Loss (W)
CH1 Power Loss (W)
1.8
0.9
Thermal design point
0.6
External FET loss is excluded.
0.3
0
1
2
3
4
0.9
Thermal design point
External FET loss
is excluded.
0.6
0.3
0
5
1
2
3
4
CH1 Output Current (A)
CH2 Output Current (A)
CH3 Output Current vs. Power Loss
CH4 Output Current vs. Power Loss
5
1.8
1.8
VIN=7.2 V
Vo3=1.8 V/1.5 V
1.5
Vo3=1.5 V
Vo3=1.8 V
CH4 Power Loss (W)
CH3 Power Loss (W)
1.2
0
0
1.2
0.9
Thermal design point
0.6
0.3
0
Vo4=0.9 V
Vo4=0.75 V
VIN=7.2 V
Vo4=0.9 V/0.75 V
1.5
1.2
0.9
Thermal design point
0.6
0.3
0
0
1
2
3
4
5
0
1
2
3
4
CH3 Output Current (A)
CH4 Output Current (A)
CH5 Output Current vs. Power Loss
CH6 Output Current vs. Power Loss
5
1.8
1.8
VIN=7.2 V
Vo5=1.5 V
1.5
CH6 Power Loss (W)
CH5 Power Loss (W)
VIN=7.2 V
Vo2=3.3 V
Si7212DN (2-para)
using
1.5
1.2
0.9
Thermal design point
0.6
0.3
VIN=7.2 V
Vo6=1.1 V/1.05 V
1.5
Vo6=1.1 V
Vo6=1.05 V
1.2
0.9
Thermal design point
0.6
0.3
0
0
0
1
2
3
CH5 Output Current (A)
DS04-27261-6E
4
5
0
1
2
3
4
5
CH6 Output Current (A)
25
MB39C308
■ NOTES FOR UNCONNECTED PINS
1. PIN CONNECTION WHEN NOT USING CH1 or CH2
When CH1 or CH2 are not used, connect the PVDD pins to power supply, connect the PG pins, CTL pins and
FB pins to Analog ground (AGND), leave OUTH pins, OUTL pins, CB pins and LX pins open and connect the
PGND pins to Power ground.
• CH1 is not used
PG1
1
CTL1
FB1
PVDD1
Power supply
OUT1H
“OPEN”
CB1
“OPEN”
LX1
“OPEN”
OUT1L
“OPEN”
PGND1
• CH2 is not used
PG2
1
CTL2
FB2
PVDD2
Power supply
OUT2H
“OPEN”
CB2
“OPEN”
LX2
“OPEN”
OUT2L
“OPEN”
PGND2
26
DS04-27261-6E
MB39C308
2. PIN CONNECTION WHEN NOT USING CH3 and CH4
When CH3 and CH4 are not used, connect the PVDD pins to power supply, connect the FSEL4 pin, VSEL34
pin, PG pins, CTL34 pins and FB pins to Analog ground (AGND), leave CB pins and LX pins open and connect
the PGND pins to Power ground.
• CH3 and CH4 are not used
FSEL4
PVDD3
Power supply
VSEL34
PG3
CB3
“OPEN”
CTL34
LX3
“OPEN”
FB3
PGND3
PVDD4
PG4
Power supply
CB4
“OPEN”
LX4
“OPEN”
FB4
PGND4
DS04-27261-6E
27
MB39C308
3. PIN CONNECTION WHEN NOT USING CH4, BUT USING CH3
When CH4 is not used but CH3 is used, connect the PVDD4 pins to VB pin through around 5 kΩ resistor, connect
the PG4 pin to Analog ground (AGND), connect 0.1 μF capacitor between CB4 and LX4 pins and connect the
PGND4 pin to Power ground, connect FSEL4 and FB4 pins to VREF pin.
• CH4 is not used, but CH3 is used
VB
VREF
FSEL4
PVDD4
around 5 kΩ
Control signal : “H”
FB4
CB4
CTL34
LX4
0.1 μF
PG4
PGND4
Note : Both CH3 and CH4 become active when CTL34 is on. Connect the pins like shown up above when CH4 is
not used but CH3 is used. PVDD4 must not be open.
4. PIN CONNECTION WHEN NOT USING CH5
When CH5 is not used, connect the PVDD5 pins to power supply, connect the PG5, CTL5 and FB5 pins to
Analog ground (AGND), leave CB5 and LX5 pins open and connect the PGND5 pin to Power ground.
• CH5 is not used
PVDD5
Power supply
PG5
CB5
“OPEN”
CTL5
LX5
“OPEN”
FB5
PGND5
28
DS04-27261-6E
MB39C308
5. PIN CONNECTION WHEN NOT USING CH6
When CH6 is not used, connect the PVDD6 pins to power supply, connect the PG6, CTL6, FB6 and DVSEL6
pins to Analog ground (AGND), leave CB6 and LX6 pins open and connect the PGND6 pin to Power ground.
• CH6 is not used
PVDD6
Power supply
PG6
CB6
“OPEN”
CTL6
LX6
“OPEN”
FB6
DVSEL6
PGND6
6. PIN CONNECTION WHEN NOT USING POWERGOOD FUNCTION
When the Power good function is not used, connect the PG pins or ALLPG pin to Analog ground (AGND).
• PG or ALLPG are not used
PG
ALLPG
DS04-27261-6E
29
MB39C308
■ APPLICATION NOTE
• Inductor Selection
See the “■RECOMMENDED OPERATING CONDITIONS” for the recommended inductance. Furthermore, to
confirm whether the current flowing through the inductor is within the rated value, the maximum value of the
current flowing through the inductor needs to be found. The maximum current flowing through the inductor can
be found from the following formula.
ILMAX ≥ IoMAX +
ΔIL =
VDD − VO
L
ΔIL
2
×
VO
VDD × fOSC
ILMAX : Maximum current through inductor [A]
IoMAX : Maximum load current [A]
ΔIL
: Inductor ripple current peak-to-peak value [A]
VDD
: Switching power supply voltage [V]
VO
: Output setting voltage [V]
fOSC
: Switching frequency [Hz]
Inductor current
ILMAX
IoMAX
ΔIL
0
30
Time
DS04-27261-6E
MB39C308
• FET Selection (CH1, CH2)
This IC operation requires the voltage which is generated between drain and source on the high-side FET. Set
the on resistance of high-side FET within the below range for reference.
CH1 high-side FET on resistance : 24 mΩ to 40 mΩ
CH2 high-side FET on resistance : 12 mΩ to 20 mΩ
The current limit value for over current protection (OCP) is determined by the high-side FET on resistance in
use. The current limit value is obtained by the following formula.
IO1_OCP =
IO2_OCP =
0.141
RON1
0.133
RON2
−
−
0.5
L × fOSC
0.5
L × fOSC
×
×
(VDD − VO1) × VO1
VDD
(VDD − VO2) × VO2
VDD
VDD
: Switching system power supply voltage [V]
VO
: Output setting voltage [V]
RON
: High-side FET on resistance [Ω]
L
: Inductor value [H]
fOSC
: Switching frequency [Hz]
Also, 2.5 V drive products are recommended for the high-side FET. A bootstrap diode is recommended to connect
to the high-side FET for the use of 4 V drive products (see “• Bootstrap Diode Selection” for the detail).
In order to judge whether the electrical current flowing through the FET is within the rated value, the maximum
value of the current flowing through the FET needs to be found. The maximum current flowing through the FET
can be found from the following formula.
IDMAX ≥ IoMAX +
ΔIL
2
IDMAX : Maximum value of FET drain current [A]
IoMAX : Maximum load current [A]
ΔIL
: Inductor ripple current peak-to-peak value [A]
Furthermore, in order to judge whether the power dissipation of the FET is within the rated value, the power
dissipation of the FET needs to be found. The power dissipation of the high-side FET can be found from the
following formula.
PHisideFET = PRON + PSW
PHisideFET : High-side FET power dissipation [W]
PRON
: High-side FET conducting power dissipation [W]
PSW
: High-side FET SW power dissipation [W]
DS04-27261-6E
31
MB39C308
High-side FET conducting power dissipation
VO
PRON = (IoMAX) 2 ×
VDD
× RON
PRON : High-side FET conducting power dissipation [W]
IoMAX : Maximum load current [A]
VDD
: Switching system power supply voltage [V]
VO
: Output setting voltage [V]
RON
: High-side FET on resistance [Ω]
High-side FET switching power dissipation
PSW =
VDD × fOSC × (Ibtm × tr + Itop × tf)
2
PSW
: Switching power dissipation [W]
VDD
: Switching system power supply voltage [V]
fOSC
: Switching frequency (Hz)
Ibtm : Inductor ripple current bottom value [A]
Itop : Inductor ripple current top value [A]
tr
: High-side FET turn-on time [s]
tf
: High-side FET turn-off time [s]
tr and tf can be found simply from the following formula.
tr =
Qgd × 12
5 − Vth
tf =
Qgd × 12
Vth
Qgd : Gate-Drain charge of High-side FET [C]
Vth
: High-side FET threshold voltage [V]
The power dissipation of the Low-side FET can be found from the following formula.
PLosideFET = PRon = (IOMAX) 2 × (1
VO
VDD
) × Ron
PRon : Low-side FET conducting power dissipation [W]
IoMAX : Maximum load current [A]
VDD
: Switching power supply voltage [V]
VO
: Output setting voltage [V]
Ron
: Low-side FET on resistance [Ω]
Note : The transition voltage of the voltage between the drain and source of the Low-side FET is generally small
and the switching power loss is negligible. Therefore it has been omitted from this formula.
32
DS04-27261-6E
MB39C308
• Input Capacitor Selection
Because this IC uses the C-Mode system, it is recommended to use ceramic capacitors with a small ESR. See
the “■ RECOMMENDED OPERATING CONDITIONS” for the value of the capacitance.
• Output Capacitor Selection
Because this IC uses the C-Mode system, it is recommended to use ceramic capacitors with a small ESR. See
the “■ RECOMMENDED OPERATING CONDITIONS” for the value of the capacitance.
• Bootstrap Diode Selection
It is not necessary to connect diode to the outside device normally because this device contains a bootstrap
diode. However, it is recommended to add a shotkey barrier diode (SBD) when 4 V drive products is used for
CH1 and CH2 switching FET. In this case, select the smallest forward current possible and connect as the figure
below.
• When adding bootstrap SBD to CH1
CB1
VB
The current to drive on the gate of high-side FET flows to the SBD of the bootstrap diode. The average current
can be found by the following formula. However, set the current which does not exceed the maximum rating.
ID ≥ Qg × fOSC
ID
: Forward current [A]
Qg
: Total gate electric charge of high-side FET [C]
fOSC
: Switching frequency [Hz]
The voltage rating of bootstrap capacitor can be found by the following formula.
VR_BOOT > VDD
VR_BOOT : Bootstrap diode DC reverse voltage [V]
VDD
: Switching power supply voltage [V]
DS04-27261-6E
33
MB39C308
• Bootstrap Capacitor Selection
Although the default bootstrap capacitor (the capacitor between CB and LX) is 0.1μF, this may need to be adjusted
if the FET used on CH1 and CH2 have a large Qg. The bootstrap capacitor needs to be able to charge sufficiently
to drive the gate of the High-side FET. As a rough guide, select a capacitor with a minimum value of capacitance
that is able to accumulate approximately 10 times the charge of the Qg of the High-side FET.
Qg
CCB ≥ 10 ×
VCB
CCB
: Bootstrap capacitance [F]
Qg
: High-side SWFET gate charge [C]
VCB
: CB voltage (4.3 V)
• VB Capacitor Selection
Although the default VB capacitor is 1 μF, this may need to be adjusted if the FET used on CH1 and CH2 have
a large Qg. The VB capacitor needs to be able to charge sufficiently to drive the gate of the High-side FET. As
a rough guide, select a capacitor with a minimum value of capacitance that is able to accumulate approximately
50 times the charge of the Qg of the High-side FET.
CVB
(
QgH12 + 9.3 × 10-9
VCB
+
QgL12 + 23 × 10-9
VVB
(
CVB ≥ 50 ×
: VB capacitance [F]
QgH12 : Total gate charge of High-side FET for CH1 and CH2 [C] (Total when Vgs = 4.3 V)
QgL12 : Total gate charge of Low-side FET for CH1 and CH2 [C] (Total when Vgs = 5 V)
34
VVB
: VB voltage (5 V)
VCB
: CB voltage (4.3 V)
DS04-27261-6E
MB39C308
• Power Dissipation and Thermal Design
Although these does not need to be examined in most cases because the IC is highly efficient, Dissipation and
the thermal design may need to be investigate if the IC is used with high power supply voltages, high oscillator
frequencies, high loads, or at high temperatures.
The internal IC power dissipation (PIC) can be found from the following formula.
PIC = VDD × (IDD + Qg12 + 32 × 10-9) × fOSC + PHisideFET3-6 + PLosideFET3-6
PIC
: Internal IC power dissipation [W]
VDD
: Power supply voltage (VIN) [V]
IDD
: Power supply current [A] (250 μA Typ)
Qg12
: Total gate charge of High-side FET (VGS = 4.3 V) and Low-side FET (VGS = 5 V) for CH1 and CH2 [C]
fOSC
: Switching frequency [Hz]
PHisideFET3-6 : Total High-side SWFET power dissipation of internal High-side FET [W]
PLosideFET3-6 : Total Low-side SWFET power dissipation of internal Low-side FET [W]
Furthermore, the power dissipation of the High-side FET of each built-in channel can be found from the following
formula.
PHisideFET = PRON + PSW
PHisideFET : High-side FET power dissipation [W]
PRON
: High-side FET conducting power dissipation [W]
PSW
: High-side FET switching power dissipation [W]
High-side FET conducting power dissipation
PRON = (IoMAX) 2
VO
VDD
× RON
PRON : High-side FET conducting power dissipation [W]
IoMAX : Maximum load current [A]
VDD
: Switching power supply voltage [V]
VO
: Output setting voltage [V]
RON : On resistance of High-side FET [Ω]
DS04-27261-6E
35
MB39C308
High-side FET switching power dissipation
VDD × fOSC × (Ibtm × tr + Itop × tf)
PSW =
2
PSW : SW power dissipation [W]
VDD
: Switching system power supply voltage [V]
fOSC : Oscillation frequency (Hz)
Ibtm : Inductor ripple current bottom value [A]
Itop : Inductor ripple current top value [A]
tr
: High-side FET turn-on time [s]
tf
: High-side FET turn-off time [s]
tr and tf are simply given by the following values.
tr = 4 ns
tf = 4 ns
The power dissipation of the Low-side FET can be found from the following formula.
PRon = (IOMAX)2 × (1 −
VO
VDD
) × Ron
PRon : Low-side FET conducting power dissipation [W]
IoMAX : Maximum load current [A]
VDD
: Switching system power supply voltage [V]
VO
: Output setting voltage [V]
Ron
: Low-side FET on resistance [Ω]
Note : The transition voltage of the voltage between the drain and source of the Low-side FET is generally small
and the switching power loss is negligible. Therefore it has been omitted from this formula.
The junction temperature (Tj) can be found from the following formula.
Tj = Ta + θja × PIC
Tj : Junction temperature [ °C] ( + 125 °C Max)
Ta : Ambient temperature [ °C]
θja : PFBGA-208 package thermal resistance (34 °C/W)
PIC : IC power dissipation [W]
36
DS04-27261-6E
MB39C308
■ REFERENCE DATA
• Efficiency vs. load current
CH2 η2 - IO2
CH1 η1 - IO1
100
95
efficiency η2 (%)
efficiency η1 (%)
100
90
85
80
75
95
90
85
80
75
70
70
65
65
60
0.01
0.1
1
60
0.01
10
efficiency η3 (%)
95
CH3 η3 - IO3
100
Vo3 = 1.8 V
Vo3 = 1.5 V
95
efficiency η4 (%)
100
90
85
80
75
90
65
60
0.01
10
CH5 η5 - IO5
100
95
efficiency η6 (%)
efficiency η5 (%)
95
90
85
80
75
DS04-27261-6E
10
CH6 η6 - IO6
VO6 = 1.05 V
VO6 = 1.1 V
75
65
Load current IO5 (A)
10
80
65
1
1
85
70
0.1
0.1
90
70
60
0.01
fosc = 700 kHz, VO4 = 0.9 V
fosc = 700 kHz, VO4 = 0.75 V
fosc = 350 kHz, VO4 = 0.9 V
fosc = 350 kHz, VO4 = 0.75 V
Load current IO4 (A)
Load current IO3 (A)
100
CH4 η4 - IO4
75
65
1
10
80
70
0.1
1
85
70
60
0.01
0.1
Load current IO2 (A)
Load current IO1 (A)
60
0.01
0.1
1
10
Load current IO6 (A)
37
MB39C308
• Load regulation
CH2 VO2 vs. IO2
Output voltage VO2 (V)
Ta = + 25°C
VO1 = 5.0 V
fosc = 700 kHz
Ta = + 25°C
VO2 = 3.3 V
fosc = 700 kHz
Load current IO2 (A)
CH3 VO3 vs. IO3
CH3 VO3 vs. IO3
Ta = + 25°C
VO3 = 1.5 V
fosc = 700 kHz
Output voltage VO3 (V)
Load current IO1 (A)
Ta = + 25°C
VO3 = 1.8 V
fosc = 700 kHz
Load current IO3 (A)
Load current IO3 (A)
CH4 VO4 vs. IO4
CH4 VO4 vs. IO4
fosc = 350 kHz
fosc = 700 kHz
Ta = + 25°C
VO4 = 0.75 V
Load current IO4 (A)
Output voltage VO4 (V)
Output voltage VO4 (V)
Output voltage VO3 (V)
Output voltage VO1 (V)
CH1 VO1 vs. IO1
fosc = 350 kHz
fosc = 700 kHz
Ta = + 25°C
VO4 = 0.9 V
Load current IO4 (A)
(Continued)
38
DS04-27261-6E
MB39C308
(Continued)
Output voltage VO5 (V)
CH5 VO5 vs. IO5
Ta = + 25°C
VO5 = 1.5 V
fosc = 700 kHz
Load current IO5 (A)
CH6 VO6 vs. IO6
Ta = + 25°C
VO6 = 1.05 V
fosc = 700 kHz
Load current IO6 (A)
DS04-27261-6E
Output voltage VO6 (V)
Output voltage VO6 (V)
CH6 VO6 vs. IO6
Ta = + 25°C
VO6 = 1.1 V
fosc = 700 kHz
Load current IO6 (A)
39
MB39C308
• Line regulation
Ta = + 25°C
VO1 = 5.0 V
fosc = 700 kHz
CH2 VO2 vs. VIN
Output voltage VO2 (V)
Output voltage VO1 (V)
CH1 VO1 vs. VIN
Input voltage VIN (V)
Input voltage VIN (V)
CH3 VO3 vs. VIN
Output voltage VO3 (V)
Output voltage VO3 (V)
CH3 VO3 vs. VIN
Ta = + 25°C
VO3 = 1.5 V
fosc = 700 kHz
Input voltage VIN (V)
CH4 VO4 vs. VIN
Output voltage VO4 (V)
Output voltage VO4 (V)
CH4 VO4 vs. VIN
Ta = + 25°C
VO4 = 0.75 V
Ta = + 25°C
VO3 = 1.8 V
fosc = 700 kHz
Input voltage VIN (V)
Input voltage VIN (V)
fosc = 350 kHz
fosc = 700 kHz
Ta = + 25°C
VO2 = 3.3 V
fosc = 700 kHz
fosc = 350 kHz
fosc = 700 kHz
Ta = + 25°C
VO4 = 0.9 V
Input voltage VIN (V)
(Continued)
40
DS04-27261-6E
MB39C308
(Continued)
Output voltage VO5 (V)
CH5 VO5 vs. VIN
Ta = + 25°C
VO5 = 1.5 V
fosc = 700 kHz
Input voltage VIN (V)
Ta = + 25°C
VO6 = 1.05 V
fosc = 700 kHz
Input voltage VIN (V)
DS04-27261-6E
CH6 VO6 vs. VIN
Output voltage VO6 (V)
Output voltage VO6 (V)
CH6 VO6 vs. VIN
Ta = + 25°C
VO6 = 1.1 V
fosc = 700 kHz
Input voltage VIN (V)
41
MB39C308
• Waveforms at load step response
CH2 (VO2 = 3.3 V)
CH1 (VO1 = 5.0 V)
IO1 = 0 A
2 A, IO1 slew rate = 2 A/μs
I O2 = 0 A
Ta = + 25 °C
VIN = 7.2 V
VO1 = 5.0 V
fosc = 700 kHz
4
IO2 2 A/div
IO1 2A/div
VO2 500 mV/div
3.3 V 1
1
100 μs/div
100 μs/div
CH3 (VO3 = 1.8 V)
CH3 (VO3 = 1.5 V)
IO3 = 0 A 2.7 A, IO3 slew rate = 2.7 A/μs
IO3 1 A/div
I O3 = 0 A
Ta = + 25 °C
VIN = 7.2 V
VO3 = 1.5 V
fosc = 700 kHz
2.7 A, IO3 slew rate = 2.7 A/μs
IO3 1 A/div
VO3 200 mV/div
VO3 200 mV/div
1.8 V
1
1
100 μs/div
100 μs/div
CH4 (fosc = 350 kHz, VO4 = 0.75 V)
IO4 = 0 A
1.5 A, IO4 slew rate = 1.5 A/μs
CH4 (fosc = 350 kHz, VO4 = 0.9 V)
1.5 A, IO4 slew rate = 1.5 A/μs
IO4 = 0 A
Ta = + 25 °C
VIN = 7.2 V
VO4 = 0.9 V
fosc = 350 kHz
Ta = + 25 °C
VIN = 7.2 V
VO4 = 0.75 V
fosc = 350 kHz
4
IO4 1 A/div
IO4 1 A/div
4
VO4 100 mV/div
VO4 100 mV/div
0.75 V
Ta = + 25 °C
VIN = 7.2 V
VO3 = 1.8 V
fosc = 700 kHz
4
4
1.5 V
Ta = + 25 °C
VIN = 7.2 V
VO2 = 3.3 V
fosc = 700 kHz
4
VO1 500 mV/div
5V
4.5 A, IO2 slew rate = 4.5 A/μs
0.9 V
1
100 μs/div
1
100 μs/div
(Continued)
42
DS04-27261-6E
MB39C308
(Continued)
CH4 (fosc = 700 kHz, VO4 = 0.75 V)
CH4 (fosc = 700 kHz, VO4 = 0.9 V)
I O4 = 0 A
I O4 = 0 A
1.5 A, IO4 slew rate = 1.5 A/μs
Ta = + 25 °C
VIN = 7.2 V
VO4 = 0.9 V
fosc = 700 kHz
Ta = + 25 °C
VIN = 7.2 V
VO4 = 0.75 V
fosc = 700 kHz
IO4 1 A/div
4
4
IO4 1 A/div
VO4 100 mV/div
VO4 100 mV/div
0.75 V
1.5 A, IO4 slew rate = 1.5 A/μs
0.9 V
1
1
100 μs/div
100 μs/div
CH5 (VO5 = 1.5 V)
IO5 = 0 A
2.5 A, IO5 slew rate = 2.5 A/μs
Ta = + 25 °C
VIN = 7.2 V
VO5 = 1.5 V
fosc = 700 kHz
IO5 1 A/div
4
VO5 200 mV/div
1.5 V
1
100 μs/div
CH6 (VO6 = 1.05 V)
CH6 (VO6 = 1.1 V)
I O6 = 0 A
I O6 = 0 A
3.5 A, IO6 slew rate = 3.5 A/μs
IO6 2 A/div
Ta = + 25 °C
VIN = 7.2 V
VO6 = 1.05 V
fosc = 700 kHz
3.5 A, IO6 slew rate = 3.5 A/μs
IO6 2 A/div
Ta = + 25 °C
VIN = 7.2 V
VO6 = 1.1 V
fosc = 700 kHz
4
4
VO6 100 mV/div
VO6 100 mV/div
1.05 V 1
1.1 V
100 μs/div
DS04-27261-6E
1
100 μs/div
43
MB39C308
• Waveform at Soft-start and Soft-stop
CH1
CH2
1
1
CTL1:2 V/div
2
CTL2:2 V/div
Ta = + 25 °C
VIN = 7.2 V
VO1 = 5.0 V
IO1 = 2 A
fosc = 700 kHz
Ta = + 25 °C
VIN = 7.2 V
VO2 = 3.3 V
IO2 = 4.5 A
fosc = 700 kHz
2
VO1: 2 V/div
VO2: 2 V/div
5 ms/div
5 ms/div
CH5
CH3, CH4
1
1
CTL34:2 V/div
VO3: 500 mv/div
Ta = + 25 °C
VIN = 7.2 V
VO3 = 1.8 V
IO3 = 2.7 A
VO4 = 0.9 V
IO4 = 1.5 A
fosc = 700 kHz
CTL5:2 V/div
Ta = + 25 °C
VIN = 7.2 V
VO5 = 1.5 V
IO5 = 2.5 A
fosc = 700 kHz
2
2
3
VO4: 500 mV/div
5 ms/div
VO5: 500 mV/div
5 ms/div
CH6
1
CTL6:2 V/div
2
Ta = + 25 °C
VIN = 7.2 V
VO6 = 1.05 V
IO6 = 3.5 A
fosc = 700 kHz
VO6:500 mV/div
5 ms/div
44
DS04-27261-6E
MB39C308
■ TYPICAL APPLICATION CIRCUIT
M1
MB39C308PFBGA208
CTL1
OUT1H
G15
FB1
5 6
Q1
S 3
C13
G
4
CB1 D16
LX1 E16 0.22 μF
VB
CTL2
OUT2H
FB2
CB2 J16
1 2 5 6 7
G
3
C14
S 4
02
LX2 H16 0.22 μF
OUT2L
VB
J15
VIN
R4
Pattern short
R9
PG4
VO4
VIN
VIN
VINs
PGNDs
PGND
G14
PG4
VREF
0Ω
100 kΩ
VB
C12
P7
FSEL4
FB4
PVDD4A
PVDD4B
PVDD4C
PVDD4D
PVDD4E
PVDD4F
PVDD4G
P3
P2
R3
R2
R1
T3
T2
CB4
LX4A
LX4B
LX4C
LX4D
LX4E
LX4F
LX4G
LX4H
PGND4A
PGND4B
PGND4C
PGND4D
PGND4E
PGND4F
PGND4G
PGND4H
P16 0.1 μF
P15
R16
R15
R14
R13
T15
T14
T13
P12
P11
P10
R12
R11
R10
T12
T11
T10
P4
P6
P5
R6
R5
R4
T6
T5
T4
VO3
Vo3s
Vo3
L3
1.5 μH
C3
FB3
C15
VIN
C16
0.1 μF
VO4
Vo4s
Vo4
L4
1.5 μH
C4
VSEL34
100 μF
C11
P13
VO3
CTL34
0Ω
Pattern short
R8
VREF
L16
L15
L14
M16
M15
M14
N16
N15
N14
P14
100 μF
C14
CTL34
PVDD3A
PVDD3B
PVDD3C
PVDD3D
PVDD3E
PVDD3F
PVDD3G
PVDD3H
PVDD3I
CB3
LX3A
LX3B
LX3C
LX3D
LX3E
LX3F
LX3G
LX3H
LX3I
PGND3A
PGND3B
PGND3C
PGND3D
PGND3E
PGND3F
PGND3G
PGND3H
PGND3I
4.7 μF
PG3
4.7 μF
H14
PG3
3.3 μH
1 2 5 67
G
FDMA420NZ
3
S 4
03
R3
100 kΩ
PGND2 G16
VO2
Vo2s
Vo2
L2
C2
H15
VO2
K15
100 μF
CTL2
C8
PG2
C15
D1
D2
D2
D4
D5
PG2
FDMA420NZ
PVDD2 K16
D1
D2
D2
D4
D5
J14
4.7 μF
VIN
R2
100 kΩ
PGND1 F16
3.3 μH
7 8
Q1
S 1
ECH8607
100 μF
G
2
OUT1L F15
VO1
Vo1s
Vo1
L1
C9
VO1
E15
C1
CTL1
C16
C7
PVDD1
4.7 μF
PG1
D15
C10
PG1
VIN
ECH8607
D1
D2
K14
D1
D2
R1
100 kΩ
VB
P9
P8
R9
R8
R7
T9
T8
T7
(Continued)
DS04-27261-6E
45
MB39C308
(Continued)
M1
MB39C308PFBGA208
L3
FB5
CB5
LX5A
LX5B
LX5C
LX5D
LX5E
LX5F
LX5G
LX5H
LX5I
PVDD6A
PVDD6B
PVDD6C
PVDD6D
PVDD6E
PVDD6F
PVDD6G
PVDD6H
PVDD6I
PVDD6J
A10
A9
A8
A7
B10
B9
B8
B7
C9
C8
C10
FB6
VB
CB6
C7
LX6A
LX6B
LX6C
LX6D
LX6E
LX6F
LX6G
LX6H
LX6I
LX6J
A6
A5
A4
B6
B5
B4
C6
C5
C4
C3
PGND6A
PGND6B
PGND6C
PGND6D
PGND6E
PGND6F
PGND6G
PGND6H
PGND6I
PGND6J
A3
A2
B3
B2
B1
C2
C1
D3
D2
D1
VO6
Vo6s
Vo6
L6
0.1 μF
1.5 μH
M1
MB39C308PFBGA208
E7 Thermal1
E8 Thermal2
E9 Thermal3
E10 Thermal4
F6 Thermal5
F7 Thermal6
F8 Thermal7
F9
F10 Thermal8
Thermal9
F11 Thermal10
G5 Thermal11
G6 Thermal12
G7 Thermal13
G8 Thermal14
G9 Thermal15
G10 Thermal16
G11 Thermal17
G12 Thermal18
H5 Thermal19
H6 Thermal20
H7 Thermal21
H8 Thermal22
H9 Thermal23
H10 Thermal24
H11 Thermal25
H12 Thermal26
J5 Thermal27
J6 Thermal28
J7 Thermal29
J8 Thermal30
J9 Thermal31
J10 Thermal32
J11 Thermal33
J12 Thermal34
K5 Thermal35
K6 Thermal36
K7 Thermal37
K8 Thermal38
K9 Thermal39
K10 Thermal40
K11 Thermal41
K12 Thermal42
L6 Thermal43
L7 Thermal44
L8 Thermal45
L9 Thermal46
L10 Thermal47
L11 Thermal48
M7 Thermal49
M8 Thermal50
M9 Thermal51
M10 Thermal52
AGND
R7
VIN
PVDD7 A11
PGND7
B15
SS2
A13
1 μF
1 μF
SS1
VIN
VB
VB A12
DIN
VB
VREF
A14
C22
VREF
B12
1 μF
B16
C19
AGND B14
C20
ALLPG
AVDD A15
C21
D14
VB
46
C18
4.7 μF
VO6
DVSEL6
C6-2
B11
DVSEL6
100 μF
CTL6
CTL6
4.7 μF
PG6
B13
100 kΩ
E3
E2
E1
F3
F2
F1
G3
G2
G1
1.5 μH
VIN
E14
PG6
ALLPG
PGND5A
PGND5B
PGND5C
PGND5D
PGND5E
PGND5F
PGND5G
PGND5H
PGND5I
VO5
Vo5s
Vo5
L5
H3 0.1 μF
H2
H1
J3
J2
J1
K3
K2
K1
R6
100 kΩ
VB
C17
L2
C6-1
100 μF
VO5
C5
CTL5
CTL5
C11
PG5
C13
L1
M3
M2
M1
N3
N2
N1
P1
C12
PG5
PVDD5A
PVDD5B
PVDD5C
PVDD5D
PVDD5E
PVDD5F
PVDD5G
PVDD5H
VIN
100 μF
F14
4.7 μF
R5
100 kΩ
VB
VREF
DS04-27261-6E
MB39C308
■ PARTS LIST
Symbol
Part name
Model name
Specification
Package
Vendor
Remarks
M1
IC
MB39C308
⎯
PFBGA-208
FML
⎯
Q1
N-ch Dual MOSFET
ECH8607
VDS = 30 V,
ID = 5 A (Max)
ECH8
SANYO
Ch1
High &
Low-side
Q2-1
N-ch MOSFET
FDMA420NZ
VDS = 20 V,
ID = 5.7 A
(Max)
MLP2x2-6L
FAIRCHILD
Ch2
High-side
Q3-1
N-ch MOSFET
FDMA420NZ
VDS = 20 V,
ID = 5.7 A
(Max)
MLP2x2-6L
FAIRCHILD
Ch2
Low-side
Q2-2
N-ch MOSFET
⎯
⎯
SOT-6
⎯
(Ch2
High-side)
Q3-2
N-ch MOSFET
⎯
⎯
TSOP-6
⎯
(Ch2
Low-side)
R1
Resistor
RR0816P-104-D
100 kΩ
1608
SSM
PG
R2
Resistor
RR0816P-104-D
100 kΩ
1608
SSM
PG
R3
Resistor
RR0816P-104-D
100 kΩ
1608
SSM
PG
R4
Resistor
RR0816P-104-D
100 kΩ
1608
SSM
PG
R5
Resistor
RR0816P-104-D
100 kΩ
1608
SSM
PG
R6
Resistor
RR0816P-104-D
100 kΩ
1608
SSM
PG
R7
Resistor
RR0816P-104-D
100 kΩ
1608
SSM
PG
R8
Resistor
⎯
Pattern short
⎯
⎯
VSEL34
R9
Resistor
⎯
Pattern short
⎯
⎯
FSEL4
C1
Ceramic Capacitor
C3225JB0J107M
100 μF (6.3 V)
3225
TDK
VO
C2
Ceramic Capacitor
C3225JB0J107M
100 μF (6.3 V)
3225
TDK
VO
C3
Ceramic Capacitor
GRM31CR60G107ME39L
100 μF (4 V)
3216
MURATA
VO
C4
Ceramic Capacitor
GRM31CR60G107ME39L
100 μF (4 V)
3216
MURATA
VO
C5
Ceramic Capacitor
GRM31CR60G107ME39L
100 μF (4 V)
3216
MURATA
VO
C6-1
Ceramic Capacitor
GRM31CR60G107ME39L
100 μF (4 V)
3216
MURATA
VO
C6-2
Ceramic Capacitor
GRM31CR60G107ME39L
100 μF (4 V)
3216
MURATA
VO
C7
Ceramic Capacitor
C2012JB1C475K
4.7 μF (16 V)
2012
TDK
PVDD
C8
Ceramic Capacitor
C2012JB1C475K
4.7 μF (16 V)
2012
TDK
PVDD
C9
Ceramic Capacitor
C2012JB1C475K
4.7 μF (16 V)
2012
TDK
PVDD
C10
Ceramic Capacitor
C2012JB1C475K
4.7 μF (16 V)
2012
TDK
PVDD
C11
Ceramic Capacitor
C2012JB1C475K
4.7 μF (16 V)
2012
TDK
PVDD
C12
Ceramic Capacitor
C2012JB1C475K
4.7 μF (16 V)
2012
TDK
PVDD
(Continued)
DS04-27261-6E
47
MB39C308
(Continued)
Symbol
Part name
Model name
Specification
Package
Vendor
Remarks
C13
Ceramic Capacitor
C1608JB1E224K
0.22 μF (25 V)
1608
TDK
CB
C14
Ceramic Capacitor
C1608JB1E224K
0.22 μF (25 V)
1608
TDK
CB
C15
Ceramic Capacitor
C1608JB1H104K
0.1 μF (50 V)
1608
TDK
CB
C16
Ceramic Capacitor
C1608JB1H104K
0.1 μF (50 V)
1608
TDK
CB
C17
Ceramic Capacitor
C1608JB1H104K
0.1 μF (50 V)
1608
TDK
CB
C18
Ceramic Capacitor
C1608JB1H104K
0.1 μF (50 V)
1608
TDK
CB
C19
Ceramic Capacitor
C1608JB1C105K
1 μF (16 V)
1608
TDK
AVDD
C20
Ceramic Capacitor
C1608JB1C105K
1 μF (16 V)
1608
TDK
PVDD7
C21
Ceramic Capacitor
C1608JB1C105K
1 μF (16 V)
1608
TDK
VB
C22
Ceramic Capacitor
C1608JB1A475K
4.7 μF (10 V)
1608
TDK
VREF
L1
Inductor
RLF7030-3R3M4R1
3.3 μH (4.1 A)
SMD
TDK
⎯
L2
Inductor
MPLC0730L3R3
3.3 μH (5.7 A)
SMD
NEC
TOKIN
⎯
L3
Inductor
RLF7030-1R5N6R1
1.5 μH (6.1 A)
SMD
TDK
⎯
L4
Inductor
RLF7030-1R5N6R1
1.5 μH (6.1 A)
SMD
TDK
⎯
L5
Inductor
RLF7030-1R5N6R1
1.5 μH (6.1 A)
SMD
TDK
⎯
L6
Inductor
RLF7030-1R5N6R1
1.5 μH (6.1 A)
SMD
TDK
⎯
PIN
Wiring Terminal
WT-2-1
⎯
⎯
Mac-Eight
⎯
FML
SANYO
FAIRCHILD
SSM
TDK
MURATA
NEC TOKIN
Mac-Eight
48
: FUJITSU MICROELECTRONICS LIMITED
: SANYO Electric Co.,Ltd.
: Fairchild Semiconductor Japan Ltd.
: SUSUMU Co., Ltd
: TDK Corporation
: Murata Manufacturing Co., Ltd.
: NEC TOKIN Corporation
: Mac-Eight Co.,Ltd.
DS04-27261-6E
MB39C308
■ PRINTED CIRCUIT BOARD LAYOUT
Design of the PCB layout is important to make the suitable operation, suppressing noise or high efficiency ratio.
Refer to the evaluation board layout of MB39C308EVB-01 and consider the following guideline when designing
the layout of a circuit board.
1. Common items for each channel and peripheral components
• Ground and design for radiation of heat
At least, place the GND layer (PGND) in one of PCB internal layers. Place the through holes next to the GND
pin of IC and each component, and connect them to the GND layer with low impedance.
Place the AGND which is separated from the GND layer with flowing large current if possible. Connect the
bypass-capacitors of VREF and AVDD and the AGND pin of IC to the AGND. Connect AGND pin of IC to the
GND layer by one point connection as close as possible so as not to flow a large current to the AGND. Connect
GND pins of VB bypass-capacitor and the switching components to the GND layer directly.
Connect each thermal pin to the GND layer via the through hole so that the heat can be dissipated efficiency. It
is an ideal to place a through hole on a pad in the footprint of each thermal pin. Furthermore, it is also effective
to place the GND plane on the back side of the substrate of the trace mounted on IC.
• Bypass capacitors and boot strap capacitors
Place the bypass-capacitors connected to the VREF, AVDD, VB, PVDD7 pins next to each pin of IC. Furthermore,
connect the bypass-capacitors with the shortest path on surface layer to each pin. Place GND pins of bypasscapacitors connected to VB and PVDD7 pins to the PGND7 pin with the shortest path.
Place the bootstrap capacitors for each channel next to CBx and LXx pins.
• Example layout
MB39C308
CBx LXx
AVDD
Pad of IC
VREF
Through hole
Capacitor
VB
PVDD7
x : Number of each channel
• Feedback line
Place the feed back lines to FB pins for each channel away from switching components and lines, because the
feed back line is sensitive to noise.
DS04-27261-6E
49
MB39C308
• Printed circuit board design rule for PFBGA
■ SMD
■ NSMD
Solder-mask
opening
Solder-mask
opening
Pad pattern
SMD (solder-mask defined)
0.5 mm pitch
50
NSMD (non-solder mask defined)
Pad pattern
Solder-mask
opening
Pad pattern
Solder-mask
opening
φ0.325 to φ0.35
φ0.225 to φ0.25
φ0.225 to φ0.25
φ0.325 to φ0.35
DS04-27261-6E
MB39C308
2. External switching FET channel (CH1, CH2)
For the loop consisting of the input capacitor (CIN), high-side FET and low-side FET of each channel, take the
most care of making the current loop as tight as possible.
The input capacitor (CIN), high-side FET and low-side FET, inductor (L) and output capacitor (CO) should be
connected to the surface layer as much as possible using short and thick connections. In addition, avoid making
connections to theses components via the through hole.
Large transient current flows through the connections between the FET gate and OUT1H,OUT1L,OUT2H and
OUT2L pins. Make this lines as short and thick as possible (ex. 0.5 mm width).
PVDD1, PVDD2, LX1, LX2 pins sense the voltage between drain and source at high-side FET. Connect the
PVDD1 or PVDD2 pin to the drain pin of high-side FET directly. Avoid connecting to the other part on the line.
Connect the LX1 or LX2 pin to the source pin of high-side FET directly. Connect the bootstrap capacitor as in
the following graph and avoid connecting to the other part on the line. Furthermore, large transient current also
flows through the connection to the LX pin. Make the line as short and thick as possible (exp: PVDD1, PVDD2,
LX1, LX2 lines are 0.5 mm width).
When not connecting the PVDD and the LX pins to the drain or the source pin of the high-side FET as the layout
below, an error may occur in PWM/PFM switch current value and the OCP setting value because of the error
occurred in the current sense value.
• Example layout
MB39C308
CB1, CB2 pin
PVDD1, PVDD2 pin
LX1, LX2 pin
Connect the PVDD pin to
the drain pin of high-side
FET directly so as to sense
the drain voltage at highside FET. The line shouldn't
be connected to the other
parts.
Drain pad
High-side FET
Bootstrap
capacitor
Through hole
VIN
CIN
Source pad
PGND
Low-side FET
CO
Loop
L
VO
Connect the LX pin to
the source pin of highside FET directly so as to
sense the source voltage
at high-side FET.
The line shouldn't be
connected to the other
parts except the bootstrap capacitor.
To FB1,FB2 pin
DS04-27261-6E
51
MB39C308
3. Internal switching FET channel (CH3 to CH6)
Place the input capacitor (CIN) for each channel next to PVDDx and PGNDx pins as in the following graph.
The PVDDx, LXx, PGNDx pins, input capacitor (CIN), inductor (L) and output capacitor (CO) should be connected
to the surface layer as much as possible using short and thick connections. Avoid connecting these components
via the through hole.
• Example layout
MB39C308
VIN
PVDDx pin
CIN
LXx pin
L
PGNDx pin
PGND
x : Number of channel
52
CO
Through hole
VO
To FBx pin
DS04-27261-6E
MB39C308
■ USAGE PRECAUTION
1. Do not configure the IC over the maximum ratings
lf the lC is used over the maximum ratings, the LSl may be permanently damaged.
It is preferable for the device to normally operate within the recommended usage conditions. Usage outside of
these conditions can have a bad effect on the reliability of the LSI.
2. Use the devices within recommended operating conditions
The recommended operating conditions are under which the LSl is guaranteed to operate.
The electrical ratings are guaranteed when the device is used within the recommended operating conditions
and under the conditions stated for each item.
3. Printed circuit board ground lines should be set up with consideration for common
impedance
4. Take appropriate measures against static electricity
•
•
•
•
Containers for semiconductor materials should have anti-static protection or be made of conductive material.
After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
Work platforms, tools, and instruments should be properly grounded.
Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground.
5. Do not apply negative voltages
The use of negative voltages below –0.3 V may create parasitic transistors on LSI lines, which can cause
malfunctions.
6. Warnings when connecting the load
During DC/DC operation, if the output is connected by hard switching to a capacitance that greatly exceeds the
DC/DC output capacitance, the output voltage may oscillate and the protection function may be detected due
to the instant voltage drop. Take note of the following points.
• Connecting to the load capacitor
A P-ch FET is normally used as a load switch, and a gate resistor is inserted as shown below for the switch to
turn on gradually and to prevent rush current.
VO
Load
Capacitor
Load switch
DS04-27261-6E
53
MB39C308
7. Partial short circuits
Normally, in the event of a short circuit, such as the DC/DC output connecting to ground or low potential point,
output is stopped by the short circuit protection (SCP) function. Take care in the event of a partial short circuit,
because the output is not stopped by the short circuit protection (SCP) function. It is recommended that a fuse
be inserted into the input. If the short circuit conditions partially occur in several channels which contain the FET,
there is a possibility of smoke or fire.
[Partial short circuit : Refers to a short circuit condition where overcurrent flows but is not strong enough to
decrease the output voltage.]
8. Affects of insufficient power supply capacity on the SCP latch function
If the large current exceeding the current limit of input power supply flows through this device such as the case
of output short, power supply voltage may drop. On such occasion, if the power supply voltage drops below 5
V (Typ) before it detects SCP, DC/DC output is shutdown by the UVLO (Under Voltage Lock Out) function. After
the DC/DC output is shutdown, the input power supply recovers and SCP timer is reset, then the DC/DC converter
starts operating again. As the results, the DC/DC output does not stop at SCP latch function, and the following
four processes are repeated in the following order. In addition, it should be noted that under the above conditions,
some components of the DC/DC converter may be destroyed.
1. Power supply voltage drops as power supply current reaches its limit.
2. DC/DC output is shutdown by UVLO.
3. UVLO is released.
4. Output current and power supply current increase.
It is recommended that a fuse be inserted into the power line. If output wires are short-circuited in the multiple
channels which contain the FET, there is a possibility of smoke or fire.
Normal SCP operation
No SCP latch
output short
output short
UVLO
hysteresis
threshold
Power supply voltage
UVLO
DC/DC output voltage
DC/DC output current
time
counting
Power supply current
SCP latch
power supply
current limit
1
2 4 1...
3
54
DS04-27261-6E
MB39C308
■ ORDERING INFORMATION
Part number
MB39C308BGF
Package
Remarks
208-ball plastic PFBGA
(BGA-208P-M02)
■ EV BOARD ORDERING INFORMATION
EV board part No.
EV board version No.
Remarks
Board rev.1.0
PFBGA-208
MB39C308EVB-11
■ RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION
The LSI products of Fujitsu Microelectronics with “E1” are compliant with RoHS Directive , and has observed
the standard of lead, cadmium, mercury, hexavalent chromium, polybrominated biphenyls (PBB) , and polybrominated diphenyl ethers (PBDE) .
A product whose part number has trailing characters “E1” is RoHS compliant.
■ MARKING FORMAT (LEAD FREE VERSION)
J APAN
MB 39 C308
XXXX XXX
E1
Lead-free version
INDEX
DS04-27261-6E
55
MB39C308
■ LABELING SAMPLE (LEAD FREE VERSION)
Lead-free mark
JEDEC logo
JEITA logo
MB123456P - 789 - GE1
(3N) 1MB123456P-789-GE1
1000
(3N)2 1561190005 107210
G
Pb
QC PASS
PCS
1,000
MB123456P - 789 - GE1
2006/03/01
ASSEMBLED IN JAPAN
MB123456P - 789 - GE1
1/1
0605 - Z01A
1000
1561190005
The part number of a lead-free product has the trailing
characters “E1”.
56
DS04-27261-6E
MB39C308
■ MB39C308BGF
RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL
[Fujitsu Microelectronics Recommended Mounting Conditions]
Item
Condition
Mounting Method
IR (infrared reflow) , Manual soldering (partial heating method)
Mounting times
2 times
Storage period
Before opening
Please use it within two years after
Manufacture.
From opening to the 2nd
reflow
Less than 6 days
When the storage period after
opening was exceeded
Please processes within 6 days
after baking (125 °C, 24H)
5 °C to 30 °C, 70%RH or less (the lowest possible humidity)
Storage conditions
[Temperature Profile for FJ Standard IR Reflow]
(1) IR (infrared reflow)
M rank : 250 °C Max
250 °C
245 °C
Main heating
170 °C
to
190 °C
(b)
RT
(a)
(a) Temperature Increase gradient
(b) Preliminary heating
(c) Temperature Increase gradient
(d) Actual heating
(d’)
(e) Cooling
(c)
(d)
(e)
(d')
: Average 1 °C/s to 4 °C/s
: Temperature 170 °C to 190 °C, 60 s to 180 s
: Average 1 °C/s to 4 °C/s
: Temperature 250 °C Max; 245 °C or more, 10 s or less
: Temperature 230 °C or more, 40 s or less
or
Temperature 225 °C or more, 60 s or less
or
Temperature 220 °C or more, 80 s or less
: Natural cooling or forced cooling
Note : Temperature : the top of the package body
(2) Manual soldering (partial heating method)
Conditions : Temperature 400 °C Max
Times
: 5 s max/pin
DS04-27261-6E
57
MB39C308
■ PACKAGE DIMENSION
208-ball plastic PFBGA
Ball pitch
0.50 mm
Package width ×
package length
9.00 mm × 9.00 mm
Lead shape
Ball
Sealing method
Plastic mold
Mounting height
1.30 mm Max.
Weight
0.10 g
(BGA-208P-M02)
208-ball plastic PFBGA
(BGA-208P-M02)
9.00±0.10(.354±.004)
0.20(.008) S B
B
0.50(.020)
TYP
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
9.00±0.10
(.354±.004)
0.50(.020)
TYP
(INDEX AREA)
T RP NML K J HGF E DCBA
0.20(.008) S A
INDEX
208-ø0.30±0.10
(208-ø.012±.004)
ø0.05(.002)
M
S AB
S
0.10(.004) S
C
1.30(.051)
MAX
2007-2008 FUJITSU MICROELECTRONICS LIMITED B208002S-c-1-5
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest Package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
58
DS04-27261-6E
MB39C308
■ CONTENTS
-
page
DESCRIPTION .................................................................................................................................................... 1
FEATURES .......................................................................................................................................................... 1
APPLICATIONS .................................................................................................................................................. 2
PIN ASSIGNMENT ............................................................................................................................................. 3
PIN DESCRIPTIONS .......................................................................................................................................... 4
BLOCK DIAGRAM .............................................................................................................................................. 7
ABSOLUTE MAXIMUM RATINGS ................................................................................................................... 9
RECOMMENDED OPERATING CONDITIONS ............................................................................................ 10
ELECTRICAL CHARACTERISTICS ................................................................................................................ 12
CHANNEL CONTROL FUNCTION .................................................................................................................. 19
POWER GOOD FUNCTION ............................................................................................................................. 19
PROTECTION ..................................................................................................................................................... 20
DESCRIPTION OF SOFT-START AND SOFT-STOP OPERATION ......................................................... 21
PRESET FUNCTION OF CH3/CH4/CH6 OUTPUT VOLTAGE .................................................................. 23
TYPICAL CHARACTERISTICS ........................................................................................................................ 24
NOTES FOR UNCONNECTED PINS ............................................................................................................. 26
APPLICATION NOTE ......................................................................................................................................... 30
REFERENCE DATA ........................................................................................................................................... 37
TYPICAL APPLICATION CIRCUIT .................................................................................................................. 45
PARTS LIST ......................................................................................................................................................... 47
PRINTED CIRCUIT BOARD LAYOUT ............................................................................................................ 49
USAGE PRECAUTION ...................................................................................................................................... 53
ORDERING INFORMATION ............................................................................................................................. 55
EV BOARD ORDERING INFORMATION ....................................................................................................... 55
RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION .................................................. 55
MARKING FORMAT (LEAD FREE VERSION) .............................................................................................. 55
LABELING SAMPLE (LEAD FREE VERSION) ............................................................................................. 56
MB39C308BGF RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL .................... 57
PACKAGE DIMENSION .................................................................................................................................... 58
DS04-27261-6E
59
MB39C308
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3329
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department