TI SN65LVDS302ZQE

SN65LVDS302
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SLLS733A – JUNE 2006 – REVISED AUGUST 2006
PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
FEATURES
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•
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Serial Interface Technology
Compatible with FlatLink™3G such as
SN65LVDS301
Supports Video Interfaces up to 24-bit RGB
Data and 3 Control Bits Received over 1, 2 or
3 SubLVDS Differential Lines
SubLVDS Differential Voltage Levels
Up to 1.755 Gbps Data Throughput
Three Operating Modes to Conserve Power
– Active mode QVGA - 17 mW
– Typical Shutdown - 0.7 µW
– Typical Standby Mode - 27 µW Typical
Bus-Swap Function for PCB-Layout Flexibility
ESD Rating > 4 kV (HBM)
Pixel Clock Range of 4 MHz–65 MHz
Failsafe on all CMOS Inputs
Packaged in 5 mm x 5 mm MicroStar Junior
µBGA® with 0,5 mm Ball Pitch
Very low EMI meets SAE J1752/3 'Kh'-spec
APPLICATIONS
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Small Low-Emission Interface between
Graphics Controller and LCD Display
Mobile Phones & Smart Phones
Portable Multimedia Players
DESCRIPTION
The
SN65LVDS302
receiver
de-serializes
FlatLink™3G compliant serial input data to 27
parallel data outputs. The SN65LVDS302 receiver
contains one shift register to load 30 bits from 1, 2 or
3 serial inputs and latches the 24 pixel bits and 3
control bits out to the parallel CMOS outputs after
checking the parity bit. If the parity check confirms
correct parity, the Channel Parity Error (CPE) output
remains low. If a parity error is detected, the CPE
output generates a high pulse while the data output
bus disregards the newly-received pixel. Instead, the
last data word is held on the output bus for another
clock cycle.
The serial data and clock are received via Sub
Low-Voltage Differential Signalling (SubLVDS) lines.
The SN65LVDS302 supports three operating power
modes (Shutdown, Standby, and Active) to conserve
power.
When receiving, the PLL locks to the incoming clock
CLK and generates an internal high-speed clock at
the line rate of the data lines. The data is serially
loaded into a shift register using the internal
high-speed clock. The deserialized data is presented
on the parallel output bus with a recreation of the
Pixel clock PCLK generated from the internal
high-speed clock. If no input CLK signal is present,
the output bus is held static with the PCLK and DE
held low, while all other parallel outputs are pulled
high.
The parallel (CMOS) output bus offers a bus-swap
feature. The SWAP control pin controls the output
pin order of the output pixel data to be either R[7:0].
G[7:0], B[7:0], VS, HS, DE or B[0:7], G[0:7], R[0:7],
VS, HS, DE. This gives a PCB designer the flexibility
to better match the bus to the LCD driver pinout or to
put the receiver device on the top side or the bottom
side of the PCB. The F/S control input selects
between a slow CMOS bus output rise time for best
EMI and power consumption and a fast CMOS
output for increased speed or higher load designs.
Flatlinkä3G
LCD
Driver
LVDS302
CLK
DATA
LVDS301
1
2
3
4
5
6
7
8
9
*
0
#
Application
Processor
with
RGB
Video
Interface
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments.
µBGA is a registered trademark of Tessera, Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
SN65LVDS302
www.ti.com
SLLS733A – JUNE 2006 – REVISED AUGUST 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
Two Link Select lines LS0 and LS1 select whether 1, 2, or 3 serial links are used. The RXEN input may be used
to put the SN65LVDS302 in a Shutdown mode. The SN65LVDS302 enters an active Standby mode if the
common mode voltage of the CLK input becomes shifted to VDDLVDS (e.g., transmitter releases CLK output
into high-impedance). This minimizes power consumption without the need of switching an external control pin.
The SN65LVDS302 is characterized for operation over ambient air temperatures of –40°C to 85°C. All CMOS
and SubLVDS signals are 2-V tolerant with VDD=0 V. This feature allows signal powerup before VCC is
stabilized.
FUNCTIONAL BLOCK DIAGRAM
VDDLVDS
RBBDC
CPE
iPCLK
D0+
50
SWAP
Parity
Check
SubLVDS
F/S
AND
50
D0-
1
50
SubLVDS
50
D1VDDLVDS
RBBDC
D2+
50
RGB=1
HS=VS=1
DE=0
D2VDDLVDS
8
0
0
1
SubLVDS
50
8
Output Buffer
D1+
27-bit parallel
Register
Serial-to-parallel conversion
VDDLVDS
RBBDC
8
R[0:7]
G[0:7]
B[0:7]
HS
VS
standby or
pwr down
DE
RBBDC
CLK+
x10, x15, or x30
50
PLL
multiplier
SubLVDS
50
CLK-
x1
iPCLK
0
PCLK
1
standby
CPOL
Vthstby
RXEN
LS0
Glitch
Suppression
Control
LS1
2
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PINOUT – TOP VIEW
PINOUT - TOP VIEW
1
2
3
4
5
6
7
8
9
A
GND
R 6/B 1
R 4/B 3
R 2/B 5
R 0/B 7
G 6/G 1
G 4/G 3
G 2/G 5
GND
R 7/B 0
R 5/B 2
R 3/B 4
R 1/B 6
G 7/G 0
G 5/G 2
G 3/G 4
G 1/G 6
G 0/G 7
LS 0
VDD
VDD
GND
VDD
GND
B 7/R 0
B 6/R 1
D 2+
LS 1
GND
GND
GND
GND
VDD
B 5 /R 2
D 2-
GND PLLD
GND
GND
GND
GND
VDD
B 3/R 4
B 2/R 5
GND
GND
GND
GND
VDD
B 1/R 6
B 0/R 7
GND
GND
VDD
F /S
PCLK
GND
VS
HS
RXEN
DE
CPE
B
C
D
B 4 /R 3
E
F
D 1+
V DDPLLD
G
D 1-
GND LVDS
GND
GND
H
CPOL
V DDLVDS V DDPLLA GND PLLA V DDLVDS GND LVDS
J
GND LVDS SWAP
CLK +
CLK -
D 0+
D 0-
RGB Output pin assignment based on SWAP pin setting:
SWAP
= 0 / SWAP
=1
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PINOUT – TOP VIEW (continued)
SWAP PIN FUNCTIONALITY
The SWAP pin allows the pcb designer to reverse the RGB bus, minimizing potential signal crossovers due to
signal routing. The two drawings beneath show the RGB signal pin assignment based on the SWAP-pin setting.
1
2
3
4
5
6
7
8
R2
R0
G6
G4
G2
9
A
R4
B
3
4
5
6
7
8
R5
R3
R1
G7
G5
G3
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
C
B1
B3
B5
B7
G1
G3
G5
B0
B2
B4
B6
G0
G2
G4
G6
G7
R0
R1
R2
R3
R4
R5
R6
R7
C
D
D
SN65LVDS302
Top View
E
F
G
SN65LVDS302
Top View
G
PCLK
H
PCLK
H
VS
J
HS
VS
J
DE
Figure 1. Pinout With SWAP PIN = GND
4
9
B
R7
F
2
A
R6
E
1
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DE
Figure 2. Pinout With SWAP PIN = VDD
HS
SN65LVDS302
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SLLS733A – JUNE 2006 – REVISED AUGUST 2006
PINOUT – TOP VIEW (continued)
Table 1. Pin Description
PIN
SWAP
SIGNAL
PIN
A1
–
GND
C1
L
R6
C2
H
B1
C3
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
SWAP .
SIGNAL
PIN
SWAP
–
LS0
F1
–
D1+
–
VDD
F2
–
VDDPLLD
F3
–
GND
unpopulated
SIGNAL
L
R4
C4
–
VDD
F4
–
GND
H
B3
C5
–
GND
F5
–
GND
L
R2
C6
–
VDD
F6
–
GND
H
B5
C7
–
GND
F7
–
VDD
L
R0
L
B7
H
B7
H
R0
L
G6
L
B6
H
G1
H
R1
H
R7
L
G4
D1
–
D2+
G1
–
D1–
H
G3
D2
–
LS1
G2
–
GNDLVDS
C8
C9
F8
F9
L
B1
H
R6
L
B0
L
G2
D3
–
GND
G3
–
GND
H
G5
D4
–
GND
G4
–
GND
–
GND
D5
–
GND
G5
–
GND
L
R7
D6
–
GND
G6
–
GND
H
B0
D7
–
VDD
G7
–
VDD
L
R5
L
B5
G8
–
F/S
H
B2
H
R2
G9
–
PCLK
L
R3
H
B4
L
R1
H
L
H
D8
L
B4
H1
–
CPOL
H
R3
H2
–
VDDLVDS
E1
–
D2–
H3
–
VDDPLLA
B6
E2
–
GNDPLLD
H4
–
GNDPLLA
G7
E3
–
GND
H5
–
VDDLVDS
G0
E4
–
GND
H6
–
GNDLVDS
GND
D9
L
G5
E5
–
GND
H7
–
H
G2
E6
–
GND
H8
–
VS
L
G3
E7
–
VDD
H9
–
HS
H
G4
L
B3
J1
–
GNDLVDS
H
R4
J2
–
SWAP
L
B2
J3
–
CLK+
H
R5
J4
–
CLK–
J5
–
D0+
J6
–
D0–
J7
–
RXEN
J8
–
DE
J9
–
CPE
L
G1
H
G6
L
G0
H
G7
E8
E9
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SN65LVDS302
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TERMINAL FUNCTIONS
NAME
I/O
DESCRIPTION
D0+, D0–
SubLVDS Data Link (active during normal operation)
D1+, D1–
SubLVDS Data Link (active during normal operation when LS0 = high and LS1 = low, or LS0 = low and
LS1=high; high impedance if LS0 = LS1 = low); input can be left open if unused
SubLVDS in
D2+, D2–
SubLVDS Data Link (active during normal operation when LS0 = low and LS1 = high, high-impedance
when LS1 = low); input can be left open if unused
CLK+, CLK–
SubLVDS Input Pixel Clock; Polarity is fixed.
R0–R7
Red Pixel Data (8); pin assignment depends on SWAP pin setting
G0–G7
Green Pixel Data (8); pin assignment depends on SWAP pin setting
B0–B7
HS
Blue Pixel Data (8); pin assignment depends on SWAP pin setting
CMOS OUT
Horizontal Sync
VS
Vertical Sync
DE
Data Enable
PCLK
Output Pixel Clock; rising or falling clock polarity is selected by control input CPOL
LS0, LS1
Link Select (Determines active SubLVDS Data Links and PLL Range) See Table 2
Disables the CMOS Drivers and Turns Off the PLL, putting device in shutdown mode
1 – Reciver enabled
0 – Receiver disabled (Shutdown)
Note: RXEN input incorporates glitch suppression logic to avoid unwanted switching. The input must be
pulled low for longer than 10µs continuously to force the receiver to enter Shutdown. The input must be
pulled high for at least 10µs continuously to activate the receiver. An input pulse shorter than 5us will
be interpreted as glitch and becomes ignored. At power up, the receiver is enabled immediately if
RXEN=H and disabled if RXEN=L
RXEN
CMOS In
CPOL
Output Clock Polarity Selection
0 – rising edge clocking
1 – falling edge clocking
Bus Swap swaps the bus pins to allow device placement on top or bottom of PCB. See pinout drawing
for pin assignments.
SWAP
0 – data output from R7...B0
1 – data output from B0...R7
CMOS bus rise time select
F/S
CPE
1 – fast output rise time
0 – slow output rise time
CMOS Out
Channel Parity Error
This output indicates the detection of a parity error by generating an output high-pulse for half of a
PCLK clock cycle; this allows counting parity errors with a simple counter.
0 – no error
high-pulse – bit error detected
VDD
Supply Voltage
GND
Supply Ground
VDDLVDS
SubLVDS I/O supply Voltage
GNDLVDS
VDDPLLA
6
Power Supply
SubLVDS Ground
PLL analog supply Voltage
GNDPLLA
PLL analog GND
VDDPLLD
PLL digital supply Voltage
GNDPLLD
PLL digital GND
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FUNCTIONAL DESCRIPTION
Deserialization Modes
The SN65LVDS302 receiver has three modes of operation controlled by link-select pins LS0 and LS1. Table 2
shows the deserializer modes of operation.
Table 2. Logic Table: Link Select Operating Modes
LS1
LS0
Mode of Operation
Data Links Status
0
0
1ChM
1-channel mode (30-bit serialization rate)
D0 active;
D1, D2 disabled
0
1
2ChM
2-channel mode (15-bit serialization rate)
D0, D1 active;
D2 disabled
1
0
3ChM
3-channel mode (10-bit serialization rate)
D0, D1, D2 active
1
1
Reserved
Reserved
1-Channel Mode
While LS0 and LS1 are held low, the SN65LVDS302 receives payload data over a single SubLVDS data pair,
D0. The PLL locks to the SubLVDS clock input and internally multiplies the clock by a factor of 30. The internal
high speed clock is used to shift in the data payload on D0 and to deserialize 30 bits of data. Figure 3 illustrates
the timing and the mapping of the data payload into the 30-bit frame. The internal high speed clock is divided by
a factor of 30 to recreate the pixel clock and the data payload with the pixel clock is presented on the output
bus. The reserved bits and parity bit are not output. While in this mode, the PLL can lock to a clock that is in the
range of 4 MHz through 15 MHz. This mode is intended for smaller video display formats that do not need the
full bandwidth capabilities of the SN65LVDS302.
CLK CLK +
D0 +/- CHANNEL res res CP R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 VS HS DE res res CP R7 R6
Figure 3. Data and Clock Input in 1-ChM (LS0 and LS1 = low)
2-Channel Mode
While LS0 is held high and LS1 is held low, the SN65LVDS302 receives payload data over two SubLVDS data
pairs, D0 and D1. The PLL locks to the SubLVDS clock input and internally multiplies the clock by a factor of 15.
The internal high speed clock is used to shift in the data payload on D0 and D1 and to deserialize 15 bits of data
from each pair. Figure 4 illustrates the timing and the mapping of the data payload into the 30-bit frame. The
internal high speed clock is divided by a factor of 15 to recreate the pixel clock, and the data payload with pixel
clock is presented on the output bus. The reserved bits and parity bit are not output. While in this mode the PLL
can lock to a clock that is in the range of 8 MHz through 30 MHz.
CLK CLK +
D0 +/- CHANNEL CP R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 VS res CP R7 R6
D1 +/- CHANNEL res G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 HS DE res G3 G2
Figure 4. Data and Clock Output in 3-ChM (LS0 = high; LS1 = low)
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3-Channel Mode
While LS0 is held low and LS1 is held high the SN65LVDS302 receives payload data over three SubLVDS data
pairs: D0, D1, and D2. The PLL locks to the SubLVDS clock input and internally multiplies the clock by a factor
of 10. The internal high speed clock is used to shift in the data payload on D0, D1, and D2, and to deserialize 10
bits of data from each pair. Figure 5 illustrates the timing and the mapping of the data payload into the 30-bit
frame. While in this mode the PLL can lock to a clock that is in the range of 20 MHz through 65 MHz.
CLK CLK +
D0 +/- CHANNEL CP R7 R6 R5 R4 R3 R2 R1 R0 VS CP R7 R6
D1 +/- CHANNEL res G7 G6 G5 G4 G3 G2 G1 G0 HS res G7 G6
D2 +/- CHANNEL res B7 B6 B5 B4 B3 B2 B1 B0 DE res B7 B6
Figure 5. Data and Clock Output in 3-ChM (LS0 = low; LS1 = high)
POWERDOWN MODES
The SN65LVDS302 Receiver has two powerdown modes to facilitate efficient power management.
SHUTDOWN MODE
A low input signal on the RXEN pin puts the SN65LVDS302 into Shutdown mode. This turns off most of the
receiver circuitry including the SubLVDS receivers, PLL, and deserializers. The subLVDS differential-input
resistance remains 100 Ω, while any input signal is ignored. All outputs will hold a static output pattern:
R[0:7]=G[0:7]=B[0:7]=VS=HS=high; DE=PCLK=low.
The current draw in Shutdown mode will be nearly zero if the subLVDS inputs are left open or pulled high.
STANDBY MODE
The SN65LVDS302 will enter the Standby mode when the SN65LVDS302 is not in Shutdown mode but the
SubLVDS clock-input common-mode voltage is above 0.9 × VDDLVDS. The CLK input incorporates a pull-up
circuit to shift the SubLVDS clock-input common-mode voltage to VDDLVDS in the absence of an input signal. All
circuitry except the SubLVDS clock-input Standby monitor is shut down. The SN65LVDS302 will also enter
Standby mode when the input clock frequency on the CLK input is less than 500 kHz. The SubLVDS input
resistance remains 100 Ω while any input signal on the data inputs D0, D1, and D2 becomes ignored. All
outputs will hold a static output pattern:
R[0:7]=G[0:7]=B[0:7]=VS=HS=high; DE=PCLK=low.
The current drawn in Standby mode will be very low.
ACTIVE MODES
A high input signal on RXEN combined with a CLK input signal switching faster than 3 MHz and VICM smaller
than 1.3 V force the SN65LVDS302 into Active mode. Current consumption in active mode depends on
operating frequency and the number of data transitions in the data payload. CLK-input frequencies between 3
MHz and 4 MHz activate the device but proper PLL functionality is not secured. It is not recommended to
operate the SN65LVDS302 in active mode at CLK frequencies below 4 MHz.
ACQUIRE MODE (PLL Approaches Lock)
When the SN65LVDS302 is enabled and a SubLVDS clock input present, the PLL will pursue lock to the input
clock. While the PLL pursues lock the output data bus will hold a static output pattern:
R[0:7]=G[0:7]=B[0:7]=VS=HS=high; DE=PCLK=low.
8
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For proper device operation, the pixel clock frequency must fall within the valid fPCLK range specified under
recommended operating conditions. If the pixel clock frequency is larger than 3 MHz but smaller than fPCLK(min),
the SN65LVDS302 PLL is enabled. Under such conditions, it is possible for the PLL to lock temporarily to the
pixel clock, causing the PLL monitor to release the device into active receive mode. If this happens, the PLL
may or may not be properly locked to the pixel clock input, potentially causing data errors, frequency oscillation,
and PLL deadlock (loss of VCO oscillation).
RECEIVE MODE
After the PLL achieves lock the device enters the normal receive mode. The output data bus presents the
de-serialized data. The PCLK output pin outputs the recovered pixel clock.
PARITY ERROR DETECTION AND HANDLING
The SN65LVDS302 receiver performs error checking on the basis of a parity bit that is transmitted across the
subLVDS interface from the transmitting device. Once the SN65LVDS302 detects the presence of the clock and
the PLL has locked onto PCLK, then the parity is checked. Parity-error detection ensures detection of all single
bit errors in one pixel and 50% of all multi-bit errors.
The parity bit covers the 27 bit data payload consisting of 24 bits of pixel data plus VS, HS, and DE. Odd Parity
bit signalling is used. The parity error is output on the CPE pin. If the sum of the 27 data bits and the parity bit
result in an odd number, the receive data are assumed to be valid. The CPE output will be held low. If the sum
equals an even number, parity error is declared. The CPE output will indicate high for half a PCLK period. The
CPE output will be set with the data bit transition and cleared after 1/2 the data bit time. This allows counting
every detected parity error with a simple counter connected to CPE.
A Parity error is indicated by a
high pulse on CPE; the width of
the pulse is 1/2 the length of a
PCLK cycle
Also if there is a parity error detected then the
data on that PCLK cycle is not output. Instead,
the last valid data from a previous PCLK cycle
is repeated on the output bus. This is to prevent
any bit error that may occur on the LVDS link
from causing perturbations in VS, HS, or DE that
may be visually disruptive to a display.
CPE
R[0:7], G[0:7],
B[0:7], HS, VS, DE
PCLK
The reserved bits are not covered in the parity
calculations.
(CPOL=0)
When a parity error is
detected, the receiver outputs
the previous pixel on the bus
Hence no data transitions
occur.
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STATUS DETECT AND OPERATING MODES FLOW DIAGRAM
The SN65LVDS302 switches between the power saving and active modes in the following way:
Power Up
RXEN = 1
CLK Input Inactive
RXEN Low
for > 10 ms
Power Up
RXEN = 0
ShutDown
Mode
Standby
Mode
RXEN High
for > 10 ms
VICM(CLK) > 0.9 VDDLVDS
RXEN Low
for > 10 ms
VICM(CLK) > 0.9 VDDLVDS
or fCLK < 500 kHz
CLK Input Active
Power Up
RXEN = 1
CLK Active
RXEN Low
for > 10 ms
Receive
Mode
PLL Achieved Lock
Acquire
Mode
Table 3. Status Detect and Operating Modes Descriptions
Mode
Characteristics
Conditions
(1) (2)
Shutdown Mode
Least amount of power consumption (most circuitry turned
off); All outputs held static:
R[0:7]=G[0:7]=B[0:7]=VS=HS=high DE=PCLK=low;
RXEN is set low for longer than 10µs
Standby Mode
Low power consumption (Standby monitor circuit active;
PLL is shutdown to conserve power);
All outputs held static:
R[0:7]=G[0:7]=B[0:7]=VS=HS=high DE=PCLK=low;
RXEN is high for longer than 10 µs, and both CLK input
common-mode VICM(CLK) above 0.9×VDDLVDS, or CLK
input floating (2)
Acquire Mode
PLL pursues lock; All outputs held static:
R[0:7]=G[0:7]=B[0:7]=VS=HS=high DE=PCLK=low;
RXEN is high; CLK input monitor detected clock input
common mode and woke up receiver out of Standby
mode
Transmit Mode
Data transfer (normal operation);
receiver deserializes data and provides data on parallel
output
RXEN is high and PLL is locked to incoming clock
(1)
(2)
10
In Shutdown Mode, all SN65LVDS302 internal switching circuits (e.g., PLL, serializer, etc.) are turned off to minimize power
consumption. The input stage of any input pin remains active.
Leaving CMOS control inputs unconnected can cause random noise to toggle the input stage and potentially harm the device. All CMOS
inputs must be tied to a valid logic level VIL or VIH during Shutdown or Standby Mode. Exceptions are the subLVDS inputs CLK and Dx,
which can be left unconnected while not in use.
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Table 4. Operating Mode Transitions
MODE TRANSITION
USE CASE
Shutdown → Standby Drive TXEN high to enable
receiver
TRANSITION SPECIFICS
1. RXEN high > 10 µs
2. Receiver enters standby mode
a. R[0:7]=G[0:7]=B[0:7]=VS=HS remain high and DE=PCLK low
b. Receiver activates clock input monitor
Standby → Acquire
Receiver activity detected
1. CLK input monitor detects clock input activity
2. Outputs remain static
3. PLL circuit is enabled
Acquire → Receive
Link is ready to receive
data
1. PLL is active and approaches lock
2. PLL achieves lock within twakeup
3. D1, D2, and/or D3 become active depending on LS0 and LS1 selection
4. First Data word was recovered
5. Parallel output bus turns on switching from static output pattern to output first
valid data word
Receive → Standby
Receive/Standby →
Shutdown
Transmitter requested to
enter Standby mode by
input common mode
voltage VICM > 0.9 VDDLVDS
(e.g. transmitter output
clock stops or enters
high-impedance state)
1. Receiver disables outputs within tsleep
Turn off Receiver
1. RXEN pulled low for > tpwrdn
2. RX Input monitor detects VICM > 0.9 VDDLVDS within tsleep
3. R[0:7]=G[0:7]=B[0:7]=VS=HS transition to high and DE=PCLK to low on next
falling PLL clock edge
4. PLL shuts down. Clock activity input monitor remains active
2. Receiver switches all outputs into high-impedance state
3. Most IC circuitry is shut down for least power consumption
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ABSOLUTE MAXIMUM RATINGS (1)
Supply voltage range, VDD
(2),
VDDPLLA, VDDPLLD, VDDLVDS
Voltage range at any input When VDDx > 0 V
or output terminal
When VDDx ≤ 0 V
V
±4
Charged-Device Mode (4) (all Pins)
±1500
Machine Model (5) (all pins)
±200
V
kV
V
See Dissipation Rating Table
±5
Ouput current, IO
(2)
(3)
(4)
(5)
–0.3 to 2.175
–0.5 to VDD + 2.175
Continuous power dissipation
(1)
UNIT
–0.5 to 2.175
Human Body Model (3) (all Pins)
Electrostatic discharge
VALUE
mA
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the GND terminals
In accordance with JEDEC Standard 22, Test Method A114-B
In accordance with JEDEC Standard 22, Test Method C101
In accordance with JEDEC Standard 22, Test Method A115-A
DISSIPATION RATINGS
(1)
(2)
PACKAGE
CIRCUIT
BOARD MODEL
TA < 25°C
DERATING FACTOR (1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
ZQE
Low-K (2)
592 mW
7.407 mW/°C
148 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air
flow.
In accordance with the Low-K thermal metric definitions of EIA/JESD51-2.
DEVICE POWER DISSIPATION
PARAMETER
PD
Device Power
Dissipation
TEST CONDITIONS
VDDx = 1.8 V, TA = 25°C, all outputs terminated with 10 pF
VDDx = 1.95 V, TA = –40°C, all outputs terminated with 10 pF
12
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TYP
fCLK at 4 MHz
16.8
fCLK at 65 MHz
64.7
MAX
UNIT
mW
fCLK at 4 MHz
27.4
fCLK at 65 MHz
128.8
mW
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RECOMMENDED OPERATING CONDITIONS (1)
VDD
VDDPLLA
VDDPLLD
VDDLVDS
Supply voltages
MIN
TYP
MAX
UNIT
1.65
1.8
1.95
V
Test set-up see Figure 7
VDDn(PP)
Supply voltage noise magnitude
50MHz (all supplies)
TA
Operating free-air temperature
fCLK≤ 50MHz; f(noise) = 1Hz to 2 GHz
100
fCLK > 50MHz; f(noise) = 1Hz to 1MHz
100
fCLK > 50 MHz; f(noise) > 1MHz
mV
40
–40
85
1-Channel transmit mode, see Figure 3
4
15
2-Channel transmit mode, see Figure 4
8
30
3-Channel transmit mode, see Figure 5
20
65
°C
CLK+ and CLK–
fCLK±
Input Pixel clock frequency
Standby mode (2), See Figure 16
tDUTCLK
CLK Input Duty Cycle
MHz
500
kHz
35
65
%
70
200
0.6
1.2
D0+, D0–, D1+, D1–, D2+, D2-, CLK+, and CLK–
|VID|
Magnitude of differential input
voltage
|VD0+-VD0-|, |VD1+-VD1-|, |VD2+-VD2-|,
|VCLK+-VCLK-| during normal operation
VICM
Input Voltage Common Mode Range
Receive or Acquire mode
Stand-by mode
∆VICM
Input Voltage Common Mode
Variation between all SubLVDS
inputs
VICM(n)– VICM(m) with n=D0, D1, D2, or CLK
and m=D0, D1, D2, or CLK
Differential Input Voltage Amplitude
Variation between all SubLVDS
inputs
VID(n)– VID(m) with n=D0, D1, D2, or CLK
and m=D0, D1, D2, or CLK
tR/F
Input Rise and Fall Time
RXEN at VDD; see figure 6-2
∆ tR/F
Input Rise or Fall Time mismatch
between all SubLVDS inputs
tR(n)– tR(m) and tF(n)– tF(m) with n=D0, D1,
D2, or CLK and m=D0, D1, D2, or CLK
∆VID
mV
V
0.9 × VDDLVDS
–100
100
mV
–10
10
%
800
–100
100
0.7×VDD
VDD
0
0.3×VDD
ps
ps
LS0, LS1, CPOL, SWAP, RXEN, F/S
VICMOSH
High-level input voltage
VICMOSL
Low-level input voltage
tinRXEN
RXEN input pulse duration
V
V
µs
10
R[7:0], G[7:0], B[7:0], VS, HS, PCLK, CPE
CL
(1)
(2)
Output load capacitance
10
pF
Unused single-ended inputs must be held high or low to prevent them from floating.
PCLK input frequencies lower than 500 kHz force the SN65LVDS302 into standby mode. Input frequencies between 500 kHz and 3
MHz may or may not activate the SN65LVDS302. Input frequencies beyond 3 MHz activate the SN65LVDS302. Input frequencies
between 500 kHz and 4 MHz are not recommended, and can cause PLL malfunction.
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DEVICE ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
Alternating 1010 Test pattern (see Table 9); All CMOS outputs
terminated with 10pF; F/S and RXEN at VDD; VIH=VDD, VIL=0 V;
VDD=VDDPLLA=VDDPLLD=VDDLVDS;
1ChM
Typical power test pattern (see Table 6); VID=70 mV, All CMOS
outputs terminated with 10pF; F/S at GND and RXEN at VDD; VIH=VDD,
VIL=0 V; VDD=VDDPLLA=VDDPLLD=VDDLVDS;
Alternating 1010 Test pattern (seeTable 9); All CMOS outputs
terminated with 10pF; F/S and RXEN at VDD; VIH=VDD, VIL=0 V;
VDD=VDDPLLA=VDDPLLD=VDDLVDS;
2ChM
IDD
RMS Supply
Current
3ChM
Typical power test pattern (see Table 7); VID=70 mV, All CMOS
outputs terminated with 10pF; F/S at GND and RXEN at VDD; VIH=VDD,
VIL=0 V; VDD=VDDPLLA=VDDPLLD=VDDLVDS;
14
MAX
fPCLK = 4 MHz
9.8
14.0
fPCLK = 6 MHz
11.7
15.9
fPCLK = 15 MHz
19.3
25.0
fPCLK = 4 MHz
4.7
MIN
fPCLK = 6 MHz
6.0
fPCLK = 15 MHz
13.2
fPCLK = 8 MHz
14.3
19.4
fPCLK = 22 MHz
25.0
33.0
fPCLK = 30 MHz
26.8
37.0
6.4
fPCLK = 22 MHz
13.7
fPCLK = 30 MHz
18.3
Alternating 1010 Test pattern (see Table 9); All CMOS outputs
terminated with 10pF; F/S and RXEN at VDD; VIH=VDD, VIL=0 V;
VDD =VDDPLLA=VDDPLLD=VDDLVDS;
fPCLK = 20 MHz
17.1
27.0
fPCLK = 65 MHz
60.8
68.0
Typical power test pattern (see Table 8); VID=70 mV, All CMOS
outputs terminated with 10pF; F/S at GND and RXEN at VDD; VIH=VDD,
VIL=0 V;
VDD =VDDPLLA=VDDPLLD=VDDLVDS;
fPCLK = 20 MHz
8.6
All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
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fPCLK = 65 MHz
UNIT
mA
mA
fPCLK = 8 MHz
CLK and D[0:2] inputs are left open; All control inputs held static high or low;
All CMOS outputs terminated with 10pF;
VIH=VDD, VIL=0V; VDD=VDDPLLA=VDDPLLD=VDDLVDS
(1)
TYP (1)
TEST CONDITIONS
mA
mA
mA
mA
22.2
Standby mode;
RXEN=VIH
15
100
µA
Shutdown
mode;
RXEN=VIL
0.4
10
µA
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INPUT ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
D0+, D0–, D1+, D1–, D2+, D2–, CLK+, and CLK–
Vthstby
Input voltage common mode threshold to RXEN at VDD
switch between receive/acquire mode and
standby mode
1.3
VTHL
Low-level differential input voltage
threshold
–40
VTHH
High-level differential input voltage
threshold
II+, II–
Input leakage current
VDD=1.95 V; VI+ = VI–;
VI = 0.4 V and VI = 1.5 V
IIOFF
Power-off input current
VDD=GND; VI = 1.5V
RID
Differential input termination resistor value
CIN
Input capacitance
Measured between input terminal
and GND
∆CIN
Input capacitance variation
Within one signal pair
Between all signals
VD0+–VD0–, VD1+–VD1–, VD2+–VD2–,
VCLK+–VCLK-
0.9×VDDLVDS
V
mV
40
78
RBBDC Pull-up resistor for standby detection
100
75
µA
–75
µA
122
Ω
1
21
mV
pF
30
0.2
1
pF
39
kΩ
LS0, LS1, CPOL, SWAP, RXEN, F/S
VIK
Input clamp voltage
IICMOS Input current (2)
II= –18mA, VDD=VDD(min)
-1.2
V
0V≤VDD≤1.95V; VI=GND or
VI=1.95V
100
nA
CIN
Input capacitance
IIH
High-level input current
VIN = 0.7 × VDD
-200
200
IIL
Low-level input current
VIN = 0.3 × VDD
–200
200
VIH
High-level input voltage
0.7×VDD
VDD
VIL
Low-level input voltage
0
0.3×VDD
(1)
(2)
2
pF
nA
V
All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
Do not leave any CMOS Input unconnected or floating to minimize leakage currents. Every input must be connected to a valid logic level
VIH or VOL while power is supplied to VDD.
OUTPUT ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.8×VDD
VDD
V
0
0.2×VDD
V
R[0:7], G[0:7], B[0:7], VS, HS, PCLK, CPE
1-ChM, F/S=L, IOH=–250 µA
VOH
High-level output current
2-or 3-ChM, F/S=L, IOH=–500 µA
1-ChM, F/S=H, IOH=–500 µA
2- or 3-ChM, F/S=H, IOH=–2.0 mA
1-ChM, F/S=L, IOL=250 µA
VOL
Low-level output current
IOH
High-level output current
2- or 3-ChM, F/S=L, IOL=500 µA
1-ChM, F/S=H, IOL=500 µA
2- or 3-ChM, F/S=H, IOL=2.0 mA
1-ChM, F/S=L
2- or 3-ChM, F/S=L; 1-ChM, F/S=H
2- or 3-ChM, F/S=H
IOL
Low-level output current
1-ChM, F/S=L
2- or 3-ChM, F/S=L; 1-ChM, F/S=H
2- or 3-ChM, F/S=H
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–250
–500
–2000
250
µA
500
2000
15
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SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
800
ps
D0+, D0–, D1+, D1–, D2+, D2–, CLK+, and CLK–
tR/F
Input rise and fall time
RXEN at VDD; see figure 6-2
∆tR/F
Input rise or fall time
mismatch between all
SubLVDS inputs
tR(n)– tR(m) and tF(n)- tF(m) with n=D0, D1, D2, or CLK
and m=D0, D1, D2, or CLK
–100
100
ps
R[7:0], G[7:0], B[7:0], VS, HS, PCLK, CPE
Rise and fall time 20%–
80% of VDD (2)
tR/F
tOUTP
PCLK output duty cycle
Output skew between PCLK
and R[0:7], G[0:7], B0:7],
HS, VS, and DE
tOSK
CL = 10 pF (3); see Figure 9
1-channel mode, F/S=L
8
16
2-channel mode, F/S=L
4
8
3-channel mode, F/S=L
4
8
1-channel mode, F/S=H
4
8
2-channel mode, F/S=H
1
2
3-channel mode, F/S=H
1
ns
2
1-channel and 3-channel mode
45%
50%
55%
CPOL=VIL, 2-channel mode
48%
53%
59%
CPOL=VIH, 2-channel mode
41%
47%
52%
see Figure 9
–500
500
ps
2.5/fPCLK
s
3.8
µs
2
ms
INPUT TO OUTPUT RESPONSE TIME
tPD(L)
Propagation delay time from
CLK+ input to PCLK output
RXEN at VDD, VIH=VDD, VIL=GND, CL=10 pF, See
Figure 14
tGS
RXEN glitch suppression
pulse width (4)
VIH=VDD, VIL=GND, RXEN toggles between VIL and VIH;
See Figure 15 and Figure 16
tpwrup
Enable time from power
down (↑RXEN)
Time from RXEN pulled high to data outputs enabled and
transmit valid data; See Figure 16
tpwrdn
Disable time from active
mode (↓RXEN)
RXEN is pulled low during receive mode; time
measurement until all outputs held static:
R[0:7]=G[0:7]=B[0:7]=VS=HS=high, DE=PCLK=low and
PLL is Shutdown; See Figure 16
11
µs
Enable time from Standby
(↑↓CLK)
RXEN at VDD; device is in standby; time measurement
from CLK input starts switching to PCLK and data
outputs enabled and transmit valid data; See Figure 17
2
ms
tsleep
Disable time from active
mode (CLK transitions to
high-impedance)
RXEN at VDD; device is receiving data; time
measurement from CLK input signal stops (input open or
input common mode VICM exceeds threshold voltage
Vthstby) until all outputs held static:
R[0:7]=G[0:7]=B[0:7]=VS=HS=high,
DE=PCLK=low and PLL is Shutdown;
See Figure 17
3
µs
fBW
PLL bandwidth (5)
Tested from CLK input to
PCLK output
twakeup
(1)
(2)
(3)
(4)
(5)
16
1.4/fPCLK
2-ChM; fPCLK=22MHz
0.087×fPCLK
3-ChM; fPCLK=65MHz
0.075×fPCLK
1.9/fPCLK
MHz
All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
tR/F depends on the F/S setting and the capacitive load connected to each output. Some application information of how to calculate tR/F
based on the output load and how to estimate the timing budget to interconnect to an LCD driver are provided in the application section
near the end of this data sheet.
The output rise and fall time is optimized for an output load of 10 pF. The rise and fall time can be adjusted by changing the output load
capacitance.
The RXEN input incorporates a glitch-suppression logic to disregard short input pulses. tGS is the duration of either a high-to-low or
low-to-high transition that is suppressed.
When using the SN65LVDS302 receiver in conjunction with the SN65LVDS301 transmitter in one link, the PLL bandwidth of the
SN65LVDS302 receiver always exceed the bandwidth of the SN65LVDS301 transmit PLL. This ensures stable PLL tracking under all
operating conditions and maximizes the receiver skew margin.
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9.0
12
4 MHz
9%
8 MHz
9%
20 MHz
8.7 %
8.5
Spec Limit
1 ChM
10
PLL - Bandwidth - %
PLL BW (% of PCLK Frequency)
11
9
8
7
Spec Limit
2 ChM
8.0
15 MHz
8.1 %
Spec Limit
3 ChM
30 MHz
8.1 %
7.5
65 MHz
7.5 %
7.0
6
6.5
5
4
0
6.0
100
200
300
400
500
PLL - Frequency - MHz
600
700
0
10
20
50
30
40
PCLK - Frequency - MHz
60
70
Figure 6. SN65LVDS302 PLL Bandwidth (also showing the SN65LVDS301 PLL bandwidth)
TIMING CHARACTERISTICS
PARAMETER
tRSKMx
(1) (2)
(1)
(2)
(3)
(4)
(5)
Receiver input skew
margin; see (3) and
Figure 43
TEST CONDITIONS
1ChM: x=0..29, fPCLK=15 MHz;
RXEN at VDD, VIH=VDD,
VIL=GND, RL=100 Ω, test setup
as in Figure 8, test pattern as in
Table 11
fCLK=15 MHz (4)
2ChM: x = 0..14,
fPCLK =30 MHz
RXEN at VDD, VIH=VDD,
VIL=GND, RL=100 Ω, test setup
as in Figure 8, test pattern as in
Table 12
fCLK=30 MHz (4)
3ChM:
RXEN at VDD, VIH=VDD,
VIL=GND, test setup as in
Figure 8, test pattern as in
Table 13
fCLK= 65 MHz (4)
fCLK=4 MHz to 15 MHz (5)
MIN
MAX
UNIT
630
1
- 480 ps
2 · 30 · fCLK
630
fCLK=8 MHz to 30 MHz (5)
1
- 480 ps
2 · 15 · fCLK
fCLK = 20 MHz to 65
MHz (5)
ps
360
1
- 410 ps
2 · 10 · fCLK
Receiver Input Skew Margin (tRSKM) is the timing margin available for transmitter output pulse position (tPPOS), interconnect skew, and
interconnect inter-symbol interference. tRSKM represents the reminder of the serial bit time not taken up by the receiver strobe
uncertainty;. The tRSKM assumes a bit error rate better than 10-12.
tRSKM is indirect proportional to the internal set-up and hold time uncertainty, ISI and duty cycle distortion from the front end receiver, the
skew missmatch between CLK and data D0, D1, and D2, as well as the PLL cycle-to-cycle jitter.
This includes the receiver internal set-up and hold time uncertainty, all PLL related high-frequency random and deterministic jitter
components that impact the jitter budget, ISI and duty cycle distortion from the front end receiver, and the skew between CLK and data
D0, D1, and D2; The pulse position min/max variation is given with a bit error rate target of 10–12; Measurements of the total jitter are
taken over a sample amount of > 10–12 samples.
The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temp ranges.
These Minimum and Maximum Limits are simulated only.
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PARAMETER MEASUREMENT INFORMATION
SN65LVDS302
2
1
Noise
Generator
100 mV
1W
VDDPLLA
VDDPLLD
VDD
10 µF
VDDLVDS
GND
Note: The generator regulates the
noise amplitude at point 1
to the
target amplitude given under the table
Recommended Operating Conditions
1.8 V
Supply
1.6 H
Figure 7. Power Supply Noise Test Set-Up
To measure t RSKM, CLK is advanced or delayed with respect to data until errors are observed at the receiver outputs. The advance
or delay is then reduced until there are no data errors observed over 10-12 serial bit times. The magnitude of the advance or delay
is tRSKM
Programmable delay
CLK and Data
Pattern
Generator
CLK
D1
DUT:
SN65LVDS302
D2
Bit error
Detector
D3
Ideal receiver strobe position
tPG_ERROR
TRSKM(p)
C
TRSKM(n)
tbit
tRSKM
tPG_ERROR
tbit
C
- is the smaller of the two measured values tRSKM(p) and tRSKM(n)
- Test equipment (pattern generator) intrinsic output pulse position timing uncertainty
- serial bit time
- LVDS302 set-up and hold-time uncertainty
Note: C can be derived by subtracting the receiver skew margin t RSKM(p) + tRSKM(p) from one serial bit time
Figure 8. Jitter Budget
18
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PARAMETER MEASUREMENT INFORMATION (continued)
tF
t setup
80% (VOH -V OL )
R[7:0], G[7:0],
B[7:0], HS, VS, DE
20% (VOH -V OL )
t hold
t OSK
tR
VOH
80% (VOH -V OL )
PCLK
50% (VOH
- –VOL)
(CPOL=0)
20% (VOH -VOL )
VOL
tR
tF
Note:
The Set-up and Hold-time of CMOS outputs R[7:0], G[7:0],
B[7:0], HS, VS, and DE in relation to PCLK can be
calulated by:
1
tS&H =
2 -rPCLK -tREF - tOSK - DtDUTP
Figure 9. Output Rise/Fall, Setup/Hold Time
VDx+ – VDx– , VCLK+ – VCLK–
100%(VIC)
tf
80%(VID)
tr
0V
20%(VID)
0%(VID)
Figure 10. SubLVDS Differential Input Rise and Fall Time Defintion
CLK+, Dx+
VDDLVDS
RID /2
R BBDC
Gain
Stage
RID/2
CLK–, Dx–
Standby
detection
line end
termination
ESD
Figure 11. Equivalent Input Circuit Design
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PARAMETER MEASUREMENT INFORMATION (continued)
I ICMOS
SWAP,
CPOL, LSx,
RXEN, F/S
CMOS Input
(V I++V I-)/2
I I+
V ICMOS
CLK+, Dx+
RGB, VS, HS,
CPE PCLK
V ID
IO
I ICLK-, Dx-
V ICM
V I+
VO
V ISubLVDS Input
CMOS Output
Figure 12. I/O Voltage and Current Definition
RGB, VS, HS,
CPE, PCLK
VO
SN65LVDS302
CL=10 pF
Figure 13. CMOS Output Test Circuit, Signal and Timing Definition
20
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PARAMETER MEASUREMENT INFORMATION (continued)
Pixel(n–1)
R7(n–1)
R7(n–2)
D0+
R7 R6 R5 R4
Pixel(n)
Pixel(n+1)
R7(n)
R7(n+1)
CP R7
CP R7
CLK–
CLK+
tPD(L)
VDD/2
PCLK
(CPOL = 0)
Pixel(n–1)
CMOS Data Out
R7
R7(n–3)
R7(n–1)
R6
R6(n–3)
R6(n–1)
Figure 14. Propagation Delay Input to Output (LS0=LS1=0)
V DD /2
RXEN
t GS
CLK
t PLL
VCO internal signal
PLL approaches lock
t pwrup
PCLK
R[7:0],G[7:0],B[7:0], DE, VS, HS
Figure 15. Receiver Phase Lock Loop Set TIme and Receiver Enable Time
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PARAMETER MEASUREMENT INFORMATION (continued)
<20 ns
3 ms
Glitch shorter
than t GS will be
ignored
2 ms
less than 20ns
Spike will be
rejected
Glitch shorter
than tGS will be
ignored
RXEN
tpwrup
tpwrdn
PCLK
tGS
I CC
tGS
CLK
Receiver disabled
(OFF)
RX RX disabled
turns (OFF)
OFF
Receiver enabled
(ON)
Receiver aquires lock
Figure 16. Receiver Enable/Disable Glitch Suppression Time
CLK
t
t
wakeup
sleep
PCLK
R[7:0], G[7:0], B[7:0], VS, HS,
RX enabled
output data valid
Receiver aquires lock,
outputs still disabled
Receiver disabled
(OFF)
RX enabled;
output data
invalid
RX
disabled
(OFF)
Figure 17. Standby Detection
POWER CONSUMPTION TESTS
Table 5 shows an example test pattern word.
Table 5. Example Test Pattern Word
Word
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
7
0x7C3E1E7
C
3
E
1
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7
0
22
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
E
7
B6
B5
B4
B3
B2
B1
B0
0
0
0
1
1
1
1
0
0
0
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TYPICAL IC POWER CONSUMPTION TEST PATTERN
Typical power-consumption test patterns consist of sixteen 30-bit transmit words in 1-channel mode, eight 30-bit
transmit words in 2-channel mode and five 30-bit transmit words in 3-channel mode. The pattern repeats itself
throughout the entire measurement. It is assumed that every possible transmit code on RGB inputs has the
same probability to occur during typical device operation.
Table 6. Typical IC Power Consumption Test Pattern,
1-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x0000007
2
0xFFF0007
3
0x01FFF47
4
0xF0E07F7
5
0x7C3E1E7
6
0xE707C37
7
0xE1CE6C7
8
0xF1B9237
9
0x91BB347
10
0xD4CCC67
11
0xAD53377
12
0xACB2207
13
0xAAB2697
14
0x5556957
15
0xAAAAAB3
16
0xAAAAAA5
Table 7. Typical IC Power Consumption Test Pattern,
2-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x0000001
2
0x03F03F1
3
0xBFFBFF1
4
0x1D71D71
5
0x4C74C71
6
0xC45C451
7
0xA3aA3A5
8
0x5555553
Table 8. Typical IC Power Consumption Test Pattern,
3-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0xFFFFFF1
2
0x0000001
3
0xF0F0F01
4
0xCCCCCC1
5
0xAAAAAA7
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MAXIMUM POWER CONSUMPTION TEST PATTERN
The maximum (or worst-case) power consumption of the SN65LVDS302 is tested using the two different test
pattern shown in table. Test patterns consist of sixteen 30-bit transmit words in 1-channel mode, eight 30-bit
transmit words in 2-channel mode, and five 30-bit transmit words in 3-channel mode. The pattern repeats itself
throughout the entire measurement. It is assumed that every possible transmit code on RGB inputs has the
same probability to occur during typical device operation.
Table 9. Worst-Case Power Consumption Test Pattern
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0xAAAAAA5
2
0x5555555
Table 10. Worst-Case Power Consumption Test Pattern
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x0000000
2
0xFFFFFF7
OUTPUT SKEW PULSE POSITION and JITTER PERFORMANCE
The following test patterns are used to measure the output skew pulse position and the jitter performance of the
SN65LVDS302. The jitter test pattern stresses the interconnect, particularly to test for ISI, using very long
run-lengths of consecutive bits, and incorporating very high and low data rates, maximizing switching noise.
Each pattern is self-repeating for the duration of the test.
Table 11. Transmit Jitter Test Pattern, 1-Channel Mode
Word
24
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x0000001
2
0x0000031
3
0x00000F1
4
0x00003F1
5
0x0000FF1
6
0x0003FF1
7
0x000FFF1
8
0x0F0F0F1
9
0x0C30C31
10
0x0842111
11
0x1C71C71
12
0x18C6311
13
0x1111111
14
0x3333331
15
0x2452413
16
0x22A2A25
17
0x5555553
18
0xDB6DB65
19
0xCCCCCC1
20
0xEEEEEE1
21
0xE739CE1
22
0xE38E381
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Table 11. Transmit Jitter Test Pattern, 1-Channel
Mode (continued)
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
23
0xF7BDEE1
24
0xF3CF3C1
25
0xF0F0F01
26
0xFFF0001
27
0xFFFC001
28
0xFFFF001
29
0xFFFFC01
30
0xFFFFF01
31
0xFFFFFC1
32
0xFFFFFF1
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Table 12. Transmit Jitter Test Pattern, 2-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x0000001
2
0x000FFF3
3
0x8008001
4
0x0030037
5
0xE00E001
6
0x00FF001
7
0x007E001
8
0x003C001
9
0x0018001
10
0x1C7E381
11
0x3333331
12
0x555AAA5
13
0x6DBDB61
14
0x7777771
15
0x555AAA3
16
0xAAAAAA5
17
0x5555553
18
0xAAA5555
19
0x8888881
20
0x9242491
21
0xAAA5571
22
0xCCCCCC1
23
0xE3E1C71
24
0xFFE7FF1
25
0xFFC3FF1
26
0xFF81FF1
27
0xFE00FF1
28
0x1FF1FF1
29
0xFFCFFC3
30
0x7FF7FF1
31
0xFFF0007
32
0xFFFFFF1
Table 13. Transmit Jitter Test Pattern, 3-Channel Mode
Word
26
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x0000001
2
0x0000001
3
0x0000003
4
0x0101013
5
0x0303033
6
0x0707073
7
0x1818183
8
0xE7E7E71
9
0x3535351
10
0x0202021
11
0x5454543
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Table 13. Transmit Jitter Test Pattern, 3-Channel
Mode (continued)
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
12
0xA5A5A51
13
0xADADAD1
14
0x5555551
15
0xA6A2AA3
16
0xA6A2AA5
17
0x5555553
18
0x5555555
19
0xAAAAAA1
20
0x5252521
21
0x5A5A5A1
22
0xABABAB1
23
0xFDFCFD1
24
0xCAAACA1
25
0x1818181
26
0xE7E7E71
27
0xF8F8F81
28
0xFCFCFC1
29
0xFEFEFE1
30
0xFFFFFF1
31
0xFFFFFF5
32
0xFFFFFF5
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TYPICAL CHARACTERISTIC CURVES
Some of the plots in this section show more than one curve representing various device pin relationships. Taken together,
they represent a working range for the tested parameter.
SUPPLY CURRENT vs TEMPERATURE
QUIESCENT SUPPLY CURRENT vs TEMPERATURE
100.0
30
2-Channel Mode, 22 MHz (VGA), F/S = 1
25
STANDBY
2-Channel Mode, 11 MHz (HVGA), F/S = 1
10.0
IDDQ - mA
IDD - mA
20
2-Channel Mode, 22 MHz (VGA), F/S = 0
15
2-Channel Mode, 11 MHz (HVGA), F/S = 0
10
1.0
POWERDOWN
5
0.1
-50
0
-50
-30
-10
10
30
Temperature - °C
50
70
90
-30
-10
10
30
50
Temperature - °C
70
90
Figure 18.
Figure 19.
SUPPLY CURRENT vs FREQUENCY, 1-CHANNEL MODE
SUPPLY CURRENT vs FREQUENCY, 2-CHANNEL MODE
40
40
35
35
30
30
2 - ChM, F/S = 1, typ pwr
2 - ChM, F/S = 1, jitter test
25
1 - ChM, F/S = 1, jitter test
IDD - mA
IDD - mA
25
20
1 - ChM,
F/S = 1,
typ pwr
1 - ChM F/S = 0, jitter test
15
20
15
10
10
2 - ChM F/S = 0, jitter test
5
5
1 - ChM, F/S = 0, typ pwr
2 - ChM, F/S = 0, typ pwr
0
0
0
5
10
f - Frequency - MHz
15
0
20
5
10
15
20
25
30
f - Frequency - MHz
Figure 20.
Figure 21.
SUPPLY CURRENT vs FREQUENCY, 3-CHANNEL MODE
RECEIVER STROBE POSITION vs TEMPERATURE
450
40
3 - ChM, F/S = 1, jitter test
35
350
30
FL3G Limit
300
t(RSPOS)
25
IDD - mA
Limit with RSKM=130 ps
400
3 - ChM, F/S = 1, typ pwr
20
3 - ChM F/S = 0, jitter test
15
3-ChM 56 MHz (XGA)
250
2-ChM 22 MHz (VVGA)
200
3-ChM 65 MHz
150
10
3 - ChM, F/S = 0, typ pwr
1-ChM 11 MHz (HVGA)
100
5
50
0
15
20
25
30
40
35
45
f - Frequency - MHz
50
55
60
0
-40
Figure 22.
28
-20
0
20
40
Temperature - °C
Figure 23.
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TYPICAL CHARACTERISTIC CURVES (continued)
PLL Bandwidth
PCLK Cycle-to-Cycle output jitter
12.0
900
3-ChM
10.0
3-ChM
8 MHz: 9%
3-ChM
2-ChM
3-ChM
Spec Limit 3ChM
1-ChM
600
Spec Limits
2-Ch Mode
CC Jitter - ps
Spec Limits
1-Ch Mode
700
Spec Limits
3-Ch Mode
6.0
4.0
500
400
300
200
2.0
0.0
0.0
3-ChM
2-ChM
100
0
10.0
20.0
30.0
40.0
50.0
Frequency - MHz
60.0
70.0
0
10
Figure 24.
20
30
40
50
Frequency - MHz
60
70
Figure 25.
RSKM, 1-CHANNEL MODE vs BIT RATE
2000
Receiver Strobe
Position uncertainty
1500
T(PPOS )
1000
Additional interconnect margin
500
RSKM - ps
PLL Bandwidth - %
2-ChM
8.0
800
Spec Limit 2ChM
225
Minimum desired interconnect budget
0
-225-
-500
-1000
-1500
-2000
120
170
220
270
320
370
420
dR - Mbps
Bit width
Trskm
1ChM
Trskm - Tppos
225ps
Figure 26.
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TYPICAL CHARACTERISTIC CURVES (continued)
RSKM, 2-CHANNEL MODE vs BIT RATE
RSKM, 3-CHANNEL MODE vs BIT RATE
2000
2000
1500
500
225 ps
Time - ps
Time - ps
1000
0
-500
225 ps
-500
270
320
dR - Mbps
370
420
-2000
200
190
190
1-Channel Mode,
f(PCLK) = 5.5 MHz
–190
350
400 450
dR - Mbps
500
550
600
0
2-Channel Mode,
f(PCLK) = 22 MHz
–190
–251
–250
1 ns/div
Response Over 80-inch of FR-4 + 1m Coax Cable
500 ps/div
Response Over 8-inch FR-4 + 1m Coax Cable
Figure 29.
Figure 30.
VGA 2-CHANNEL OUTPUT WAVEFORM
VGA3-CHANNEL OUTPUT WAVEFORM
249
249
190
190
Output Voltage Amplitude - mV
Output Voltage Amplitude - mV
300
VGA 2-CHANNEL OUTPUT WAVEFORM
250
Output Voltage Amplitude - mV
Output Voltage Amplitude - mV
QVGA OUTPUT WAVEFORM
2-Channel Mode,
f(PCLK) = 22 MHz
0
3-Channel Mode,
f(PCLK) = 22 MHz
–190
–190
–251
–251
30
250
Figure 28.
249
0
Trskm
-1500
Figure 27.
0
225 ps
Bit width
Bit width
-1500
220
225 ps
0
-1000
Trskm
170
Trskm
Trskm - Tppos
Trskm - Tppos
Trskm - Tppos
-1000
-2000
120
Bit width
Trskm - Tppos
1000
500
1500
Bit width
Trskm
500 ps/div
Response Over 80-inch FR-4 + 1m Coax Cable
1 ns/div
Response Over 80-inch FR-4 + 1m Coax Cable
Figure 31.
Figure 32.
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TYPICAL CHARACTERISTIC CURVES (continued)
XGA 3-CHANNEL OUTPUT WAVEFORM
XGA 3-CHANNEL OUTPUT WAVEFORM
249
Output Voltage Amplitude - mV
400 mV/div
Output Voltage Amplitude - mV
190
0
–190
3-Channel Mode,
f(PCLK) = 56 MHz
3-Channel Mode,
f(PCLK) = 56 MHz
–251
300 ps/div
Response Over 80-inch FR-4 + 1m Coax Cable
3.5 ns/div
Response With 10-pF Load
Figure 33.
Figure 34.
INPUT COMMON-MODE NOISE REJECTION vs
FREQUENCY
INPUT RETURN LOSS
0.0
0.0
-2.0
-10.0
-4.0
Differential S11 - dB
CMNR - dB
-6.0
-8.0
-10.0
-12.0
-14.0
-16.0
-20.0
-30.0
-40.0
-50.0
-18.0
-20.0
0
-60.0
200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency - MHz
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency - MHz
Figure 35.
Figure 36.
INPUT DIFFERENTIAL CROSSTALK vs FREQUENCY
PHASE NOISE
0.0
-50
-60
-70
-20.0
-80
-30.0
-100
-90
dBc/Hz
Differential Xtalk - dB
-10.0
-40.0
f(PCLK) = 65 MHz
-110
-120
-130
-50.0
-140
-60.0
-150
-160
-70.0
-170
-80.0
-180
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency - MHz
1
Figure 37.
10
100
1k
10k
100k
1M
10M
FREQUENCY - Hz
Figure 38.
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TYPICAL CHARACTERISTIC CURVES (continued)
GTEM SAE J1752/3 EMI test
30
f(PCLK)=62 MHz
RADIATED EMISSION - dBmV
25
20
15
10
5
0
0
200
400
600
800
1000
1200
FREQUENCY - MHz
Figure 39.
32
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APPLICATION INFORMATION
Preventing Increased Leakage Currents in Control Inputs
A floating (left open) CMOS input allows leakage currents to flow from VDD to GND. Do not leave any CMOS
input unconnected or floating. Every input must be connected to a valid logic level VIH or VOL while power is
supplied to VDD. This also minimizes the power consumption of standby and power down mode.
Power Supply Design Recommendation
For a multilayer PCB, it is recommended to keep one common GND layer underneath the device and connect all
ground terminals directly to this plane.
SN65LVDS302 DECOUPLING RECOMMENDATION
The SN65LVDS302 was designed to operate reliably in a constricted environment with other digital switching
ICs. In cell phone designs, the SN65LVDS302 often shares a power supply with various other ICs. The
SN65LVDS302 can operate with power supply noise as specified in Recommend Device Operating Conditions.
To minimize the power supply noise floor, provide good decoupling near the SN65LVDS302 power pins. The
use of four ceramic capacitors (two 0.01 µF and two 0.1 µF) provides good performance. At the very least, it is
recommended to install one 0.1 µF and one 0.01 µF capacitor near the SN65LVDS302. To avoid large current
loops and trace inductance, the trace length between decoupling capacitor and IC power inputs pins must be
minimized. Placing the capacitor underneath the SN65LVDS302 on the bottom of the PCB is often a good
choice.
VGA APPLICATION
Figure 40 shows a possible implementation of a standard 640x480 VGA display. The LVDS301 interfaces to the
SN65LVDS302, which is the corresponding receiver device to deserialize the data and drive the display driver.
The pixel clock rate of 22 MHz assumes ~10% blanking overhead and 60 Hz display refresh rate. The
application assumes 24-bit color resolution. Also shown is how the application processor provides a powerdown
(reset) signal for both serializer and the display driver. The signal count over the Flexible Printed Circuit board
(FPC) could be further decreased by using the standby option on the SN65LVDS302 and pulling RXEN high
with a 30 kΩ resistor to VDD.
22MHz
27
22MHz
D0+
D0-
PCLK
R[7:0]
G[7:0]
B[7:0]
HS,VS,DE
330Mbps
D1+
D1-
330Mbps
PCLK
D1+
D1-
R[7:0]
G[7:0]
B[7:0]
HS,VS,DE
SN65LVDS 302
LS0
TXEN
LS0
LS1
SPI
RESET
SN65LVDS 301
CLK+
CLKD0+
D0-
1.8 V
Video Mode Display
Driver
22MHz
27
LCD with VGA
resolution
GND
SPI
GND
2x0.01uF
ENABLE
1.8V
RXEN
D[7:0]
D[15:8]
D[23:16]
HS,VS,DE
1.8V
CLK+
CLK-
2x0.1uF
GND
2.7 V
LS1
VDDx
Application
Processor
(e.g. OMAP)
Pixel CLK
GND
2x0.01uF
FPC
GND
GND
2.7V
VDDx
2x0.1uF
1.8V
Serial port interface
(3-wire )IF
If FPC wire count is
, critical replace this
connection with- a pull up resistor at RXEN
3
Figure 40. Typical VGA Display Application
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APPLICATION INFORMATION (continued)
DUAL LCD-DISPLAY APPLICATION
The example in Figure 41 shows a possible application setup driving two video-mode displays from one
application processor. The data rate of 330 Mbps at a pixel clock rate of 5.5 MHz corresponds to a 320x240
QVGA resolution at 60 Hz refresh rate and 10% blanking overhead.
18+3
CLK+
5.5MHz
CLKD0+
330Mbps
D0-
CLK+
CLK-
PCLK
D0+
D0-
R[ 5: 0]
G[ 5: 0]
B[ 5: 0]
HS, VS, DE
Display Driver
PCLK
R[ 5:
G[ 5:
B[ 5:
HS, VS,
PCLK
0]
0]
0]
DE
EN
SIN
SOUT
SCLK
LS0
Display Driver
PCLK
1.8V
1
21
SN65LVDS 302
TXEN
LS0
LS1
SN 65LVDS 301
SCLK
SI N
SOUT
SEL2
SEL1
GND
2x0.01uF
LCD with QVGA
resolution
1. 8V
GND
2. 7V
1. 8V
EN
SIN
SOUT
SCLK
1.8V
2
LCD wit h QVGA
resolut ion
D[ 5: 0]
D[ 11 : 6]
D[ 17 : 12 ]
HS, VS, DE
5.5MHz
2. 7V
GND
2x0.1uF
GND
RXEN
VDDx
Application
Processor
(e.g. OMAP )
Pixel CLK
GND
2x0.01uF
FPC
VDDx
GND
LS1
2x0.1uF
Figure 41. Example Dual-QVGA Display Application
TYPICAL APPLICATION FREQUENCIES
The SN65LVDS302 supports pixel clock frequencies from 4 MHz to 65 MHz over 1, 2, or 3 data lanes. Table 14
provides a few typical display resolution examples and shows the number of data lanes necessary to connect
the SN65LVDS302 with the display. The blanking overhead is assumed to be 20%. Often, blanking overhead is
smaller, resulting in a lower data rate. Furthermore, the examples in the table assumes a display frame refresh
rate of 60-Hz. The actual refresh rate may differ depending on the application-processor clock implementation.
Table 14. Typical Application Data Rates and Serial Lane Usage
Display Screen
Resolution
Visible
Pixel Count
Blanking
Overhead
Display
Refresh
Rate
Pixel Clock Frequency
[MHz]
176x220 (QCIF+)
38,720
20%
90 Hz
4.2 MHz
125 Mbps
240x320 (QVGA)
76,800
20%
60 Hz
5.5 MHz
166 Mbps
640x200
128,000
20%
60 Hz
9.2 MHz
276 Mbps
138 Mbps
352x416 (CIF+)
146,432
20%
60 Hz
10.5 MHz
316 Mbps
158 Mbps
352x440
154,880
20%
60 Hz
11.2 MHz
335 Mbps
167 Mbps
320x480 (HVGA)
153,600
20%
60 Hz
11.1 MHz
332 Mbps
166 Mbps
800x250
200,000
20%
60 Hz
14.4 MHz
432 Mbps
216 Mbps
640x320
204,800
20%
60 Hz
14.7 MHz
442 Mbps
221 Mbps
640x480 (VGA)
307,200
20%
60 Hz
22.1 MHz
332 Mbps
221 Mbps
1024x320
327,680
20%
60 Hz
23.6 MHz
354 Mbps
236 Mbps
854x480 (WVGA)
409,920
20%
60 Hz
29.5 MHz
443 Mbps
295 Mbps
800x600 (SVGA)
480,000
20%
60 Hz
34.6 MHz
346 Mbps
1024x768 (XGA)
786,432
20%
60 Hz
56.6 MHz
566 Mbps
34
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Serial Data Rate Per Lane
1-ChM
2-ChM
3-ChM
SN65LVDS302
www.ti.com
SLLS733A – JUNE 2006 – REVISED AUGUST 2006
CALCULATION EXAMPLE: HVGA DISPLAY
Display Resolution:
320 x 480
Frame Refresh Rate:
58.4 Hz
Vertical Visible Pixel:
480 lines
Vertical Front Porch:
20 lines
Vertical Sync:
5 lines
Vertical Back Porch:
3 lines
Horizontal Visible Pixel:
320 columns
Horizontal Front Porch:
10 columns
Horizontal Sync:
5 columns
Horizontal Back Porch:
3 columns
Hsync =5
HBP
The following calculation shows an example for a Half-VGA display with the following parameters:
Visible area = 480 column
HFP=20
Vsync =5
VBP =3
Visible area
=320 lines
Visible area
Entire Display
VFP=10
Figure 42. HVGA Display
Calculation of the total number of pixel and blanking overhead:
Visible Area Pixel Count: 480 × 320 = 153600 pixel
Total Frame Pixel Count: (480+20+5+3) × (320+10+5+3) = 173304 pixel
Blanking Overhead:
(173304-153600) ÷ 153600 = 12.8 %
The application requires the following serial-link parameters:
Pixel Clk Frequency:
173304 × 58.4 Hz = 10.1 MHz
Serial Data Rate:
1-channel mode: 10.4 MHz × 30 bit/channel = 304 Mbps
2-channel mode: 10.4 MHz × 15 bit/channel = 152 Mbps
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35
SN65LVDS302
www.ti.com
SLLS733A – JUNE 2006 – REVISED AUGUST 2006
How To Determine Interconnect Skew and Jitter Budget
Designing a reliable data link requires examining the interconnect skew and jitter budget. The sum of all
transmitter, PCB, connector, FPC, and receiver uncertainties must be smaller than the available serial bit time.
The highest pixel clock frequency defines the available serial bit time. The transmitter timing uncertainty is
defined by tPPOS in the transmitter data sheet. For a bit-error-rate target of ≤ 10-12, the measurement duration
for tPPOS is ≥ 1012. The SN65LVDS302 receiver can tolerate a maximum timing uncertainty defined by tRSKM.
The interconnect budget is calculated by:
t int erconnect = t RSKM - t PPOS
(1)
Example:
fPCLK(max) = 23 MHz (VGA display resolution, 60 Hz)
Transmission mode: 2-ChM; tPPOS(SN65LVDS301) = 330 ps
Target bit error rate: 10-12
tRSKM(SN65LVDS302) = 1/(2*15*fPCLK) – 480 ps = 969 ps
The interconnect budget for cable skew & ISI needs to be smaller than:
t int erconnect = t RSKM - t PPOS = 639ps
(2)
Ideal TPPosn data transition
Data Period /2
D0, D1, D2
TPPosn(min)
TPPosn(max)
Ideal receiver strobe position
RSKM
RSKM
RX internal sampling clock
Tppos: Transmitter output pulse position (min and max)
RSKM: Receiver Skew Margin
TPPosx(max) -TPPosx(min) = TJ TXPLL(non-trackable) + tTXskew + tTXDJ
RSKM = SKEW PCB + XTALK PCB + ISIPCB
TJ TXPLL(non-trackable): non-trackable TX PLL jitter; this jitter is the integration
> f (BWRX);
of total jitter above the receiver PLL bandwidth ; TJ TXPLL
TJ=RJ[ps-rms]*14 + DJ[ps]
t TXskew
: transmitter output skew (skew between CLK and data)
SKEW
XTALK
Intersymbol Interference ISI)
RSPosn: Receiver input strobe position (min and max)
RSPosn(max) - RSPosn(min) = SkewRX + S&HRX + TJ (RXPLL(non-trackable)
PCB : PCB induced Skew (trace + connector);
: PCB induced cross-talk;
PCB
ISI PCB: Inter-symbol interference of PCB; is
dependent on interconnect frequency loss; may be
zero for short interconnects.
t TXIDJTransmitter Deterministic JItter of TX output stage (includes TX
RSPosn (max)
RSPosn (min)
Skew RX: Receiver input skew (skew between CLK and Dx input)
S&H RX: Receiver input latch Sample & Hold uncertainty
TJ (RXPLL(non-trackable) : Intrinsic RX PLL jitter above RX PLL bandwidth; PLL
f(BW RX ); TJ=RJ[ps-rms]*14 + DJ[ps]
Figure 43. Jitter Budget
36
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TJ >
SN65LVDS302
www.ti.com
SLLS733A – JUNE 2006 – REVISED AUGUST 2006
F/S-PIN SETTING AND CONNECTING THE SN65LVDS302 TO AN LCD DRIVER
NOTE:
Receiver PLL tracking: To maximize the design margin for the interconnect, good
RX PLL tracking of the TX PLL is important. FlatLink3G requires the RX PLL to have
a bandwidth higher than the bandwidth of the TX PLL. The SN65LVDS302 PLL
design is optimized to track the SN65LVDS0301 PLL particularly well, thus providing
a very large receiver skew margin. A FlatLink3G-compliant link must provide at least
±225 ppm of receiver skew margin for the interconnect.
It is important to understand the tradeoff between power consumption, EMI, and maximum speed when selecting
the F/S signal. It is beneficial to choose the slowest rise time possible to minimize EMI and power consumption.
Unfortunately a slower rise time also reduces the timing margin left for the LCD driver. Hence it is necessary to
calculate the timing margin to select the correct F/S pin setting.
The output rise time depends on the output driver strength and the output load. An LCD driver typical capacitive
load is assumed with ~10pF. The higher the capacitive load, the slower will be the rise time. Rise time of the
SN65LVDS302 is measured as the time duration it takes the output voltage to rise from 20% of VDD and 80% of
VDD and fall time is defined as the time for the output voltage to transition from 80% of VDD down to 20%.
Within one mode of operation and one F/S pin setting, the rise time of the output stage is fixed and does not
adjust to the pixel frequency. Due to the short bit time at very fast pixel clock speeds and the real capacitive load
of the display driver, the output amplitude might not reach VDD and GND saturation fully. To ensure sufficient
signal swing and verify the design margin, it becomes necessary to determine that the output amplitude under
any circumstance reaches the display driver’s input stage logic threshold (usually 30% and 70% of VDD).
Figure 44 shows a worst-case rise time simulation assuming a LCD driver load of 16pF at VGA display
resolution. PCLK is the fastest switching output. With F/S set to GND (Figure 44-a), the PCLK output voltage
amplitude is significantly reduced. The voltage amplitude of the output data RGB[7:0], VS, HS, and DE shows
less amplitude attenuation because these outputs carry random data pattern and toggle equal or less than half
of the PCLK frequency. It is necessary to determine the timing margin between the LVDS302 output and LCD
driver input.
RX rise/fall time
Application: VGA (2-channel mode); F/S set to GND; Display driver load ~16 pF
RX rise/fall time
Application: VGA (2-channel mode); F/S set to VDD; Display driver load ~16 pF
2.0V
2.0V
1.8V
1.8V
1.6V
1.6V
1.4V
1.4V
1.2V
VOD
VOD
1.2V
(
1.0V
0.8V
0.6V
0.6V
0.4V
0.4V
0.2V
0.2V
0.0V
100ns
150ns
200ns
250ns
300ns
350ns
clk 22 MHz, F/S=1, CL=16 pF
400ns
450ns
500ns
550ns
600ns
The data signal has a slower maximum switching
frequency, and therefore drives a larger amplitude
than the clock signal
1.0V
0.8V
0.0V
100ns
150ns
200ns
250ns
300ns
350ns
clk 22 MHz, F/S=0, CL=16 pF
data 22 Mbps, F/S=1, CL=16 pF
400ns
450ns
500ns
550ns
600ns
data 22 Mbps, F/S=0, CL=16 pF
(b)
(a)
Figure 44. Output Amplitude as a Function of Output Toggling Frequency,
Capacitive Load and F/S Setting
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37
SN65LVDS302
www.ti.com
SLLS733A – JUNE 2006 – REVISED AUGUST 2006
HOW TO DETERMINE THE LCD DRIVER TIMING MARGIN
To determine the timing margin, it is necessary to specify the frequency of operation, identify the set-up and hold
time of the LCD driver, and specify the output load of the SN65LVDS302 as a combination of the LCD driver
input parasitics plus any capacitance caused by the connecting PCB trace. Furthermore, the setting of pin F/S
and the SN65LVDS302 output skew impact the margin. The total remaining design margin calculates as
following:
t rise(max) C LOAD
1
t DM +
* t DUTP(max_error) *
* Ťt OSKŤ
2 ƒ PCLK
10 pF
(3)
where:
tDM– Design margin
fPCLK– Pixel clock frequency
tDUTP(max_error)– maximum duty cycle error
trise(max)– maximum rise or fall time; see tR/F under switching characteristics
CL– parasitic capacitance (sum of LCD driver input parasitics + connecting PCB trace)
tskew– clock to data output skew SN65LVDS302
Example:
At a pixel clock frequeny of 5.5MHz (QVGA), and an assumed LCD driver load of 15 pF, the remaining timing
margin is:
Ť
Ť
t
(max) * 50
t DUTP(max_error) + DUTP
100%
t DM +
2
1
* 9ns *
5.5MHz
t PCLK + 5%
100%
16ns (FńS+GND)
10pF
1
+ 9.1ns
5.5MHz
15pF
* 500ps + 57.3ns
As long as the set-up and hold time of the LCD driver are each less than 57 ns, the timing budget is met
sufficiently.
38
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Sep-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
SN65LVDS302ZQE
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQE
80
360
Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
SN65LVDS302ZQER
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQE
80
2500 Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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