ONSEMI NVMFS5830NL

NVMFS5830NL
Power MOSFET
40 V, 2.3 mW, 185 A, Single N−Channel
Features
•
•
•
•
•
Small Footprint (5x6 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low QG and Capacitance to Minimize Driver Losses
AEC−Q101 Qualified and PPAP Capable
These are Pb−Free Devices*
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V(BR)DSS
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
40
V
Gate−to−Source Voltage
VGS
± 20
V
ID
185
A
Continuous Drain Current RYJ−mb (Notes 1,
2, 3, 4)
Power Dissipation
RYJ−mb (Notes 1, 2, 3)
Continuous Drain Current RqJA (Notes 1, 3,
4)
Power Dissipation
RqJA (Notes 1 & 3)
Pulsed Drain Current
Tmb = 25°C
Steady
State
Tmb = 100°C
Tmb = 25°C
Steady
State
PD
ID
Operating Junction and Storage Temperature
Source Current (Body Diode)
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VGS = 10 V, IL(pk) = 85 A, L
= 0.1 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
W
158
A
29
PD
W
3.8
Junction−to−Ambient − Steady State (Note 3)
IDM
1012
A
TJ, Tstg
−55 to
+ 175
°C
IS
185
A
EAS
361
mJ
TL
260
°C
May, 2012 − Rev. 0
D
S
S
S
G
1
SO−8 FLAT LEAD
CASE 488AA
STYLE 1
A
Y
W
ZZ
V5830L
AYWZZ
D
D
D
= Assembly Location
= Year
= Work Week
= Lot Traceability
ORDERING INFORMATION
Symbol
Value
Unit
RYJ−mb
1.0
°C/W
RqJA
39
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi (Y) is used as required per JESD51−12 for packages in which
substantially less than 100% of the heat flows to single case surface.
3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
4. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2012
MARKING
DIAGRAM
1.9
THERMAL RESISTANCE MAXIMUM RATINGS
Junction−to−Mounting Board (top) − Steady
State (Notes 2, 3)
S (1,2,3)
N−CHANNEL MOSFET
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
Parameter
G (4)
20
TA = 100°C
TA = 25°C, tp = 10 ms
D (5,6)
79
TA = 100°C
TA = 25°C
185 A
3.6 mW @ 4.5 V
131
Tmb = 100°C
TA = 25°C
ID MAX
2.3 mW @ 10 V
40 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
RDS(ON) MAX
1
Package
Shipping†
NVMFS5830NLT1G
SO−8FL
(Pb−Free)
1500 /
Tape & Reel
NVMFS5830NLT3G
SO−8FL
(Pb−Free)
5000 /
Tape & Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy
and soldering details, please download the ON
Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Publication Order Number:
NVMFS5830NL/D
NVMFS5830NL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
40
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
32
VGS = 0 V,
VDS = 40 V
mV/°C
TJ = 25 °C
1
TJ = 125°C
100
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
±100
mA
nA
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
Forward Transconductance
RDS(on)
1.4
2.4
7.2
VGS = 10 V
ID = 20 A
1.7
2.3
VGS = 4.5 V
ID = 20 A
2.6
3.6
gFS
VDS = 5 V, ID = 10 A
V
mV/°C
38
mW
S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
5880
VGS = 0 V, f = 1 MHz, VDS = 25 V
750
pF
500
Total Gate Charge
QG(TOT)
VGS = 4.5 V, VDS = 32 V; ID = 60 A
58
nC
Total Gate Charge
QG(TOT)
VGS = 10 V, VDS = 32 V; ID = 60 A
113
nC
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Plateau Voltage
VGP
3.6
td(ON)
22
5.5
VGS = 4.5 V, VDS = 32 V; ID = 60 A
19.5
nC
32
V
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(OFF)
VGS = 4.5 V, VDS = 20 V,
ID = 10 A, RG = 2.5 W
tf
32
ns
40
27
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
Charge Time
Discharge Time
Reverse Recovery Charge
VSD
VGS = 0 V,
IS = 10 A
TJ = 25°C
0.74
TJ = 125°C
0.58
tRR
ta
tb
1.0
V
41
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 60 A
QRR
19
19
33
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
ns
nC
NVMFS5830NL
TYPICAL CHARACTERISTICS
5.5 V
10 V
350
4.4 V
4.2 V
ID, DRAIN CURRENT (A)
300
4.0 V
250
3.8 V
200
3.6 V
150
3.4 V
100
VGS = 3.2 V
50
TJ = 25°C
0
1
2
3
4
250
200
150
50
TJ = 125°C
TJ = −55°C
2
3
4
5
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.0035
0.010
ID = 20 A
TJ = 25°C
0.008
TJ = 25°C
0.0030
VGS = 4.5 V
0.0025
0.006
0.004
0.0020
0.002
VGS = 10 V
0.0015
0.000
0
2
4
6
8
0.0010
10
VGS, GATE−TO−SOURCE VOLTAGE (V)
0
25
50
75
100
125
150
175
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
100000
2.0
1.8
TJ = 25°C
100
0
5
VGS = 10 V
ID = 20 A
VGS = 0 V
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0
VDS ≥ 10 V
300
ID, DRAIN CURRENT (A)
350
1.6
1.4
1.2
1.0
TJ = 150°C
10000
TJ = 125°C
0.8
0.6
−50
−25
0
25
50
75
100
125
150
175
1000
10
20
30
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
40
NVMFS5830NL
TYPICAL CHARACTERISTICS
C, CAPACITANCE (pF)
7000
VGS, GATE−TO−SOURCE VOLTAGE (V)
8000
VGS = 0 V
TJ = 25°C
Ciss
6000
5000
4000
3000
2000
Coss
1000
0
Crss
0
10
20
30
40
8
6
Qgs
4
Qgd
2
VDS = 32 A
ID = 60 A
TJ = 25°C
0
0
10
20
30 40
50
60 70
80
90 100 110 120
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source Voltage vs. Total
Charge
175
100
IS, SOURCE CURRENT (A)
VDD = 20 V
ID = 10 A
VGS = 4.5 V
td(off)
tr
tf
td(on)
1
10
100
150
VGS = 0 V
TJ = 25°C
125
100
75
50
25
0
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
ID, DRAIN CURRENT (A)
t, TIME (ns)
QT
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
1000
10
10
10 ms
100
100 ms
1 ms
10
10 ms
1
0.1
0.01
0.1
VGS = 10 V
Single Pulse
TC = 25°C
RDS(on) Limit
Thermal Limit
Package Limit
dc
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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4
100
NVMFS5830NL
TYPICAL CHARACTERISTICS
RqJA(t) (°C/W) EFFECTIVE TRANSIENT
THERMAL RESISTANCE
100
Duty Cycle = 0.5
10
0.2
0.1
0.05
1 0.02
0.01
0.1
0.01
0.000001
Single Pulse
0.00001
0.0001
0.001
0.01
0.1
PULSE TIME (sec)
Figure 12. Thermal Response
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5
1
10
100
1000
NVMFS5830NL
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE G
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
0.20 C
D
2
A
B
D1
2X
0.20 C
4X
E1
2
3
q
E
2
1
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
c
A1
4
TOP VIEW
C
3X
e
0.10 C
SEATING
PLANE
DETAIL A
A
0.10 C
MILLIMETERS
MIN
NOM
MAX
0.90
1.00
1.10
0.00
−−−
0.05
0.33
0.41
0.51
0.23
0.28
0.33
5.15 BSC
4.50
4.90
5.10
3.50
−−−
4.22
6.15 BSC
5.50
5.80
6.10
3.45
−−−
4.30
1.27 BSC
0.51
0.61
0.71
1.20
1.35
1.50
0.51
0.61
0.71
0.05
0.17
0.20
3.00
3.40
3.80
0_
−−−
12 _
SOLDERING FOOTPRINT*
SIDE VIEW
8X
DETAIL A
b
0.10
C A B
0.05
c
1
4
K
4X
0.750
4X
1.000
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
e/2
L
3X
1.270
0.965
1.330
2X
0.905
2X
PIN 5
(EXPOSED PAD)
G
0.495
E2
L1
4.530
3.200
M
0.475
2X
D2
1.530
BOTTOM VIEW
4.560
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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NVMFS5830NL/D