TI UCC27222PWP

SLUS486B − AUGUST 2001 − REVISED JULY 2003
FEATURES
Maximizes Efficiency by Minimizing
APPLICATIONS
Non-Isolated Single or Multi-phased
Body-Diode Conduction and Reverse
Recovery Losses
Transparent Synchronous Buck Gate Drive
Operation From the Single Ended PWM Input
Signal
12-V or 5-V Input Operation
3.3-V Input Operation With Availability of
12-V Bus Bias
On-Board 6.5-V Gate Drive Regulator
±3.3-A TrueDrive Gate Drives for High
Current Delivery at MOSFET Miller
Thresholds
Automatically Adjusts for Changing
Operating Conditions
Thermally Enhanced 14-Pin PowerPAD
HTSSOP Package Minimizes Board Area and
Junction Temperature Rise
DC-to-DC Converters for Processor Power,
General Computer, Telecom and Datacom
Applications
DESCRIPTION
The UCC27221 and UCC27222 are high-speed
synchronous
buck
drivers
for
today’s
high-efficiency, lower-output voltage designs.
Using Predictive Gate Drive (PGD) control
technology, these drivers reduce diode
conduction and reverse recovery losses in the
synchronous
rectifier
MOSFET(s).
The
UCC27221 has an inverted PWM input while the
UCC27222 has a non-inverting PWM input.
Predictive Gate Drive technology uses control
loops which are stabilized internally and are
therefore transparent to the user. These loops use
no external components, so no additional design
is needed to take advantage of the higher
efficiency of these drivers.
FUNCTIONAL APPLICATION DIAGRAM
VIN
UCC27222
7
IN
VHI
14
PWMIN
6,8 GND
3
G1
13
VOUT
VDD
SW 11,12
4,5 VLO
G2
9,10
GNDOUT
GNDIN
Note: 12-V input system shown. For 5-V input only systems, see Figure 6.
This closed loop feedback system detects
body-diode conduction, and adjusts deadtime
delays to minimize the conduction time interval.
This virtually eliminates body-diode conduction
while adjusting for temperature, load- dependent
delays, and for different MOSFETs. Precise gate
timing at the nanosecond level reduces the
reverse recovery time of the synchronous rectifier
MOSFET body-diode, reducing reverse recovery
losses seen in the main (high-side) MOSFET. The
lower junction temperature in the low-side
MOSFET increases product reliability. Since the
power dissipation is minimized, a higher switching
frequency can also be used, allowing for smaller
component sizes.
The UCC27221 and UCC27222 are offered in the
thermally enhanced 14-pin PowerPAD package
with 2°C/W θjc.
Predictive Gate Drive and PowerPAD are trademarks of Texas Instruments Incorporated.
! "#$ ! %#&'" ($)
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Copyright  2002, Texas Instruments Incorporated
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1
SLUS486B − AUGUST 2001 − REVISED JULY 2003
PWP PACKAGE
(TOP VIEW)
N/C
N/C
VDD
VLO
PVLO
AGND
IN
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VHI
G1
SW
SWS
G2S
G2
PGND
N/C − No internal connection
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
−40C to 105C
PWM INPUT
(IN)
PowerPAD
HTSSOP−14 (PWP)
INVERTING
UCC27221PWP
NON-INVERTING
UCC27222PWP
The PWP package is available taped and reeled. Add R suffix to device type
(e.g. UCC27221PWPR) to order quantities of 2,000 devices per reel and 90
units per tube.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†}
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 to 20 V
Input voltage, VHI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
SW, SWS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Supply current, IDD, including gate drive current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 mA
Sink current (peak) pulsed, G1/G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 A
Source current (peak) pulsed, G1/G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −4.0 A
Analog input, IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −3.0 V to VDD + 0.3 V, not to exceed 15 V
Power Dissipation at TA = 25°C (PWP package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 W
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 115°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature soldering 1.6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltages are with respect to AGND and PGND. Currents are positive into, negative out of the specified terminal.
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SLUS486B − AUGUST 2001 − REVISED JULY 2003
ELECTRICAL CHARACTERISTICS
VDD = 12-V, 1-µF capacitor from VDD to GND, 1-µF capacitor from VHI to SW, 0.1-µF and 2.2-µF capacitor from PVLO to PGND, PVLO tied to
VLO, TA = −40C to 105C for the UCC2722x, TA = TJ (unless otherwise noted)
VLO regulator
PARAMETER
MIN
TYP
MAX
IVLO = 0 mA
IVLO = 0 mA
6.2
6.5
6.8
Regulator output voltage
VDD = 12 V,
VDD = 20 V,
6.2
6.5
6.8
IVLO = 100 mA
6.1
6.5
6.9
Line Regulation
VDD = 8.5 V,
VDD = 12 V to 20 V
2
10
15
40
Load Regulation
TEST CONDITIONS
Short-circuit current(1)
IVLO = 0 mA to 100 mA
VDD = 8.5 V
Dropout voltage, (VDD at 5% VLO drop)
VLO = 6.175 V,
220
IVLO = 100 mA
UNIT
V
mV
mA
7.1
7.8
8.5
MIN
TYP
MAX
V
undervoltage lockout
PARAMETER
Start threshold voltage
TEST CONDITIONS
3.30
3.82
4.40
Minimum operating voltage after start
Measured at VLO
3.15
3.70
4.25
Hysteresis
0.07
0.12
0.20
MIN
TYP
MAX
3.6
4.7
5.8
5.5
7.1
8.5
5.5
10
20
UNIT
V
bias currents
PARAMETER
VLO bias current at VLO (ON), 5 V applications only
TEST CONDITIONS
VLO = 4.5 V,
VDD = no connect
VDD = 8.5 V
VDD bias current
fIN = 500 kHz,
No load on G1/G2
UNIT
mA
input command (IN)
MIN
TYP
MAX
High-level input voltage
PARAMETER
10 V < VDD < 20 V
TEST CONDITIONS
3.3
3.6
3.9
Low-level input voltage
10 V < VDD < 20 V
2.2
2.5
2.8
Input bias current
VDD = 15 V
1
UNIT
V
µA
input (SWS)
PARAMETER
MIN
TYP
MAX
fIN = 500 kHz,
G2S = 0.0 V
tON, G2 maximum,
1.4
2.0
2.6
tON, G2 minimum,
Low-level input threshold voltage
fIN = 500 kHz,
G2S = 0.0 V
0.7
1.0
1.3
tON, G1 minimum
−100
−300
−500
mV
Input bias current
fIN = 500 kHz,
SWS = 0.0 V
−0.9
−1.2
−1.5
mA
UNIT
High-level input threshold voltage
TEST CONDITIONS
UNIT
V
input (G2S)
PARAMETER
MIN
TYP
MAX
High-level input voltage
fIN = 500 kHz,
SWS = 0.0 V
TEST CONDITIONS
tON, G2 maximum,
1.4
2.0
2.6
Low-level input voltage
fIN = 500 kHz,
SWS = 0.0 V
tON, G2 minimum,
0.7
1.0
1.3
Input bias current
G2S = 0 V
−370
−470
−570
V
µA
NOTE 1: Ensured by design. Not production tested.
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3
SLUS486B − AUGUST 2001 − REVISED JULY 2003
ELECTRICAL CHARACTERISTICS
VDD = 12-V, 1-µF capacitor from VDD to GND, 1-µF capacitor from VHI to SW, 0.1-µF and 2.2-µF capacitor from PVLO to PGND, PVLO tied to
VLO, TA = −40C to 105C for the UCC2722x, TA = TJ (unless otherwise noted)
G1 main output
MIN
TYP
MAX
Sink resistance
PARAMETER
SW = 0 V,
VHI = 6 V,
TEST CONDITIONS
IN = 0 V,
G1 = 0.5 V
0.3
0.9
1.5
Source resistance(2)
Source current(1)(2)
SW = 0 V,
VHI = 6 V,
IN = 6.5 V,
G1 = 5.5 V
10
25
45
SW = 0 V,
VHI = 6 V,
IN = 6.5 V,
G1 = 3.0 V
−3
−3.3
Sink current(1)(2)
SW = 0 V,
VHI = 6 V,
IN = 0 V,
G1 = 3.0 V
3
3.3
Rise time
C = 2.2 nF from G1 to SW,
Fall time
C = 2.2 nF from G1 to SW,
VDD = 20 V
VDD = 20 V
UNIT
Ω
A
17
25
17
25
MIN
TYP
MAX
5
15
30
35
ns
G2 SR output
PARAMETER
TEST CONDITIONS
Sink resistance(2)
PVLO = 6.5 V,
IN = 6.5 V,
G1 = 0.25 V
Source resistance(2)
Source current(1)(2)
PVLO = 6.5 V,
IN = 0 V,
G2 = 6.0 V
10
20
PVLO = 6.5 V,
IN = 0 V
G2 = 3.25 V
−3
−3.3
Sink current(1)(2)
Rise time(2)
PVLO = 6.5 V,
IN = 6.5 V
G2 = 3.25 V
3
3.3
C = 2.2 nF from G2 to PGND VDD = 20 V
17
25
Fall time
C = 2.2 nF from G2 to PGND VDD = 20 V
20
35
UNIT
Ω
A
ns
deadtime delay
MIN
TYP
MAX
tOFF, G2, IN to G2 falling
tOFF, G1, IN to G1 falling
PARAMETER
TEST CONDITIONS
60
80
100
55
80
110
Delay Step Resolution
3.5
4.1
4.7
tON, G1 minimum
tON, G1 maximum
−15
tON, G2 minimum
tON, G2 maximum
−21
UNIT
ns
48
38
NOTE 1: Ensured by design. Not production tested.
2: The pullup / pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors. The output resistance is the RDS(ON) of the MOSFET transistor when the
voltage on the driver output is less than the saturation voltage of the bipolar transistor.
tOFF,G1
3.25 V
UCC27222
IN
tOFF,G2
tON,G1
tON,G2
90%
10%
G1
G2
90%
10%
Figure 1. Predictive Gate Drive Timing Diagram
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UDG−01042
SLUS486B − AUGUST 2001 − REVISED JULY 2003
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
DESCRIPTION
I/O
AGND
6
−
Analog ground for all internal logic circuitry. AGND and PGND should be tied to the PCB ground plane
with vias.
G1
13
O
High-side gate driver output that swings between SW and VHI.
G2
9
O
Low-side gate driver output that swings between PGND and PVLO.
G2S
10
I
Used by the predictive deadtime controller for sensing the SR MOSFET gate voltage to set the
appropriate deadtime.
IN
7
I
Digital input command pin. A logic high forces on the main switch and forces off the synchronous
rectifier.
PGND
8
−
Ground return for the G2 driver. Connect PGND to PCB ground plane with several vias.
PVLO
5
I
PVLO supplies the G2 driver. Connect PVLO to VLO and bypass on the PCB.
SW
12
−
G1 driver return connection.
SWS
11
I
Used by the predictive controller to sense SR body-diode conduction. Connect to SR MOSFET drain
close to the MOSFET package.
VDD
3
I
Input to the internal VLO regulator. Nominal VDD range is from 8.5 V to 20 V. Bypass with at least
0.1 µF of capacitance.
VHI
14
I
Floating G1 driver supply pin. VHI is fed by an external Schottky diode during the SR MOSFET on-time.
Bypass VHI to SW with an external capacitor.
VLO
4
O
Output of the VLO regulator and supply input for the logic and control circuitry. Connect VLO to PVLO and
bypass on the PCB.
SIMPLIFIED BLOCK DIAGRAM
N/C
1
N/C
2
VDD
3
VLO
4
14 VHI
13 G1
VLO
12 SW
VLO
REGULATOR
11 SWS
PREDICTIVE
DELAY
CONTROLLER
+
3.82 V/ 3.7 V
10 G2S
UVLO
PVLO
5
PVLO
PVLO
UCC27221
AGND
IN
6
7
9
G2
8
PGND
UCC27222
UDG−01030
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SLUS486B − AUGUST 2001 − REVISED JULY 2003
APPLICATION INFORMATION
predictive gate drive technique
The Predictive Gate Drive technology utilizes a digital feedback system to detect body-diode conduction, and
then adjusts the deadtime delays to minimize it. This system virtually eliminates the body-diode conduction time
intervals for the synchronous MOSFET, while adjusting for different MOSFETs characteristics, propagation and
load dependent delays. Maximum power stage efficiency is the end result.
Two internal feedback loops in the predictive delay controller continuously adjusts the turn on delays for the two
MOSFET gate drives G1 and G2. As shown in Figure 2, tON,G1 and tON,G2 are varied to provide minimum
body-diode conduction in the synchronous rectifier MOSFET Q2. The turn-off delay for both G1 and G2, tOFF,G1
and tOFF,G2 are fixed by propagation delays internal to the device.
The predictive delay controller is implemented using a digital control technique, and the time delays are
therefore discrete. The turn-on delays, tON, G1 and tON, G2, are changed by a single step (typically 3 ns) every
switching cycle. The minimum and maximum turn-on delays for G1 and G2 are specified in the electrical
characteristics table.
UCC27221
tOFF,G1
3.25 V
IN
3.25 V
UCC37222
tOFF,G2
tON,G1
tON,G2
90%
10%
G1
G2
90%
10%
Figure 2. Predictive Gate Drive Timing Diagram
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SLUS486B − AUGUST 2001 − REVISED JULY 2003
APPLICATION INFORMATION
A typical application circuit for systems with 8.5-V to 20-V input is shown in Figure 3.
VIN
D1
CIN
C2
PWM
Input
N/C
UCC27222 VHI
N/C
G1
VDD
SW
VLO
SWS
PVLO
G2S
AGND
G2
IN
R1
Q1
L1
C1
V OUT
Q2
Cout
PGND
GND
GND
Figure 3. System Application: 8.5-V to 20-V Input
selection of VHI series resistor R1 (dV/dt Considerations):
The series resistor R1 may be needed to slowdown the turn-on of the main forward switch to limit the dV/dt which
can inadvertently turn on the synchronous rectifier switch. In nominal 12-V input designs, a R1 value of 4-Ω to
10-Ω can be used depending on the type of MOSFET used and the high-side/low-side MOSFET ratio. In 5-V
or lower input applications however, R1 is not needed.
When the drain-source voltage of a MOSFET quickly rises, inadvertent dV/dt induced turn-on of the device is
possible. This can especially be a problem for input voltages of 12 V or greater. As Q1 rapidly turns on, the
drain-to-source voltage of Q2 rises sharply, resulting in a dV/dt voltage spike appearing on the gate signal of
Q2. If the dV/dt induced voltage spike were to exceed the given threshold voltage, the MOSFET may briefly
turn on when it should otherwise be commanded off. Obviously this undesired event would have a negative
impact on overall efficiency.
Minimizing the dV/dt effect on Q2 can be accomplished by proper MOSFET selection and careful layout
techniques. The details of how to select a MOSFET to minimize dV/dt susceptibility are outlined in SEM−1400,
Topic 2, Appendix A, Section A5. Secondly, the switch node connecting Q1, Q2 and L1 should be laid out as
tight as possible, minimizing any parasitic inductance, which might worsen the dV/dt problem.
If the dV/dt induced voltage spike is still present on the gate Q2, a 4W to 10W value of R1 is recommended to
minimize the possibility of inadvertently turning on Q2. The addition of R1 slows the turn-on of Q1, limiting the
dV/dt rate appearing on the drain-to-source of Q2. Slowing down the turn-on of Q1 will result in slightly higher
switching loss for that device only, but the efficiency gained by preventing dV/dt turn-on of Q2 will far outweigh
the negligible effect of adding R1.
When Q2 is optimally selected for dV/dt robustness and careful attention is paid to the PCB layout of the switch
node, R1 may not be needed at all, and can therefore be replaced with a 0-Ω jumper to maintain high efficiency.
The goal of the designer should not be to completely eliminate the dV/dt turn-on spike but to assure that the
maximum amplitude is less than the MOSFET gate-to-source turn-on threshold voltage under all operating
conditions.
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SLUS486B − AUGUST 2001 − REVISED JULY 2003
APPLICATION INFORMATION
selection of bypass capacitor C1
Bypass capacitors should be selected based upon allowable ripple voltage, usually expressed as a percent of
the regulated power supply rail to be bypassed. In all of the UCC27222 application circuits shown herein, C1
provides the bypass for the main (high-side) gate driver. Every time Q1 is switched on, a packet of charge is
removed from C1 to charge Q1’s gate to approximately 6.0 V. The charge delivered to the gate of Q1 can be
found in the manufacturer’s datasheet curves. An example of a gate charge curve is shown in Figure 4.
GATE-TO-SOURCE VOLTAGE
vs
TOTAL GATE CHARGE
VGS − Gate-to-Source Voltage − V
8
6
4
2
31 nC
0
0
10
20
30
40
Q6 − Total Gate Charge − nC
Figure 4.
As shown in Figure 4, 31 nC of gate charge is required in order for Q1’s gate to be charged to 6.0 V, relative
to its source. The minimum bypass capacitor value can be found using the following calculation:
C1 MIN +
QG
k
ǒVHI * VSWǓ
(1)
where k is the percent ripple on C1, QG is the total gate charge required to drive the gate of Q1 from zero to
the final value of (VHI−VSW). In this example gate charge curve, the value of the quantity (VHI−VSW) is taken
to be 6.0 V. This value represents the nominal VLO regulator output voltage minus the forward voltage drop of
the external Schottky diode, D1. For the MOSFET with the gate charge described in Figure 4, the minimum
capacitance required to maintain a 3% peak-to-peak ripple voltage can be calculated to be 172 nF, so a 180-nF
or a 220-nF capacitor could be used. The maximum peak-to-peak C1 ripple must be kept below 0.4 V for proper
operation.
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SLUS486B − AUGUST 2001 − REVISED JULY 2003
APPLICATION INFORMATION
selection of MOSFETs
The peak current rating of a driver imposes a limit on the maximum gate charge of the external power MOSFET
driven by it. The limit is based on the amount of time needed to deliver or remove the required charge to achieve
the desired switching speed during turn-on and turn-off of the external transistor. Hence, there are the families
of gate driver circuits with different current ratings.
To demonstrate this, assume a constant time interval for the switching transition and a fixed gate drive
amplitude. A larger MOSFET with more gate charge will require higher current capability from the driver to
turn-on or turn-off the device in the same amount of time. Accordingly, there is a practical upper limit on gate
charge which can be driven by the UCC27222 family of drivers. Considering the current capability of the
TrueDrive output stage and the available dynamic range (delay adjust range) of the Predictive Gate Drive
circuitry, this limit is approximately 120 nC of gate charge.
Some higher current applications require several MOSFETs to be connected parallel and driven by the same
gate drive signal. If their combined gate charge exceeds 120 nC, the rise and fall times of the gate drive signals
will extend and limit the delay adjust range of the PGD circuit in the UCC27222. This may limit the benefits of
the PGD technology under certain operating conditions.
Note that there are additional considerations in the gate drive circuit design which influence the maximum gate
charge of the external MOSFETs. The most significant of these is the operating frequency which, together with
the amount of gate charge, will define the power dissipation in the driver. The allowable power dissipation is a
function of the maximum junction and operating temperatures, thermal and reliability considerations.
selection of bypass capacitor C2
C2 supplies the peak current required to turn on the Q2 synchronous rectifier MOSFET, as well as the peak
current to charge the C1 capacitor through the bootstrap diode. Since the synchronous MOSFET is turned on
with 0 V across its drain-to-source, there is no Miller, or gate-to-drain charge. Therefore the synchronous
MOSFET gate can be modeled as a simple linear capacitance. The value of this capacitance can be found from
the datasheet’s gate charge curve. Referring to Figure 5, the slope of the curve past the Miller plateau indicates
the equivalent gate capacitance. Because the Y-axis is described in volts, the capacitance is actually the inverse
of the slope of the curve. For example, the curve in Figure 4 has a slope of approximately 2 V / 12 nC over the
gate charge range of 10 nC to 40 nC. The equivalent capacitance is 12 nC / 2 V = 6 nF. With the equivalent
capacitance, the minimum bypass capacitor value can be calculated as:
C2 MIN +
C EQ
(2)
k
where
CEQ is the equivalent gate capacitance,
k is the voltage ripple on C2, expressed as a percentage
For a peak-to-peak ripple of 3%, the minimum C2 capacitor value is calculated to be 200 nF. A 220-nF capacitor
would be used in this case.
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SLUS486B − AUGUST 2001 − REVISED JULY 2003
APPLICATION INFORMATION
regulator current and power dissipation
The regulator current can be calculated from the dc or average current required by the two gate drivers. This
current can be expressed as:
I REG + F SW
ǒCEQ
VLO ) Q GǓ
(3)
Assuming all the power dissipation is internal to the device, and the internal bias current is negligible, the power
dissipated by the device is:
P DIS + F SW
ǒCEQ
VLO ) Q GǓ
VDD
(4)
For a 500-kHz design, using MOSFETs with the gate charge characteristics shown in Figure 4 for both Q1 and
Q2, the average regulator current would be 35 mA, and, when operated from a 12-V input rail, the resulting
power dissipation is calculated to be 420 mW.
systems using 3.3-V or 5-V power input and 12-V gate drive
Figure 5 shows a schematic for systems where the power bus input is 5 V and 12 V is available for powering
the gate drives. This system provides the 6.5-V gate drive to both MOSFETs, while the power stage operates
off the 3.3-V or 5-V bus.
+3.3 V
or +5V
D1
UCC27222
N/C
CIN
R1
VHI
+12 V
C3
C2
PWM
Q1
G1
N/C
VDD
SW
VLO
SWS
PVLO
G2S
AGND
G2
IN
L1
C1
V OUT
Q2
Cout
PGND
Input
GND
GND
Figure 5. System Application: 3.3-V or 5-V Power Input with 12 V Available for Gate Drive
Note that the series resistor R1 may be needed to slowdown the turn-on of the main forward switch to limit the
dV/dt which can inadvertently turn on the synchronous rectifier switch. The dV/dt considerations and the
selection of R1 are discussed in the previous section.
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SLUS486B − AUGUST 2001 − REVISED JULY 2003
APPLICATION INFORMATION
systems with 5-V input only
The circuit pictured in Figure 6 starts up from a 5-V input bus and provides a 6.5-V gate drive to the power
MOSFETs. This circuit uses a charge pump consisting of D3, D4 and C3 to effectively double the input voltage
and apply this to the input of the linear regulator. The regulator then regulates the doubled input voltage to the
6.5-V nominal for VLO.
D3
D4
+5V
D1
C3
D2
CIN
UCC27222
N/C
C2
PWM
Input
Q1
G1
N/C
C4
VHI
VDD
SW
VLO
SWS
PVLO
G2S
AGND
G2
IN
L1
C1
V OUT
Q2
Cout
PGND
GND
GND
Figure 6. System Application: 5-V-Only Power Input with 6.5-V Gate Drive Using Charge Pump Circuit
www.ti.com
11
SLUS486B − AUGUST 2001 − REVISED JULY 2003
APPLICATION INFORMATION
selecting D2, D3, and D4
Selection of suitable diodes is based upon the conducted peak and average currents. D2 simply provides a path
to charge C2 at converter power-up. Virtually any one of the common BAT54 series of Schottky diodes can be
used. To select D3 and D4, the peak currents of these two diodes need to be taken into account. First, the
average current flowing in both D3 and D4 is the same as the regulator current described in equation (3). The
peak currents in D3 and D4 are described as:
I D3PK +
I REG
1*D
(5)
I D4PK +
I REG
D
(6)
For most UCC27222 applications, the duty cycle is much less than 50%, and the peak current in D3 is quite
reasonable. However, the peak current in D4 is quite high. This high peak current requires using a diode with
a higher current rating for D4.
To maintain a reasonable charge pump efficiency, BAT54-type diodes can be used for applications where the
peak currents are below approximately 40 mA. For applications where the peak current is greater than 40 mA,
a 350-mA or 500-mA diode should be used. A typical 350-mA diode is SD103CW, SOD−123 package,
manufactured by Diodes Inc. A typical 500-mA diode is the ZHCS500, SOT−23 package, available from Zetex
Inc.
selection of the flying capacitor C3
The flying capacitor is subjected to large peak currents, and to keep the peak-to-peak ripple voltage low, this
capacitor has to be larger than C1 and C2. Selection of C3 should be done based on allowable peak-to-peak
ripple on C3:
C3 MIN +
I REG
F SW
k
ǒVIN * VFD3Ǔ
(7)
where IREG is the regulator output current, FSW is the switching frequency, k is the percent ripple on C3, and
VFD2 is the forward drop of D3.
selection of bypass capacitor C4
The bypass capacitor C4 needs to be sized to take the peak current from the charge pump diode D4. The
capacitor is sized based on allowable ripple voltage:
C MIN +
I REG
F
SW
k
ǒ2
(1 * D)
VIN * V FD3 * V FD4Ǔ
where VFD3 and VFD4 are the forward voltages of D3 and D4 and k is the percent ripple allowed on C4.
12
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(8)
SLUS486B − AUGUST 2001 − REVISED JULY 2003
APPLICATION INFORMATION
synchronous rectification and predictive delay
In a normal buck converter, when the main switch turns off, current is flowing to the load in the inductor. This
current cannot be stopped immediately without using infinite voltage. For the current path to flow and maintain
voltage levels at a safe level, a rectifier or catch device is used. This device can be either a conventional diode,
or it can be a controlled active device if a control signal is available to drive it. The UCC27222 provides a signal
to drive an N-channel MOSFET as a rectifier. This control signal is carefully coordinated with the drive signal
for the main switch so that there is minimum delay from the time that the rectifier MOSFET turns off and the main
switch turns on, and minimum delay from when the main switch turns off and the rectifier MOSFET turns on.
This scheme, Predictive Gate Drive delay, uses information from the current switching cycle to adjust the
delays that are to be used in the next cycle. Figure 7 shows the switch-node voltage waveform for a
synchronously rectified buck converter. Illustrated are the relative effects of a fixed-delay drive scheme
(constant, pre-set delays for the turnoff to turn on intervals), an adaptive delay drive scheme (variable delays
based upon voltages sensed on the current switching cycle) and the predictive delay drive scheme.
Note that the longer the time spent in body-diode conduction during the rectifier conduction period, the lower
the efficiency. Also, not described in Figure 7 is the fact that the predictive delay circuit can prevent the body
diode from becoming forward biased at all while at the same time avoiding cross conduction or shoot through.
This results in a significant power savings when the main MOSFET turns on, and minimizes reverse recovery
loss in the body diode of the rectifier MOSFET.
The power dissipation on the main (forward) MOSFET is reduced as well, although that savings is not as
significant as the savings in the rectifier MOSFET.
During reverse recovery the body diode is still forward biased, thus the reverse recovery current goes through
the forward MOSFET while the drain−source voltage is still high, causing additional switching losses. Without
PGD during this switching transition, Vds = Vin and Ids = Iload + Irr in the main MOSFET. With PGD however,
Vds = Vin and Ids = Iload. The reduction in current accounts for additional power savings in the main MOSFET.
VIN
0V
VD
GND
Channel Conduction
Body Diode Conduction
Fixed Delay
Adaptive Delay
Predictive Delay
UDG−02175
Figure 7. Switch Node Waveforms for Synchronous Buck Converter
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13
SLUS486B − AUGUST 2001 − REVISED JULY 2003
APPLICATION INFORMATION
comparison between predictive and adaptive gate drive techniques
The first synchronous rectifier controllers had a fixed turn-on delay between the two gate drivers. The advantage
of this well-known technique is its simplicity. The drawbacks include the need to make the delay times long
enough to cover the entire application of the device and the temperature and lot-to-lot variation of the time delay.
Since the body-diode of the synchronous rectifier conducts during this deadtime, the efficiency of this technique
varies with different MOSFETs, ambient temperature, and with the lot-to-lot variation of the deadtime delay.
To combat the variability of the internal time delays, second generation controllers used state information from
the power stage to control the turn-on of the two gate drivers. This technique is usually referred to as adaptive
gate drive technique and is pictured in FIgure 8.
+
ON
VIN
+
ON
OFF
VOUT
UDG−01031
Figure 8. Adaptive Gate Drive Technique
The main advantage of the adaptive technique is the on-the-fly delay adjustment for different MOSFETs and
temperature-variable time delays. The disadvantages include the body-diode conduction time intervals caused
by delays in the cross-coupling loops and the inability to compensate for the delay to charge the MOSFET gates
to the threshold levels. Additionally, it is difficult to determine whether the synchronous MOSFET channel is off
by solely monitoring the SR MOSFET gate voltage. Some devices actually add a programmable delay between
the turn-off of the synchronous rectifier and the turn-on of the main MOSFET via an external capacitor. This
added delay directly affects the power stage efficiency through additional body-diode conduction losses. Since
these losses are centralized in the synchronous MOSFET, the stress and temperature rise in this component
becomes a major design headache.
The third-generation predictive control technique is different from the adaptive technique in that it uses
information from the previous switching cycle to set the deadtime for the current cycle. The adaptive technique
on the other hand uses the current state information to set the delay times. The inherent feedback loop
propagation delays cause body-diode conduction.
14
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SLUS486B − AUGUST 2001 − REVISED JULY 2003
APPLICATION INFORMATION
adaptive vs. predictive waveforms
Figures 9 through 11 illustrate the adaptive (left) vs. predictive (right) switching waveforms. Key comparison
regions are denoted with (A), (B), (C), (D), and (E) for the adaptive control waveforms and (A′), (B′), (C′), (D′),
and (E′) for the predictive control waveforms. Figures 10 and 11 are close-ups of each transition edge.
At (A), the propagation delay from sensing the synchronous rectifier gate going low to the high-side gate going
high results in approximately 60 ns of body-diode conduction shown at (B). With the predictive drive, as soon
as the body-diode conduction of the SR MOSFET (B) is sensed, the high-side turn-on delay is adjusted to
minimize the body-diode conduction time (B′).
At (A′), the high side gate-to-source voltage is increasing while the synchronous rectifier gate-to-source voltage
is decreasing. A natural result of the precise timing of the high-side MOSFET turn-on is shown at (C) and (C′).
The overshoot and ringing for the predictive drive (C′) has much smaller amplitude than the adaptive drive (C)
due a reduction in reverse recovery in the SR MOSFET body diode. This reduction in reverse recovery is only
possible with the extremely precise gate timing used in the predictive drive technique.
At (D), the propagation delay from the synchronous rectifier drain-to-source voltage falling to the gate-to-source
voltage rising causes the body diode of the SR MOSFET to conduct for approximately 60 ns (E). When the
predictive drive is enabled (D′), the inherent delay is eliminated and virtually no body-diode conduction is shown
at (E′).
D
A
Complementary
Gate Drive
Waveforms
2 V / div
A4
C
D4
C4
E
B
VDS of SR
MOSFET
Switch
2 V / div
B4
E4
Predictive Drive
100 ns / div
Adaptive Drive
100 ns / div
Figure 9. Adaptive vs. Predictive Switching Waveforms
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15
SLUS486B − AUGUST 2001 − REVISED JULY 2003
APPLICATION INFORMATION
A4
A
C
B
Complementary
Gate Drive
Waveforms
2 V / div
C4
VDS of SR
MOSFET
Switch
2 V / div
B4
Adaptive Drive
20 ns / div
Predictive Drive
20 ns / div
Figure 10. Close-Up: Turn-Off of Synchronous Rectifier Switch to Turn-On of Main Switch
D
E
Complementary
Gate Drive
Waveforms
2 V / div
VDS of SR
MOSFET
Switch
2 V / div
Adaptive Drive
20 ns / div
D4
E4
Predictive Drive
20 ns / div
Figure 11. Close-Up: Turn-Off of Main Switch to Turn-On of Synchronous Rectifier Switch
efficiency comparison
Figures 12 through 15 show a series of efficiency measurements taken at two output voltages (0.9 V and 1.8
V) and two switching frequencies (250 kHz and 500 kHz) for both predictive and adaptive delay techniques.
The efficiency gain using the predictive technique is 1% for a VOUT level of 1.8 V and at a switching frequency
of 250 kHz (Figure 12). Figures 13 and 14 show the efficiency gain approximately doubles when VOUT is lowered
by a factor of two (to 0.9 V), or when the switching frequency is doubled to 500 kHz. With both doubled frequency
and one-half of the output voltage, the efficiency gain of predictive technology is about 4% over the adaptive
technology (Figure 15). Therefore, as the switching frequency increases and output voltages are lowered, the
efficiency gains are higher. This results in lower operational temperatures for increased reliability as well as
smaller size designs for increased frequencies.
16
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SLUS486B − AUGUST 2001 − REVISED JULY 2003
APPLICATION INFORMATION
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
OUTPUT CURRENT
0.5
ADAPTIVE
0.3
86
84
0.2
82
DELTA POWER
DISSIPATION
78
0.1
74
0
5
10
15
IOUT − Output Current − A
PREDICTIVE
88
0.3
86
ADAPTIVE
84
0.2
82
80
76
0.0
74
20
0.0
0
5
10
15
IOUT − Output Current − A
96
EFFICIENCY
vs
OUTPUT CURRENT
96
1.2
1.0
ADAPTIVE
86
0.6
DELTA POWER
DISSIPATION
82
0.4
80
78
VIN = 5 V
VOUT = 1.8 V
fSW = 500 kHz
76
74
0
5
10
15
0.2
90
Efficiency − %
0.8
92
Delta Power Dissipation − W
PREDICTIVE
90
Efficiency − %
1.2
VIN = 5 V
VOUT = 0.9 V
fSW = 500 kHz
94
94
84
20
Figure 13
EFFICIENCY
vs
OUTPUT CURRENT
88
0.1
DELTA POWER
DISSIPATION
Figure 12
92
0.4
90
78
VIN = 5 V
VOUT = 1.8 V
fSW = 250 kHz
76
92
Efficiency − %
Efficiency − %
90
Delta Power Dissipation − W
0.4
80
VIN = 5 V
VOUT = 0.9 V
fSW = 250 kHz
94
PREDICTIVE
92
88
0.5
96
PREDICTIVE
0.8
88
86
0.6
84
82
ADAPTIVE
0.4
80
0.2
78
76
0.0
20
1.0
DELTA POWER
DISSIPATION
74
IOUT − Output Current − A
Delta Power Dissipation − W
94
Delta Power Dissipation − W
96
0
5
10
15
IOUT − Output Current − A
0.0
20
Figure 15
Figure 14
www.ti.com
17
SLUS486B − AUGUST 2001 − REVISED JULY 2003
LAYOUT CONSIDERATIONS
packaging
The UCC27221/2 are only available in TI’s thermally enhanced 14-pin PowerPad package. This package
offers exceptional thermal impedance with a junction-to-case rating of 2C/W. Shown as the crosshatched
region in Figure 16, PowerPad includes an exposed leadframe die pad located on the bottom side of the
package. Exposed pad dimensions for the PowerPad TSSOP 14-pin package are 69 mils x 56 mils (1.8 mm
x 1.4 mm). However, the exposed pad tolerances can be + 41 / − 2 mils (+ 1.05 /− .05 mm) due to position and
mold flow variation. Effectively removing the heat from the PowerPAD package requires a thermal land area,
shown as the shaded gray region in Figure 16, designed into the PCB directly beneath the package. A minimum
thermal land area of 5 mm by 3.4 mm is recommended as illustrated in Figure 16. Any tolerance variances of
the exposed PowerPad falls well within the thermal land area when the recommended minimum land area
is included on the printed circuit board. In addition, a 2-by-3 array of 13-mil thermal vias is required within the
exposed PowerPad area, as shown in Figure 16. If additional heat sinking capability is required, larger 25-mil
vias can be added to the thermal land area.
Required Vias on PowerPad Area
2 x 3 Array
0.33mm
(13 mil) dia Vias
3.4mm
(0.1339”)
0.65mm
(0.0256”)
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
0.3mm
(0.0118”)
1.05mm
(0.0413”)
Exposed
PowerPad
1.8mm (0.069”)
5.0mm
(0.1968”)
Optional Vias on Thermal Land Area
0.635mm
(25 mil) dia Vias
Exposed
PowerPad
1.4mm (0.056”)
Figure 16. TSSOP−14PWP Package Outline and Minimum PowerPADE PCB Thermal Land
18
www.ti.com
SLUS486B − AUGUST 2001 − REVISED JULY 2003
REFERENCE DESIGN AND EVALUATION MODULE
A reference design is discussed in, 12 V to 1.8 V, 20-A High Efficiency Synchronous Buck Converter Using the
UCC27222 with Predictive Gate Drive, TI Literature Number SLUU140 and accompanying evaluation module
(EVM) SLUP192. The design highlights UCC27222 and its Predictive Gate Drive synchronous buck operation
using a simple single ended PWM controller. The schematic is shown in Figure 17.
Figure 17. Typical Application Diagram
www.ti.com
19
SLUS486B − AUGUST 2001 − REVISED JULY 2003
TYPICAL CHARACTERISTICS
UVLO THRESHOLD
vs
TEMPERATURE
16
4.2
14
4.1
4.0
IDD: VDD = 12 V, 500 kHz
12
10
8
IDD: VDD = 8.5 V, Static
6
IVLO: VLO = 12 V, Static, 5 V Only Systems
UVLO On
3.9
UVLO Threshold − V
ISUPPLY − Bias Current − mA
BIAS CURRENT
vs
TEMPERATURE (NO LOAD)
3.8
3.7
UVLO Off
3.6
3.5
4
3.4
2
3.3
0
3.2
−50
−25
0
25
50
75
100
125
−50
−25
50
TA − Temperature − °C
Figure 18
Figure 19
6.8
6.8
6.7
6.7
6.6
VDD = 20 V
6.5
75
100
125
VLO LOAD REGULATION
vs
TEMPERATURE
VLO − Load Regulation − V
VLO − Line Regulation − V
25
TA − Temperature − °C
VLO LINE REGULATION
vs
TEMPERATURE (NO LOAD, IVLO = 0 mA)
VDD = 12 V
6.4
6.3
6.6
IVLO = 0 mA
6.5
IVLO = 100 mA
6.4
6.3
6.2
6.2
−50
−25
0
25
50
75
100
125
TA − Temperature − °C
−50
−25
0
25
50
TA − Temperature − °C
Figure 20
20
0
Figure 21
www.ti.com
75
100
125
SLUS486B − AUGUST 2001 − REVISED JULY 2003
TYPICAL CHARACTERISTICS
DROPOUT VOLTAGE (VDD AT VLO = 6.175 V)
vs
TEMPERATURE (IVLO = 100 mA)
8.6
8.6
8.4
8.4
VDD − Dropout Voltage − V
VDD − Dropout Voltage − V
DROPOUT VOLTAGE (VDD AT VLO = 6.175 V)
vs
OUTPUT CURENT
8.2
8.0
7.8
7.6
8.2
8.0
7.8
7.6
7.4
7.4
7.2
7.2
7.0
7.0
0
50
IVLO − VLO Output Current − mA
−50
100
−25
0
25
50
75
100
125
TA − Temperature − °C
Figure 22
Figure 23
VLO SHORT CIRCUIT CURRENT
vs
TEMPERATURE
INPUT THRESHOLD
vs
TEMPERATURE (VDD = 10 V TO 20 V)
4.0
300
Input Threshold Rising
3.5
280
3.0
270
Input Threshold − V
VLO − Short Circuit Current − mA
290
260
250
240
230
Input Threshold Falling
2.5
2.0
1.5
Input Threshold Hyst.
1.0
220
0.5
210
200
−50
0.0
−25
0
25
50
75
100
125
−50
−25
0
25
50
TA − Temperature − °C
TA − Temperature − °C
Figure 24
Figure 25
www.ti.com
75
100
125
21
SLUS486B − AUGUST 2001 − REVISED JULY 2003
TYPICAL CHARACTERISTICS
PROPAGATION DELAYS
vs
TEMPERATURE
4.7
120
4.5
100
tPROP − Propagation Delays − ns
PGD Step Resolution − ns
PREDICTIVE DELAY BIT WEIGHT
vs
TEMPERATURE
4.3
4.1
3.9
tOFF, G2
80
tOFF, G1
60
40
3.7
20
3.5
0
−50
−25
0
25
50
75
100
−50
125
−25
TA − Temperature − °C
PREDICTIVE DELAY RANGE
vs
TEMPERATURE
100
125
50
tON, G1 Max
20
10
0
tON, G1 Min
−10
40
tON − G2 Delay Range − ns
tON − G1 Delay Range − ns
125
60
tON, G2 Max
30
20
10
0
tON, G2 Min
−10
−20
−20
−30
−30
−25
0
25
50
75
100
125
TA − Temperature − °C
−50
−25
0
25
50
TA − Temperature − °C
Figure 28
22
100
PREDICTIVE DELAY RANGE
vs
TEMPERATURE
30
−50
75
Figure 27
50
40
50
TA − Temperature − °C
Figure 26
60
25
0
Figure 29
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75
SLUS486B − AUGUST 2001 − REVISED JULY 2003
TYPICAL CHARACTERISTICS
G1 RISE AND FALL TIMES
vs
TEMPERATURE (2.2 nF)
G2 RISE AND FALL TIMES
vs
TEMPERATURE (2.2 nF)
30
30
25
25
Fall Time
20
20
G2 tR, tF − ns
G1 tR, tF − ns
Rise Time
15
Fall Time
15
Rise Time
10
10
5
5
0
0
−50
−25
25
0
50
75
100
−50
125
−25
0
25
50
TA − Temperature − °C
TA − Temperature − °C
Figure 30
Figure 31
G1 SINK RESISTANCE
vs
TEMPERATURE (RDS(on))
75
100
125
G1 SOURCE RESISTANCE
vs
TEMPERATURE
1.5
40
1.4
35
1.3
30
G1 RSOURCE − Ω
G1 RSINK − Ω
1.2
1.1
1.0
0.9
25
20
15
0.8
10
0.7
5
0.6
0
0.5
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
TA − Temperature − °C
TA − Temperature − °C
Figure 32
Figure 33
www.ti.com
75
100
125
23
SLUS486B − AUGUST 2001 − REVISED JULY 2003
TYPICAL CHARACTERISTICS
G2 SOURCE RESISTANCE
vs
TEMPERATURE
G2 SINK RESISTANCE
vs
TEMPERATURE (RDS(on))
40
40
35
35
30
G2 RSOURCE − Ω
G2 RSINK − Ω
30
25
20
15
25
20
15
10
10
5
5
0
0
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TA − Ambient Temperature − °C
TA − Temperature − °C
Figure 34
Figure 35
RELATED PRODUCTS
PART
NUMBER
DESCRIPTION
GATE
DRIVE
PACKAGE
TPS2830/1
Fast synchronous buck MOSFET drivers with dead-time control
± 2.4 A
PowerPAD HTSSOP−14, SOIC−14
TPS2832/3
Fast synchronous buck MOSFET drivers with dead-time control
± 2.4 A
SOIC−8
TPS2834/5
Synchronous buck MOSFET drivers with dead-time control
± 2.4 A
PowerPAD HTSSOP−14, SOIC−14
TPS2836/7
Synchronous buck MOSFET drivers with dead-time control
± 2.4 A
SOIC−8
TPS2838/9
Synchronous buck MOSFET drivers with drive regulator
±4A
PowerPAD HTSSOP−16
TPS2848/9
Synchronous buck MOSFET drivers with drive regulator
±4A
PowerPAD HTSSOP−14
±1A
PowerPAD MSOP−10
TPS40000/1/2/3 Low input voltage mode synchronous buck controller with predictive
gate drive
REFERENCES
1. Power Supply Design Seminar SEM−1400 Topic 2: Design and Application Guide for High Speed MOSFET
Gate Drive Circuits, by Laszlo Balogh, Texas Instruments Literature Number SLUP169.
2. Power Supply Design Seminar SEM−1400 Topic 7: Implication of Synchronous Rectifiers in Isolated,
Single-Ended, Forward Converters, by Christopher Bridge, Texas Instruments Literature Number
SLUP175.
3. 12 V to 1.8 V, 20 A High-Efficiency Synchronous Buck Converter Using UCC27222 With Predictive Gate
Drive] Technology, TI Literature Number SLUU140.
24
www.ti.com
/011/
01
SLUS486B − AUGUST 2001 − REVISED JULY 2003
PowerPAD PLASTIC SMALL−OUTLINE
PWP (R−PDSO−G14)
www.ti.com
25
SLUS486B − AUGUST 2001 − REVISED JULY 2003
MECHANICAL DATA
PWP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE
20 PINS SHOWN
0,30
0,19
0,65
20
0,10 M
11
Thermal Pad
(See Note F)
4,50
4,30
0,15 NOM
6,60
6,20
Gage Plane
1
10
0,25
A
0°−ā 8°
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
14
16
20
24
28
A MAX
5,10
5,10
6,60
7,90
9,80
A MIN
4,90
4,90
6,40
7,70
9,60
DIM
4073225/F 10/98
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusions.
The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad.
This pad is electrically and thermally connected to the backside of the die.
E. Falls within JEDEC MO-153
F. The PowerPAD is not directly connected to any leads of the package. However, it is electrically and thermally connected to the
substrate which is the ground of the device. The exposed pad dimension is 1.4 mm x 1.8 mm. However, the tolerances can be
+1.05/−0.05 mm (+ 41 / −2 mils) due to position and mold flow variation.
G. For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities, refer to Technical
Brief, PowerPad Thermally Enhanced Package, Texas Instrument s Literature No. SLMA002 and Application Brief, PowerPad Made
Easy, Texas Instruments Literature No. SLMA004. Both documents are available at www.ti.com.
26
www.ti.com
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Amplifiers
Applications
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
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