Ordering number : ENA2006 LC877G16A CMOS IC 16K-byte ROM and 512-byte RAM 8-bit 1-chip Microcontroller Overview The LC877G16A is an 8-bit microcontroller that, centered around a CPU running at a minimum bus cycle time of 200ns, integrates on a single chip a number of hardware features such as 16K-byte ROM, 512-byte RAM, an LCD controller/driver, a sophisticated 16-bit timer/counter (may be divided into 8-bit timers), two 8-bit timers with a prescaler, a 16-bit timer with a prescaler (may be divided into 8-bit timers), a UART interface (full duplex), infrared remote control receive function, and general-purpose I/O circuits. Features ROM • 16384 × 8 bits RAM • 512 × 9 bits Minimum Bus Cycle Time • 200ns (5MHz) VDD=2.7 to 5.5V Note: The bus cycle time here refers to ROM read speed. Minimum Instruction Cycle Time (tCYC) • 600ns (5MHz) VDD=2.7 to 5.5V Operating Temperature Range • -40°C to +85°C Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. Ver.1.00 30712HKIM 20120119-S00007 No.A2006-1/17 LC877G16A Ports • Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1-bit units: • Normal withstand voltage input port • LCD ports Segment output: Common output: Bias power supply for LCD driving: Multiplexed pin functions Input/output ports: • Dedicated oscillator ports • Reset pin • Power pins 13 (2 for UART, 1 for remote control, and 10 for key-scan signal I/O) 1 (XT1) 74 (S00 to S73) 4 (COM0 to COM3) 3 (V1 to V3) 8 (P1n) 2 (CF1, CF2) 1 (RES) 2 (VDD1, VSS1) LCD Controller (1) Display duty: 1/3duty, 1/4duty (2) Display bias: 1/2bias, 1/3bias UART • Full duplex • 7/8/9 bits data bit selectable • 1 stop bit (2-bit in continuous data transmission) • Built-in baudrate generator • Maximum transfer rate: 200kbps (5MHz) Timers • Timer 0: 16-bit timer/counter with a capture register Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture registers) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register) • Timer 4: 8-bit timer with a 6-bit prescaler • Timer 5: 8-bit timer with a 6-bit prescaler • Timer 8: 16-bit timer Mode 0: 8-bit timer with an 8-bit prescaler × 2 channels Mode 1: 16-bit timer with an 8-bit prescaler • Base Timer 1) The clock can be selected from the system clock and timer 0 prescaler output. 2) An interrupt can be generated at five different time intervals. No.A2006-2/17 LC877G16A Infrared Remote Control Receiver Circuit 1 1) Noise rejection function 2) Supports receive formats with a guide-pulse of half-clock/clock/none. 3) Determines an end of receive by detecting a no-signal period (no carrier). (Supports same receive format with a different bit length.) High-speed Multiplication/Division Instructions • 16 bits × 8 bits (5 tCYC execution time) • 24 bits × 16 bits (12 tCYC execution time) • 16 bits ÷ 8 bits (8 tCYC execution time) • 24 bits ÷ 16 bits (12 tCYC execution time) Interrupts • 14 sources, 8 vectors 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt request of the level equal to or lower than the current interrupt is not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, an interrupt into the smallest vector address is given priority. No. Vector Address Level 1 00003H X or L INT0 Interrupt Source 2 0000BH X or L INT1 3 00013H H or L T0L/remote control receiver1 4 0001BH H or L INT3/base timer 5 00023H H or L T0H 7 00033H H or L UART receive/T8L/T8H 8 0003BH H or L UART transmit 0004BH H or L Port 0/T4/T5 6 9 10 • Priority levels: X > H > L • When interrupts of the same level occur at the same time, an interrupt with the smallest vector address is given priority. Subroutine Stack Levels • Up to 256 levels mum (stack is allocated in RAM) Oscillator Circuits • RC oscillator circuit (internal): For system clock • CF oscillator circuit: For system clock, with internal Rf, and external Rd System Clock Divider Function • Can run on low current. • The minimum instruction cycle can be selected from among 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and 76.8μs (at a main clock rate of 5MHz). No.A2006-3/17 LC877G16A Standby Function • HALT mode: HALT mode is used to minimize power dissipation of the IC. Halts instruction execution while allowing the peripheral circuits to continue operation. (Some serial transfer functions are suspended.) 1) Oscillators do not stop automatically. 2) Released by a system reset or occurrence of an interrupt. • HOLD mode: HOLD mode is used to minimize power dissipation of the IC. Suspends instruction execution and operation of the peripheral circuits. 1) The CF and RC oscillators automatically stop operation. 2) There are three ways of releasing HOLD mode. (1) Setting the reset pin to a low level (2) Setting at least one of the INT0, INT1, and INT3 pins to the specified level (3) Establishing an interrupt source at port 0 Package Form • ΤQFP100 (14×14) “Lead-free and halogen-free product” Development Tools • On-chip debugger: TCB87-Type B + LC87D7G16A TCB87-Type C (3-wire cable) + LC87D7G16A No.A2006-4/17 LC877G16A Package Dimensions unit : mm (typ) 3274 75 0.5 16.0 14.0 51 50 100 26 14.0 16.0 76 1 0.5 0.2 25 0.125 1.2max 0.1 (1.0) (1.0) SANYO : TQFP100(14X14) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 Pin Assignment LC877G16A 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 RES XT1 VSS1 CF1 CF2 VDD1 S0/P10 S1/P11 S2/P12 S3/P13 S4/P14 S5/P15 S6/P16 S7/P17 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S69 S70 S71 S72 S73 COM0 COM1 COM2 COM3 V3 V2 V1 P70/INT0/T0LCP P71/INT1/T0HCP P00 P01 P02 P03 P04 P05 P06 P07 RMIN/P73/INT3/T0IN UTX/P34 URX/P35 Top view SANYO: ΤQFP100 (14×14) “Lead-free and halogen-free product” No.A2006-5/17 LC877G16A PIN No. NAME PIN No. 1 RES 51 NAME S44 2 XT1 52 S45 3 VSS1 53 S46 4 CF1 54 S47 5 CF2 55 S48 6 VDD1 56 S49 7 S0/P10 57 S50 8 S1/P11 58 S51 9 S2/P12 59 S52 10 S3/P13 60 S53 11 S4/P14 61 S54 12 S5/P15 62 S55 13 S6/P16 63 S56 14 S7/P17 64 S57 15 S8 65 S58 16 S9 66 S59 17 S10 67 S60 18 S11 68 S61 19 S12 69 S62 20 S13 70 S63 21 S14 71 S64 22 S15 72 S65 23 S16 73 S66 24 S17 74 S67 25 S18 75 S68 26 S19 76 S69 27 S20 77 S70 28 S21 78 S71 29 S22 79 S72 30 S23 80 S73 31 S24 81 COM0 32 S25 82 COM1 33 S26 83 COM2 34 S27 84 COM3 35 S28 85 V3 36 S29 86 V2 37 S30 87 V1 38 S31 88 P70/INT0/T0LCP 39 S32 89 P71/INT1/T0HCP 40 S33 90 PO0 41 S34 91 P01 42 S35 92 P02 43 S36 93 P03 44 S37 94 P04 45 S38 95 P05 46 S39 96 P06 47 S40 97 P07 RMIN/P73/INT3/T0IN 48 S41 98 49 S42 99 UTX/P34 50 S43 100 URX/P35 No.A2006-6/17 LC877G16A System Block Diagram Interrupt control Standby control Clock CF generator ROM RC PC RES Reset control ACC B Register C Register Bus interface ALU PSW Base timer Port 0 Timer 0 Port 1/Segment RAR INT Noise filter Port 3/UART RAM LCD controller Port 7 Stack pointer Timer 4 Remote control receiver circuit Timer 5 Timer 8 No.A2006-7/17 LC877G16A Pin Description Pin Name I/O Function Option VSS1 - - power supply VDD1 - + power supply No Port 0 I/O • 8-bit I/O port Yes P00 to P07 No • I/O can be specified in 1-bit units. • Pull-up resistors can be turned on and off in 1-bit units. • HOLD release input • Port 0 interrupt input Port 3 I/O P34, P35 Yes • 2-bit I/O port • I/O can be specified in 1-bit units. • Pull-up resistors can be turned on and off in 1-bit units. • Multiplexed pin function UTX: UART transmit data output URX: UART receive data input XT1 I • Test pin No • 1-bit input port Port 7 I/O P70, P71, P73 • 3-bit I/O port No • I/O can be specified in 1-bit units. • Pull-up resistors can be turned on and off in 1-bit units. • Multiplexed pin function P70: INT0 input/HOLD release input/timer 0L capture input/watchdog timer output P71: INT1 input/HOLD release input/timer 0H capture input P73: INT3 input (with noise filter input/timer 0 event input/timer 0H capture input/infrared remote control receive input Interrupt acknowledge type S0/P10 to I/O S7/P17 Rising Falling INT0 Enable Enable INT1 Enable Enable INT3 Enable Enable Rising & H level L level Disable Enable Enable Disable Enable Enable Enable Disable Disable Falling • LCD display segment output No • Can be used as a general-purpose I/O port (P1). S8 to S73 O • LCD segment output No COM0 to O • LCD common output No No COM3 V1 to V3 I/O • LCD bias RES I • Reset pin No CF1 I • Ceramic resonator input pin No CF2 O • Ceramic resonator output pin No Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name P00 to P07 Option Selected in Units of Output Type Pull-up Resistor 1 CMOS Programmable 2 N-channel open drain Programmable 1 bit 1 CMOS Programmable 2 N-channel open drain Programmable P70 - No N-channel open drain Programmable P71, P73 - No CMOS Programmable S0/P10 to S7/P17 - No CMOS Programmable S8 to S73 - No Dedicated LCD output No COM0 to COM3 - No Dedicated LCD output No V1 to V3 - No Dedicated LCD input No XT1 - No Input only No P34 to P35 1 bit Option Type No.A2006-8/17 LC877G16A Absolute Maximum Ratings at Ta = 25°C, VSS1 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] Maximum supply VDD max VDD1 LCD supply voltage VLCD V1, V2, V3 Input voltage VI(1) Input/output voltage High level output current Total output VDD XT1, CF1, RES -0.3 VDD+0.3 VIO(1) Ports 0, 1, 3, 7 -0.3 VDD+0.3 IOPH(1) Ports 0, 34, 35 • CMOS output selected • Each pin used Ports 71, 73 • Each pin used -5 IOPH(3) Port 1 • Each pin used -5 IOMH(1) Ports 0, 34, 35 • CMOS output selected • Each pin used -7.5 IOMH(2) Ports 71, 73 • Each pin used -3 IOMH(3) Port 1 • Each pin used -3 ΣIOAH(1) Ports 0,1,34, 35, 7 Total of all pins -45 mA Peak output IOPL(1) Ports 0, 34, 35 • Each pin used 20 current IOPL(2) Port 7 • Each pin used 10 IOPL(3) Port 1 • Each pin used 10 Mean output IOML(1) Ports 0, 34, 35 • Each pin used 15 current IOML(2) Ports 7 • Each pin used 7.5 IOML(3) Port 1 • Each pin used 7.5 ΣIOAL(1) Ports 0,1,34, 35, 7 Total of all pins Pd max TQFP100(14×14) Ta=-40 to +85°C (Note 1-1) Total output 80 current Allowable power 231 dissipation Operating ambient Topr temperature Storage ambient Tstg temperature V -10 IOPH(2) current Low level output current unit -0.3 current (Note 1-1) max +6.5 current Mean output typ -0.3 voltage Peak output min -40 +85 -55 +125 mW °C Note 1-1: The mean output current is a mean value measured over 100ms. No.A2006-9/17 LC877G16A Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] Operating VDD(1) VDD1 min typ max unit 0.588μs≤tCYC≤30μs supply voltage range 2.7 5.5 2.0 5.5 (Note 2-1) Memory VHD VDD1 retention supply Keep RAM and register data in HOLD mode. voltage High level input VIH(1) Ports 0, 1, 3, 7 voltage • Output disabled • When INT1VTSL=0 2.7 to 5.5 +0.7 VDD 2.7 to 5.5 0.85VDD VDD 2.7 to 5.5 0.75VDD (P71 only) VIH(2) P71 interrupt side • Output disabled • When INT1VTSL=1 Low level VIH(3) XT1, CF1, RES VIL(1) Ports 0, 1 Output disabled input voltage VIL(2) Ports 34, 35, 7 • Output disabled • When INT1VTSL=0 (P71 only) VIL(3) P71 interrupt side VDD V 0.15VDD 4.0 to 5.5 VSS 2.7 to 4.0 VSS 4.0 to 5.5 VSS 2.7 to 4.0 VSS 0.2VDD 2.7 to 5.5 VSS 0.45VDD +0.4 0.2VDD 0.1VDD +0.4 • Output disabled • When INT1VTSL=1 Instruction 0.3VDD VIL(4) XT1 2.7 to 5.5 VSS 0.2VDD VIL(5) CF1, RES 2.7 to 5.5 VSS 0.25VDD 2.7 to 5.5 0.588 30 2.7 to 5.5 0.1 5 2.7 to 5.5 0.2 10 tCYC cycle time μs (Note 2-2) External FEXCF(1) CF1 system clock • CF2 pin open • System clock frequency frequency division ration=1/1 • External system clock duty=50 ± 5% • CF2 pin open • System clock frequency division ratio = 1/2 Oscillation FmCF (1) CF1, CF2 5MHz ceramic resonator frequency oscillation range See Fig. 1. (Note 2-3) FmRC MHz 2.7 to 5.5 5 Internal RC oscillation 2.7 to 5.5 0.3 1.0 2.0 Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See Tables 1 and 2 for the oscillation constants. No.A2006-10/17 LC877G16A Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] High level IIH(1) Ports 0, 1, 3, 7 input current min typ max unit • Output disabled • Pull-up resistor off • VIN=VDD 2.7 to 5.5 1 2.7 to 5.5 1 2.7 to 5.5 1 2.7 to 5.5 15 (Including output Tr off-leakage current) IIH(2) RES IIH(3) XT1 VIN=VDD • Input port specification • VIN=VDD Low level IIH(4) CF1 VIN=VDD IIL(1) Ports 0, 1, 3, 7 • Output disabled input current μA • Pull-up resistor off • VIN=VSS 2.2 to 5.5 -1 2.2 to 5.5 -1 2.2 to 5.5 -1 -15 (Including output Tr off-leakage current) IIL(2) RES VIN=VSS IIL(3) XT1 • Input port specification • VIN=VSS IIL(4) CF1 VIN=VSS 2.2 to 5.5 High level VOH(1) CMOS output ports IOH=-1mA 4.5 to 5.5 VDD-1 output VOH(2) 0, 34, 35 IOH=-0.4mA 3.0 to 5.5 VDD-0.4 IOH=-0.2mA 2.7 to 5.5 VDD-0.4 VDD-0.4 voltage VOH(3) VOH(4) Ports 71 to 73 VOH(5) VOH(6) Port 1 VOH(7) IOH=-0.4mA 3.0 to 5.5 IOH=-0.2mA 2.7 to 5.5 VDD-0.4 IOH=-0.4mA 3.0 to 5.5 VDD-0.4 IOH=-0.2mA 2.7 to 5.5 VDD-0.4 IOL=10mA 4.5 to 5.5 1.5 Low level VOL(1) output VOL(2) IOL=1.6mA 3.0 to 5.5 0.4 VOL(3) IOL=1mA 2.7 to 5.5 0.4 IOL=1.6mA 3.0 to 5.5 0.4 IOL=1mA 2.7 to 5.5 0.4 IOL=1.6mA 3.0 to 5.5 0.4 IOL=1mA 2.7 to 5.5 0.4 voltage VOL(4) Ports 0, 1, 34, 35 Port 7 VOL(5) VOL(6) Port 1 VOL(7) LCD output VODLS S0 to S73 voltage • IO=0mA • VLCD, 2/3VLCD 1/3VLCD level output 2.7 to 5.5 0 ±0.2 2.7 to 5.5 0 ±0.2 V • See Fig. 6. VODLC COM0 to COM3 • IO=0mA • VLCD, 2/3VLCD 1/2VLCD, 1/3VLCD level output • See Fig. 6. LCD bias RLCD(1) resistor Resistance per See Fig. 6. one bias resistor RLCD(2) • Resistance per 2.7 to 5.5 60 2.7 to 5.5 30 See Fig. 6. one bias resistor • Resistor division kΩ 1/2 mode Pull-up MOS Tr. resistor Hysteresis Rpu(1) capacitance VOH=0.9VDD Rpu(2) VHYS(1) CP 4.5 to 5.5 15 35 80 2.7 to 4.5 18 50 150 • Port 7 • RES voltage Pin • Ports 0, 1, 3, 7 All pins 2.7 to 5.5 0.1VDD V 2.7 to 5.5 10 pF • For pins other than that under test: VIN=VSS • f=1MHz • Ta=25°C No.A2006-11/17 LC877G16A Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] High/low tPIH(1) INT0(P70), • Interrupt source flag can be set. level pulse tPIL(1) INT1(P71) • Event input for timer 0 is enabled. tPIH(2) INT3(P73) • Interrupt source flag can be set. tPIL(2) (Noise rejection • Event input for timer 0 is enabled. min typ 2.7 to 5.5 1 2.7 to 5.5 2 max unit width ratio is 1/1.) tPIH(3) INT3(P73) • Interrupt source flag can be set. tPIL(3) (Noise rejection • Event input for timer 0 is enabled. tCYC 2.7 to 5.5 64 2.7 to 5.5 256 2.7 to 5.5 4 2.7 to 5.5 200 ratio is 1/32.) tPIH(4) INT3(P73) • Interrupt source flag can be set. tPIL(4) (Noise rejection • Event input for timer 0 is enabled. ratio is 1/128.) tPIH(5) RMIN(P73) tPIL(5) tPIL(5) Recognized as a signal by infrared remote control receiver circuit RES Resetting is enabled. RMCK (Note4-1) μs Note 4-1: RMCK denotes the reference frequency of the remote control receiver circuit (40tCYC/50tCYC). Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = 0V Parameter Normal mode Symbol IDDOP(1) Pins/ VDD1 VDD[V] • FmCF=5MHz ceramic resonator oscillation consumption • System clock set to CF 5MHz side current • Internal RC oscillation stopped IDDOP(2) • 1/1 frequency division ratio (Note 5-1) IDDOP(3) Specification Conditions Remarks • FmCF=0Hz (oscillation stopped) min typ max 4.5 to 5.5 2.9 7.2 2.7 to 3.6 1.6 3.9 4.5 to 5.5 0.4 1.3 2.7 to 3.6 0.2 0.6 4.5 to 5.5 1.1 3.2 2.7 to 3.6 0.5 1.5 4.5 to 5.5 0.3 0.8 2.7 to 3.6 0.2 0.3 4.5 to 5.5 0.14 14 2.7 to 3.6 0.03 10 unit • System clock set to internal RC oscillation IDDOP(4) HALT mode consumption current (Note 5-1) IDDHALT(1) • 1/2 frequency division ratio HALT mode • FmCF=5MHz ceramic resonator oscillation • System clock set to CF 5MHz side IDDHALT(2) • Internal RC oscillation stopped • 1/1 frequency division ratio IDDHALT(3) HALT mode • FmCF=0Hz (oscillation stopped) IDDHALT(4) • System clock set to internal RC oscillation • 1/2 frequency division ratio HOLD mode IDDHOLD(1) consumption current mA IDDHOLD(2) HOLD mode • CF1=VDD or open (When using external clock) μA Note 5-1: The consumption current value do not include current that flows into the output transistors and internal pullup resistors. No.A2006-12/17 LC877G16A UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, VSS1 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] Transfer rate UBR UTX(P34), 2.7 to 5.5 URX(P35) min typ max 16/3 8192/3 unit tCYC Data length: 7/8/9 bits (LSB first) Stop bits: 1 bit (2-bit in continuous data transmission) Parity bits: None Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H) Start bit Start of transmission Stop bit Transmit data (LSB first) End of transmission UBR Example of 8-bit Data Reception Mode Processing (Receive Data=55H) Stop bit Start bit Start of reception Receive data (LSB first) End of reception UBR No.A2006-13/17 LC877G16A Main System Clock Oscillator Circuit Characteristics Given below are the characteristics of a sample main system clock oscillator circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a sample main system clock oscillator circuit with a ceramic resonator Oscillation Circuit Parameters Frequency Manufacturer Operating Stabilization Voltage Resonator Name C1 C2 Rf1 Rd1 [pF] [pF] [Ω] [Ω] CSTCR5M00G53-R0 (15) (15) Open 2.2k CSTLS5M00G53-B0 (15) (15) Open 2.2k Range[V] Time Notes typ max [ms] [ms] 2.7 to 5.5 0.05 0.15 2.7 to 5.5 0.05 0.15 Values shown in 5MHz Murata parentheses are capacitance included in the resonator The oscillation stabilization time is a period until the oscillation becomes stable after VDD becomes higher than minimum operating voltage. (See Fig. 3) Notes: Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. CF1 CF2 Rf1 Rd1 C2 C1 CF Figure 1 Ceramic Oscillator Circuit 0.5VDD Figure 2 AC Timing Measurement Point No.A2006-14/17 LC877G16A VDD Power supply VDD lower limit 0V Reset time RES Internal RC oscillation tmsCF CF1, CF2 Operating mode Undefined Reset Instruction execution Reset Time and Oscillation Stabilization Time HOLD release signal Without HOLD release signal HOLD release signal valid Internal RC oscillation tmsCF CF1, CF2 Operation mode HOLD HALT HOLD Release Signal and Oscillation Stabilization Time Figure 3 Oscillation Stabilization Time No.A2006-15/17 LC877G16A VDD Note: Select CRES and RRES value to assure that at least 200μs reset time is generated after the VDD becomes higher than the minimum operating voltage. RRES RES CRES Figure 4 Reset Circuit tPIL tPIH Figure 5 Pulse Input Timing Signal Waveform VDD SW : ON/OFF (programmable) RLCD RLCD SW: ON (VLCD=VDD) RLCD RLCD VLCD RLCD RLCD 2/3VLCD RLCD 1/2VLCD RLCD 1/3VLCD RLCD RLCD GND Figure 6 LCD Bias Resistor No.A2006-16/17 LC877G16A SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of January, 2012. Specifications and information herein are subject to change without notice. PS No.A2006-17/17