TI SN74ALVCH162268DL

SN74ALVCH162268
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES018L – AUGUST 1995 – REVISED SEPTEMBER 2004
FEATURES
•
•
•
•
•
•
•
•
Member of the Texas Instruments Widebus™
Family
Operates From 1.65 V to 3.6 V
Max tpd of 4.8 ns at 3.3 V
±24-mA Output Drive at 3.3 V
B-Port Outputs Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
DESCRIPTION/ORDERING INFORMATION
This 12-bit to 24-bit registered bus exchanger is
designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH162268 is used for applications in
which data must be transferred from a narrow
high-speed bus to a wide, lower-frequency bus.
DGG OR DL PACKAGE
(TOP VIEW)
OEA
CLKEN1B
2B3
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
CLKEN2B
SEL
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
OEB
CLKENA2
2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4
CLKENA1
CLK
The device provides synchronous data exchange
24
33
between the two ports. Data is stored in the internal
25
32
registers on the low-to-high transition of the clock
26
31
(CLK) input when the appropriate clock-enable
27
30
(CLKEN) inputs are low. The select (SEL) line is
synchronous with CLK and selects 1B or 2B input
28
29
data for the A outputs.
For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single
storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be
presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables
(OEA, OEB). These control terminals are registered, so bus direction changes are synchronous with CLK.
The B outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot
and undershoot.
ORDERING INFORMATION
PACKAGE (1)
TA
SSOP - DL
-40°C to 85°C
TSSOP - DGG
VFBGA - GQL
VFBGA - ZQL (Pb-free)
(1)
ORDERABLE PART NUMBER
Tube
SN74ALVCH162268DL
Tape and reel
SN74ALVCH162268DLR
Tape and reel
SN74ALVCH162268GR
Tape and reel
SN74ALVCH162268KR
74ALVCH162268ZQLR
TOP-SIDE MARKING
ALVCH162268
ALVCH162268
VH2268
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1995–2004, Texas Instruments Incorporated
SN74ALVCH162268
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES018L – AUGUST 1995 – REVISED SEPTEMBER 2004
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as
possible, and OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined
by the current-sinking capability of the driver. Due to OE being routed through a register, the active state of the
outputs cannot be determined prior to the arrival of the first clock pulse.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
GQL OR ZQL PACKAGE
(TOP VIEW)
1
3
4
5
TERMINAL ASSIGNMENTS
6
1
2
3
4
5
6
A
A
2B3
CLKEN1B
OEA
OEB
CLKENA2
2B4
B
B
2B1
2B2
GND
GND
2B5
2B6
C
C
A2
A1
VCC
VCC
2B7
2B8
D
D
A4
A3
GND
GND
2B9
2B10
E
E
A6
A5
2B11
2B12
F
F
A7
A8
1B11
1B12
G
G
A9
A10
GND
1B9
1B10
H
A11
A12
VCC
VCC
1B7
1B8
J
1B1
1B2
GND
GND
1B5
1B6
K
1B3
CLKEN2B
SEL
CLK
CLKENA1
1B4
H
J
K
2
2
GND
SN74ALVCH162268
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES018L – AUGUST 1995 – REVISED SEPTEMBER 2004
FUNCTION TABLES
OUTPUT ENABLE
INPUTS
OUTPUTS
CLK OEA OEB
A
1B, 2B
Z
Z
Active
↑
H
↑
H
L
Z
↑
L
H
Active
Z
↑
L
L
Active
Active
H
A-TO-B STORAGE (OEB = L)
INPUTS
CLKENA1
H
(1)
(2)
CLKENA2
OUTPUTS
CLK
H
X
L
L
↑
L
L
↑
X
L
X
L
A
1B
X
1B0
2B
(1)
2B0 (1)
L
L (2)
X
H
H (2)
X
↑
L
X
L
↑
H
X
H
Output level before the indicated steady-state input conditions were
established
Two CLK edges are needed to propagate data.
B-TO-A STORAGE (OEA = L)
INPUTS
OUTPUT
CLKEN1B
CLKEN2B
CLK
SEL
1B
2B
A
H
X
X
H
X
X
A0 (1)
X
H
X
L
X
X
A0 (1)
L
L
↑
H
L
X
L
L
L
↑
H
H
X
H
X
L
↑
L
X
L
L
X
L
↑
L
X
H
H
(1)
Output level before the indicated steady-state input conditions
were established
3
SN74ALVCH162268
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES018L – AUGUST 1995 – REVISED SEPTEMBER 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
29
CLK
2
CLKEN1B
27
CLKEN2B
CLKENA1
30
55
C1
CLKENA2
56
1D
OEB
C1
SEL
28
1D
1
OEA
CE
1D
C1
1D
C1
G1
A1
1
CE
C1
1D
1D
CE
C1
1D
C1
1D
CE
C1
1D
1 of 12 Channels
Pin numbers shown are for the DGG and DL packages.
4
1B1
CE
1
8
23
6
2B1
www.ti.com
SN74ALVCH162268
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES018L – AUGUST 1995 – REVISED SEPTEMBER 2004
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
MIN
MAX
-0.5
4.6
Except I/O ports (2)
-0.5
4.6
I/O ports (2) (3)
-0.5
VCC + 0.5
-0.5
VCC + 0.5
UNIT
V
VI
Input voltage range
VO
Output voltage range (2) (3)
IIK
Input clamp current
VI < 0
-50
mA
IOK
Output clamp current
VO < 0
-50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through each VCC or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
DGG package
64
DL package
56
GQL/ZQL package
(1)
(2)
(3)
(4)
V
V
°C/W
42
-65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended
operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 4.6 V, maximum.
The package thermal impedance is calculated in accordance with JESD 51-7.
5
SN74ALVCH162268
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES018L – AUGUST 1995 – REVISED SEPTEMBER 2004
RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
MIN
MAX
1.65
3.6
Low-level input voltage
VI
Input voltage
VO
Output voltage
High-level output current (A port)
IOH
High-level output current (B port)
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
IOL
Low-level output current (B port)
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
0.8
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
6
V
0
VCC
V
0
VCC
V
VCC = 1.65 V
-4
VCC = 2.3 V
-12
VCC = 2.7 V
-12
VCC = 3 V
-24
VCC = 1.65 V
-2
VCC = 2.3 V
-6
VCC = 2.7 V
mA
-8
-12
VCC = 1.65 V
4
VCC = 2.3 V
12
VCC = 2.7 V
12
VCC = 3 V
24
VCC = 1.65 V
2
VCC = 2.3 V
6
VCC = 2.7 V
mA
8
VCC = 3 V
∆t/∆v
V
0.35 × VCC
VCC = 3 V
Low-level output current (A port)
V
0.65 × VCC
VCC = 1.65 V to 1.95 V
VIL
UNIT
12
-40
10
ns/V
85
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application
report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74ALVCH162268
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES018L – AUGUST 1995 – REVISED SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -100 µA
IOH = -6 mA
2.3 V
2
2.3 V
1.7
2.7 V
2.2
3V
2.4
IOH = -24 mA
3V
2
IOH = -100 µA
1.65 V to 3.6 V
A port
B port
1.65 V
1.2
2.3 V
1.9
2.3 V
1.7
3V
2.4
IOH = -8 mA
2.7 V
2
IOH = -12 mA
3V
2
IOL = 100 µA
1.65 V to 3.6 V
0.2
IOL = 4 mA
1.65 V
0.45
IOL = 6 mA
2.3 V
0.4
2.3 V
0.7
II
2.7 V
0.4
IOL = 24 mA
3V
0.55
IOL = 100 µA
1.65 V to 3.6 V
0.2
IOL = 2 mA
1.65 V
0.45
IOL = 4 mA
2.3 V
0.4
2.3 V
0.55
IOL = 6 mA
3V
0.55
IOL = 8 mA
2.7 V
0.6
IOL = 12 mA
3V
0.8
VI = VCC or GND
VI = 0.58 V
VI = 0.7 V
II(hold)
2.3 V
VI = 1.7 V
VI = 0.8 V
3V
VI = 2 V
±5
3.6 V
1.65 V
VI = 1.07 V
UNIT
V
VCC - 0.2
IOH = -4 mA
IOL = 12 mA
VOL
MAX
1.2
IOH = -2 mA
IOH = -6 mA
TYP (1)
VCC - 0.2
1.65 V
IOH = -12 mA
B port
1.65 V to 3.6 V
MIN
IOH = -4 mA
A port
VOH
VCC
V
µA
25
-25
45
µA
-45
75
-75
3.6 V
±500
IOZ (3)
VO = VCC or GND
3.6 V
±10
µA
ICC
VI = VCC or GND, IO = 0
3.6 V
40
µA
750
µA
VI = 0 to 3.6
∆ICC
V (2)
One input at VCC - 0.6 V, Other inputs at VCC or GND
3 V to 3.6 V
Ci
Control inputs
VI = VCC or GND
3.3 V
3.5
pF
Cio
A or B ports
VO = VCC or GND
3.3 V
9
pF
(1)
(2)
(3)
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
For I/O ports, the parameter IOZ includes the input leakage current.
7
SN74ALVCH162268
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES018L – AUGUST 1995 – REVISED SEPTEMBER 2004
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V
MIN
fclock
Clock frequency
tw
Pulse duration, CLK high or low
tsu
Setup time
th
Hold time
VCC = 2.7 V
MAX
MIN
120
3.3
MAX
VCC = 3.3 V
± 0.3 V
MIN
125
150
3.3
3.3
3.4
A data before CLK↑
4.5
4
B data before CLK↑
0.8
1.2
1
SEL before CLK↑
1.4
1.6
1.3
CLKENA1 or CLKENA2 before CLK↑
3.6
3.4
2.8
CLKEN1B or CLKEN2B before CLK↑
3.2
3
2.5
OE before CLK↑
4.2
3.9
3.2
A data after CLK↑
0
0
0.2
B data after CLK↑
1.3
1.2
1.3
1
1
1
CLKENA1 or CLKENA2 after CLK↑
0.1
0.1
0.4
CLKEN1B or CLKEN2B after CLK↑
0.1
0
0.5
0
0
0.2
SEL after CLK↑
OE after CLK↑
UNIT
MAX
MHz
ns
ns
ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
TYP
fmax
tpd
VCC = 2.5 V
± 0.2 V
MIN
MAX
120
CLK
tdis
CLK
MIN
MAX
125
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
150
MHz
B
8
1.6
6.1
5.9
1.8
5.4
A (1B)
8
1.6
5.8
5.4
1.7
4.8
A (2B)
8
1.6
5.8
5.3
1.8
4.8
A (SEL)
11
2.5
7.3
6.5
2.4
5.8
B
12
2.7
7.2
6.8
2.6
6.1
A
9
2
6.2
5.6
1.8
5.1
B
10
2.8
7.2
6.1
2.5
5.9
A
9
2
6.5
5.4
2.1
5
CLK
ten
VCC = 2.7 V
ns
ns
ns
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
Cpd
8
Power dissipation capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 50 pF, f = 10 MHz
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
87
120
80.5
118
UNIT
pF
SN74ALVCH162268
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES018L – AUGUST 1995 – REVISED SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUT
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
tw
VI
Timing
Input
VM
VM
VM
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VM
VM
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VLOAD/2
VM
tPZH
VOH
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPHL
VM
VI
VM
tPZL
VI
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VI
Data
Input
VM
0V
0V
tsu
Output
VI
VM
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VOH
VM
VOH − V∆
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
9
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74ALVCH162268DLG4
ACTIVE
SSOP
DL
56
74ALVCH162268DLRG4
ACTIVE
SSOP
DL
74ALVCH162268GRE4
ACTIVE
TSSOP
74ALVCH162268GRG4
ACTIVE
74ALVCH162268ZQLR
ACTIVE
SN74ALVCH162268DGGR
SN74ALVCH162268DL
20
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
56
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
BGA MI
CROSTA
R JUNI
OR
ZQL
56
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
OBSOLETE
TSSOP
DGG
56
ACTIVE
SSOP
DL
56
SN74ALVCH162268DLR
ACTIVE
SSOP
DL
SN74ALVCH162268GR
ACTIVE
TSSOP
SN74ALVCH162268KR
NRND
BGA MI
CROSTA
R JUNI
OR
TBD
Call TI
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
56
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
GQL
56
1000
SNPB
Level-1-240C-UNLIM
20
TBD
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2007
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
74ALVCH162268ZQLR
Package Package Pins
Type Drawing
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ZQL
56
1000
330.0
16.4
4.8
7.3
1.45
8.0
16.0
Q1
SSOP
DL
56
1000
330.0
32.4
11.35
18.67
3.1
16.0
32.0
Q1
SN74ALVCH162268GR
TSSOP
DGG
56
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
SN74ALVCH162268KR
BGA MI
CROSTA
R JUNI
OR
GQL
56
1000
330.0
16.4
4.8
7.3
1.45
8.0
16.0
Q1
SN74ALVCH162268DLR
BGA MI
CROSTA
R JUNI
OR
SPQ
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
74ALVCH162268ZQLR
BGA MICROSTAR
JUNIOR
ZQL
56
1000
346.0
346.0
33.0
SN74ALVCH162268DLR
SSOP
DL
56
1000
346.0
346.0
49.0
SN74ALVCH162268GR
TSSOP
DGG
56
2000
346.0
346.0
41.0
SN74ALVCH162268KR
BGA MICROSTAR
JUNIOR
GQL
56
1000
346.0
346.0
33.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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