L6599AT
Improved high-voltage resonant controller
Features
■
50% duty cycle, variable frequency control of
resonant half-bridge
■
High-accuracy oscillator
■
Up to 500 kHz operating frequency
■
Two-level OCP: frequency-shift and latched
shutdown
■
Interface with PFC controller
■
Latched disable input
■
Burst-mode operation at light load
■
Input for power-ON/OFF sequencing or
brownout protection
■
Non-linear soft-start for monotonic output
voltage rise
■
600 V-rail compatible high-side gate driver with
integrated bootstrap diode and high dv/dt
immunity
■
-300/700 mA high-side and low-side gate
drivers with UVLO pull-down
■
DIP16, SO16N package
■
Guaranteed for extreme temperature ranges
DIP16
SO16N
Applications
■
Street lighting
■
LCD and PDP TVs
■
Desktop PCs, entry-level servers
■
Telecom SMPS
■
High efficiency industrial SMPS
■
AC-DC adapters, open frame SMPS
Table 1.
Device summary
Order codes
Package
Packaging
L6599ATD
SO16N
Tube
L6599ATDTR
SO16N
Tape and reel
L6599ATN
DIP16
Tube
October 2009
Doc ID 15534 Rev 3
1/31
www.st.com
31
Contents
L6599AT
Contents
1
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.1
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.2
Operation at no load or very light load . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.3
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4
Current sense, OCP and OLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.5
Latched shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.6
Line sensing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.7
Bootstrap section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/31
Doc ID 15534 Rev 3
L6599AT
1
Device description
Device description
The L6599AT is a temperature-extended version of the L6599A. It is a double-ended
controller specifically designed for the series-resonant half-bridge topology. It provides a
50% complementary duty cycle: the high-side switch and the low-side switch are driven
ON/OFF at 180° out-of-phase for exactly the same time interval. Output voltage regulation is
obtained by modulating the operating frequency. A fixed dead-time inserted between the
turn-off of one switch and the turn-on of the other guarantees soft-switching and enables
high-frequency operation.
To drive the high-side switch using the bootstrap approach, the IC incorporates a highvoltage floating structure capable of withstanding more than 600 V with a synchronousdriven high-voltage DMOS that replaces the external fast-recovery bootstrap diode.
The IC enables the designer to set the operating frequency range of the converter by means
of an externally programmable oscillator.
At start-up, to prevent uncontrolled inrush current, the switching frequency starts from a
programmable maximum value and progressively decays until it reaches the steady-state
value determined by the control loop. This frequency shift is non linear to minimize output
voltage overshoots; its duration is programmable as well.
At light load the IC may enter a controlled burst-mode operation that keeps the converter
input consumption to a minimum.
The device’s functions include a not-latched active-low disable input with current hysteresis
suitable for power sequencing or for brownout protection, a current sense input for OCP with
frequency shift and delayed shutdown with automatic restart. A higher level OCP latches off
the IC if the first-level protection is not sufficient to control the primary current. Their
combination offers complete protection against overload and short-circuits. An additional
latched disable input (DIS) allows easy implementation of OTP and/or OVP.
An interface with the PFC controller is provided that enables the switching off of the preregulator during fault conditions, such as OCP shutdown and DIS high, or during burstmode operation.
Doc ID 15534 Rev 3
3/31
Block diagram
2
L6599AT
Block diagram
Figure 1.
Block diagram
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4/31
Doc ID 15534 Rev 3
L6599AT
3
Pin connection
Pin connection
Figure 2.
Pin connection (top view)
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Table 2.
Pin n°
1
2
3
Pin description
Type
Function
Css
Soft-start. This pin connects an external capacitor to GND and a resistor to
RFmin (pin 4) that set both the maximum oscillator frequency and the time
constant for the frequency shift that occurs as the chip starts up
(soft-start). An internal switch discharges this capacitor every time the chip
turns off (Vcc < UVLO, LINE < 1.24 V or > 6 V, DIS > 1.85 V, ISEN > 1.5 V,
DELAY > 2 V) to make sure it is soft-started next, and when the voltage on
the current sense pin (ISEN) exceeds 0.8 V, as long as it stays above 0.75
V.
DELAY
Delayed shutdown upon overcurrent. A capacitor and a resistor are
connected from this pin to GND to set the maximum duration of an
overcurrent condition before the IC stops switching and the delay after
which the IC restarts switching. Every time the voltage on the ISEN pin
exceeds 0.8 V the capacitor is charged by an internal 150 µA current
generator and is slowly discharged by the external resistor. If the voltage
on the pin reaches 2 V, the soft start capacitor is completely discharged so
that the switching frequency is pushed to its maximum value and the
150 µA is kept always on. As the voltage on the pin exceeds 3.5 V the IC
stops switching and the internal generator is turned off, so that the voltage
on the pin decays because of the external resistor. The IC is soft-restarted
as the voltage drops below 0.3 V. In this way, under short-circuit conditions,
the converter works intermittently with very low input average power.
CF
Timing capacitor. A capacitor connected from this pin to GND is charged
and discharged by internal current generators programmed by the external
network connected to pin 4 (RFmin) and determines the switching
frequency of the converter.
Doc ID 15534 Rev 3
5/31
Pin connection
L6599AT
Table 2.
Pin n°
4
5
6
7
8
6/31
Pin description (continued)
Type
Function
RFmin
Minimum oscillator frequency setting. This pin provides a precise 2 V
reference and a resistor connected from this pin to GND defines a current
that is used to set the minimum oscillator frequency. To close the feedback
loop that regulates the converter output voltage by modulating the
oscillator frequency, the phototransistor of an optocoupler is connected to
this pin through a resistor. The value of this resistor sets the maximum
operating frequency. An R-C series connected from this pin to GND sets
frequency shift at start-up to prevent excessive energy inrush (soft-start).
STBY
Burst-mode operation threshold. The pin senses some voltage related to
the feedback control, which is compared to an internal reference (1.24 V).
If the voltage on the pin is lower than the reference, the IC enters an idle
state and its quiescent current is reduced. The chip restarts switching as
the voltage exceeds the reference by 50 mV. Soft-start is not invoked. This
function realizes burst-mode operation when the load falls below a level
that can be programmed by properly choosing the resistor connecting the
optocoupler to pin RFmin (see block diagram). Tie the pin to RFmin if
burst-mode is not used.
ISEN
Current sense input. The pin senses the primary current though a sense
resistor or a capacitive divider for lossless sensing. This input is not
intended for a cycle-by-cycle control; hence the voltage signal must be
filtered to get average current information. As the voltage exceeds a 0.8 V
threshold (with 50 mV hysteresis), the soft-start capacitor connected to pin
1 is internally discharged: the frequency increases hence limiting the
power throughput. Under output short-circuit, this normally results in a
nearly constant peak primary current. This condition is allowed for a
maximum time set at pin 2. If the current keeps on building up despite this
frequency increase, a second comparator referenced at 1.5 V latches the
device off and brings its consumption almost to a “before start-up” level.
The information is latched and it is necessary to recycle the supply voltage
of the IC to enable it to restart: the latch is removed as the voltage on the
Vcc pin goes below the UVLO threshold. Tie the pin to GND if the function
is not used.
LINE
Line sensing input. The pin is to be connected to the high-voltage input bus
with a resistor divider to perform either AC or DC (in systems with PFC)
brownout protection. A voltage below 1.24 V shuts down (not latched) the
IC, lowers its consumption and discharges the soft-start capacitor. IC’s
operation is re-enabled (soft-started) as the voltage exceeds 1.24 V. The
comparator is provided with current hysteresis: an internal 13 µA current
generator is ON as long as the voltage applied at the pin is below 1.24 V
and is OFF if this value is exceeded. Bypass the pin with a capacitor to
GND to reduce noise pick-up. The voltage on the pin is top-limited by an
internal zener. Activating the zener causes the IC to shut down (not
latched). Bias the pin between 1.24 and 6 V if the function is not used.
DIS
Latched device shutdown. Internally the pin connects a comparator that,
when the voltage on the pin exceeds 1.85V, shuts the IC down and brings
its consumption almost to a “before start-up” level. The information is
latched and it is necessary to recycle the supply voltage of the IC to enable
it to restart: the latch is removed as the voltage on the Vcc pin goes below
the UVLO threshold. Tie the pin to GND if the function is not used.
Doc ID 15534 Rev 3
L6599AT
Pin connection
Table 2.
Pin n°
9
Pin description (continued)
Type
Function
Open-drain ON/OFF control of PFC controller. This pin, normally open, is
intended for stopping the PFC controller, for protection purpose or during
burst-mode operation. It goes low when the IC is shut down by DIS>1.85 V,
PFC_STOP ISEN > 1.5 V, LINE > 6 V and STBY<1.24 V. The pin is pulled low also
when the voltage on pin DELAY exceeds 2 V and goes back open as the
voltage falls below 0.3 V. During UVLO, it is open. Leave the pin
unconnected if not used.
10
GND
Chip ground. Current return for both the low-side gate-drive current and
the bias current of the IC. All of the ground connections of the bias
components should be tied to a track going to this pin and kept separate
from any pulsed current return.
11
LVG
Low-side gate-drive output. The driver is capable of 0.3 A min. source and
0.7 A min. sink peak current to drive the lower MOSFET of the half-bridge
leg. The pin is actively pulled to GND during UVLO.
12
Vcc
Supply voltage of both the signal part of the IC and the low-side gate
driver. Sometimes a small bypass capacitor (0.1 µF typ.) to GND might be
useful to get a clean bias voltage for the signal part of the IC.
13
N.C.
High-voltage spacer. The pin is not internally connected to isolate the highvoltage pin and ease compliance with safety regulations (creepage
distance) on the PCB.
14
OUT
High-side gate-drive floating ground. Current return for the high-side gatedrive current. Layout carefully the connection of this pin to avoid too large
spikes below ground.
HVG
High-side floating gate-drive output. The driver is capable of 0.3 A min.
source and 0.7 A min. sink peak current to drive the upper MOSFET of the
half-bridge leg. A resistor internally connected to pin 14 (OUT) ensures
that the pin is not floating during UVLO.
VBOOT
High-side gate-drive floating supply Voltage. The bootstrap capacitor
connected between this pin and pin 14 (OUT) is fed by an internal
synchronous bootstrap diode driven in-phase with the low-side gate-drive.
This patented structure replaces the normally used external diode.
15
16
Doc ID 15534 Rev 3
7/31
Electrical data
L6599AT
4
Electrical data
4.1
Absolute maximum ratings
Table 3.
Absolute maximum rating
Symbol
Pin
VBOOT
16
VOUT
Value
Unit
Floating supply voltage
-1 to 618
V
14
Floating ground voltage
-3 to VBOOT-18
V
dVOUT /dt
14
Floating ground max. slew rate
50
V/ns
Vcc
12
IC supply voltage (Icc = 25 mA)
Self-limited
V
VPFC_STOP
9
Maximum voltage (pin open)
-0.3 to Vcc
V
IPFC_STOP
9
Maximum sink current (pin low)
Self-limited
A
VLINEmax
7
Maximum pin voltage (Ipin ≤ 1 mA)
Self-limited
V
IRFmin
4
Maximum source current
2
mA
---
1 to 6, 8
Analog inputs & outputs
-0.3 to 5
V
Power dissipation @TA = 70 °C (DIP16)
1
W
Power dissipation @TA = 50 °C (SO16)
0.83
Ptot
Tj
Parameter
Junction temperature operating range
-40 to 150
°C
Storage temperature
-55 to 150
°C
Value
Unit
Max. thermal resistance junction-to-ambient (DIP16)
80
°C/W
Max. thermal resistance junction-to-ambient (SO16)
120
°C/W
Tstg
Note:
ESD immunity for pins 14, 15 and 16 is guaranteed up to 900 V.
4.2
Thermal data
Table 4.
Symbol
Rth(JA)
8/31
Thermal data
Parameter
Doc ID 15534 Rev 3
L6599AT
5
Electrical characteristics
Electrical characteristics
TJ = -40 to 125 °C, Vcc = 15 V, VBOOT = 15 V, CHVG = CLVG = 1 nF; CF = 470 pF;
RRFmin = 12 kΩ; unless otherwise specified
Table 5.
Electrical characteristics
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
16
V
IC supply voltage
Vcc
Operating range
After device turn-on
VccOn
Turn-on threshold
Voltage rising
10
10.7
11.4
V
VccOff
Turn-off threshold
Voltage falling
7.45
8.15
8.85
V
Hys
Hysteresis
VZ
Vcc clamp voltage
8.85
2.55
Iclamp = 15 mA
16
V
17
17.9
V
Supply current
Start-up current
Before device turn-on
Vcc = VccOn- 0.2 V
200
250
µA
Iq
Quiescent current
Device on, VSTBY = 1 V
1.5
2
mA
Iop
Operating current
Device on, VSTBY = VRFmin
3.5
5
mA
Iq
Residual consumption
VDIS > 1.85 V or
VDELAY > 3.5 V or VLINE <
1.24 V or VLINE = Vclamp
300
400
µA
Istart-up
High-side floating gate-drive supply
ILKBOOT
VBOOT pin leakage current
VBOOT = 580 V
5
µA
ILKOUT
OUT pin leakage current
VOUT = 562 V
5
µA
RDS(on)
Synchronous bootstrap
diode on-resistance
VLVG = HIGH
Ω
150
Overcurrent comparator
IISEN
Input bias current
VISEN = 0 to VISENdis
tLEB
Leading edge blanking
After VHVG and VLVG lowto-high transition
Frequency shift threshold
Voltage rising (1)
Hysteresis
Voltage falling
Latch off threshold
Voltage rising (1)
VISENx
VISENdis
td(H-L)
-1
250
0.76
0.8
ns
0.84
50
1.44
Delay to output
µA
V
mV
1.5
1.56
V
300
400
ns
Line sensing
Vth
Threshold voltage
Voltage rising or falling (1)
1.2
1.24
1.28
V
IHys
Current hysteresis
VLINE = 1.1 V
10
13
16
µA
Clamp level
ILINE = 1 mA
6
8
V
Vclamp
Doc ID 15534 Rev 3
9/31
Electrical characteristics
Table 5.
L6599AT
Electrical characteristics (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
-1
µA
DIS function
IDIS
Vth
Input bias current
VDIS = 0 to Vth
(1)
Disable threshold
Voltage rising
Output duty cycle
Both HVG and LVG
1.78
1.85
1.92
V
48
50
52
%
58.2
60
61.8
RRFmin= 2.7 kΩ
240
250
260
Between HVG and LVG
0.2
0.3
0.4
Oscillator
D
fosc
Oscillation frequency
TD
Dead-time
VCFp
Peak value
VCFv
Valley value
(1)
VREF
KM
Voltage reference at pin 4
I_REF = -2
mA (1)
kHz
µs
3.9
V
0.9
V
1.93
2
2.07
V
1.8
2
2.2
V
Current mirroring ratio
1
A/A
PFC_STOP function
Ileak
High level leakage current
1
µA
200
Ω
IPFC_STOP = 1 mA,
VDIS = 1.5 V
0.2
V
Open-state current
V(Css) = 2 V
0.5
µA
Discharge resistance
VISEN > VISENx
RPFC_STOP ON-state resistance
VL
VPFC_STOP =Vcc,
VDIS = 0 V
Low saturation level
IPFC_STOP = 1 mA,
VDIS = 1.5 V
130
Soft-start function
Ileak
R
Ω
120
Standby function
IDIS
Input bias current
VDIS = 0 to Vth
Vth
Disable threshold
Voltage falling
Hys
Hysteresis
Voltage rising
(1)
1.2
1.24
-1
µA
1.28
V
50
mV
Delayed shutdown function
Ileak
Open-state current
V(DELAY) = 0
Charge current
VDELAY = 1 V,
VISEN = 0.85 V
100
Vth1
Threshold for forced
operation at max.
frequency
Voltage rising (1)
Vth2
Shutdown threshold
Voltage rising (1)
ICHARGE
10/31
Doc ID 15534 Rev 3
0.5
µA
150
200
µA
1.98
2.05
2.12
V
3.35
3.5
3.65
V
L6599AT
Electrical characteristics
Table 5.
Symbol
Vth3
Electrical characteristics (continued)
Parameter
Restart threshold
Test condition
Voltage falling
(1)
Min.
Typ.
Max.
Unit
0.30
0.33
0.36
V
1.8
V
Low-side gate driver (voltages referred to GND)
VLVGL
Output low voltage
Isink = 200 mA
VLVGH
Output high voltage
Isource = 5 mA
Isourcepk
Peak source current
-0.3
A
Peak sink current
0.7
A
Isinkpk
12.8
13.3
V
tf
Fall time
30
ns
tr
Rise time
60
ns
UVLO saturation
Vcc= 0 to VccOn,
Isink = 2 mA
1.1
V
1.8
V
High-side gate driver (voltages referred to OUT)
VLVGL
Output low voltage
Isink = 200 mA
VLVGH
Output high voltage
Isource = 5 mA
Isourcepk
Peak source current
-0.3
A
Peak sink current
0.7
A
Isinkpk
12.8
13.3
V
tf
Fall time
30
ns
tr
Rise time
60
ns
HVG-OUT pull-down
25
kΩ
1. Values tracking each other
Doc ID 15534 Rev 3
11/31
Application information
6
L6599AT
Application information
The L6599AT is an advanced double-ended controller specifically designed for resonant
half-bridge topology (see Figure 4.). In these converters the switches (MOSFETs) of the
half-bridge leg are alternately switched on and off (180° out-of-phase) for exactly the same
time interval. This is commonly referred to as operation at “50% duty cycle”, although the
real duty cycle, that is the ratio of the on-time of either switch to the switching period, is
actually less than 50%. The reason is that there is an internally fixed dead-time TD inserted
between the turn-off of either MOSFET and the turn-on of the other, where both MOSFETs
are off. This dead- time is essential for the converter to work correctly; it ensures softswitching and enable high-frequency operation with high efficiency and low EMI emissions.
To perform output voltage regulation of the converter, the device is capable of operating in
different modes (Figure 3), depending on the load conditions:
1.
Variable frequency at heavy and medium/light load. A relaxation oscillator (see
Section 6.1: Oscillator for more details) generates a symmetrical triangular waveform,
to which the MOSFETs' switching is locked. The frequency of this waveform is related
to a current that is modulated by the feedback circuitry. As a result, the tank circuit
driven by the half-bridge is stimulated at a frequency dictated by the feedback loop to
keep the output voltage regulated, thus exploiting its frequency-dependent transfer
characteristics.
2.
Burst-mode control with no or very light load. When the load falls below a certain value,
the converter enters a controlled intermittent operation, where a series of a few
switching cycles at a nearly fixed frequency are spaced out by long idle periods where
both MOSFETs are in an OFF-state. A further load decrease is translated into longer
idle periods, and then into a reduction of the average switching frequency. When the
converter is completely unloaded, the average switching frequency can go down to
even a few hundred hertz, thus minimizing any magnetizing current losses as well as all
frequency-related losses, and making it easier to comply with energy saving
recommendations.
Figure 3.
Multi-mode operation of the L6599AT
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!-V
12/31
Doc ID 15534 Rev 3
L6599AT
Application information
Figure 4.
Typical system block diagram
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6.1
Oscillator
The oscillator is programmed externally by means of a capacitor (CF) connected from pin 3
(CF) to ground, which is alternately charged and discharged by the current defined with the
network connected to pin 4 (RFmin). The pin provides an accurate 2 V reference with about
2 mA source capability and the higher the current sourced by the pin, the higher the
oscillator frequency. The block diagram in Figure 5 shows a simplified internal circuit that
explains the operation.
The network that loads the RFmin pin is generally made up of three branches:
1.
A resistor RFmin connected between the pin and ground, which determines the
minimum operating frequency.
2.
A resistor RFmax connected between the pin and the collector of the (emitter-grounded)
phototransistor that transfers the feedback signal from the secondary side back to the
primary side. While in operation, the phototransistor modulates the current through this
branch - thus modulating the oscillator frequency - to perform output voltage regulation.
The value of RFmax determines the maximum frequency at which the half-bridge is
operated when the phototransistor is fully saturated.
3.
An R-C series circuit (CSS+RSS) connected between the pin and ground that enables
the setup of a frequency shift at startup (see Section 6.3: Soft-start). Note that the
contribution of this branch is zero during steady-state operation.
Doc ID 15534 Rev 3
13/31
Application information
Figure 5.
L6599AT
Oscillator internal block diagram
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The following approximate relationships hold for the minimum and the maximum oscillator
frequency respectively:
Equation 1
fmin =
1
3 ⋅ CF ⋅RFmin
;
fmax =
1
3 ⋅ CF ⋅ ( RFmin // RFmax )
After fixing CF in the hundred pF or nF range (consistent with the maximum source
capability of the RFmin pin and trading this off against the total consumption of the device),
the value of RFmin and RFmax is selected so that the oscillator frequency is able to cover the
entire range needed for regulation, from the minimum value fmin (at minimum input voltage
and maximum load) to the maximum value fmax (at maximum input voltage and minimum
load):
Equation 2
RFmin =
1
3 ⋅ CF ⋅ fmin
; RFmax =
RFmin
fmax
−1
fmin
A different selection criterion is given for RFmax in case burst-mode operation at no-load is
used (see Section 6.2: Operation at no load or very light load).
14/31
Doc ID 15534 Rev 3
L6599AT
Application information
Figure 6.
Oscillator waveforms and their relationship with gate-driving signals
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In Figure 6 the timing relationship between the oscillator waveform and the gate-drive
signal, as well as the swinging node of the half-bridge leg (HB) is shown. Note that the lowside gate-drive is turned on while the oscillator's triangle is ramping up and the high-side
gate-drive is turned on while the triangle is ramping down. In this way, at start-up, or as the
IC resumes switching during burst-mode operation, the low-side MOSFET is switched on
first to charge the bootstrap capacitor. As a result, the bootstrap capacitor is always charged
and ready to supply the high-side floating driver.
6.2
Operation at no load or very light load
When the resonant half-bridge is lightly loaded or not loaded at all, its switching frequency is
at its maximum value. To keep the output voltage under control in these conditions and to
avoid losing soft-switching, there must be some significant residual current flowing through
the transformer's magnetizing inductance. This current, however, produces some
associated losses that prevent converter's no-load consumption from achieving very low
values.
To overcome this issue, the L6599AT enables the designer to make the converter operate
intermittently (burst-mode operation), with a series of a few switching cycles spaced out by
long idle periods where both MOSFETs are in OFF-state, so that the average switching
frequency can be substantially reduced. As a result, the average value of the residual
magnetizing current and the associated losses is considerably cut down, thus facilitating the
converter to comply with energy saving recommendations.
The L6599AT can be operated in burst-mode by using pin 5 (STBY): if the voltage applied to
this pin falls below 1.24 V the IC enters an idle state where both gate-drive outputs are low,
the oscillator is stopped, the soft-start capacitor CSS keeps its charge and only the 2 V
reference at RFmin pin stays alive to minimize the IC's consumption and the VCC capacitor's
discharge. The IC resumes normal operation as the voltage on the pin exceeds 1.24 V by 50
mV.
To implement burst-mode operation the voltage applied to the STBY pin needs to be related
to the feedback loop. Figure 7a shows the simplest implementation, suitable for a narrow
input voltage range (e.g. when there is a PFC front-end).
Doc ID 15534 Rev 3
15/31
Application information
Figure 7.
L6599AT
Burst-mode implementation:
a) narrow input voltage range; b) wide input voltage range
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Essentially, RFmax defines the switching frequency fmax above which the L6599AT enters
burst-mode operation. Once fixed fmax, RFmax is derived from the relationship:
Equation 3
RFmax =
3 RFmin
8 fmax
−1
fmin
Note that, unlike the fmax considered in the previous section (“Section 6.1: Oscillator“), here
fmax is associated to a load PoutB greater than the minimum. PoutB is such that the
transformer's peak currents are low enough not to cause audible noise.
The resonant converter's switching frequency, however, depends also on the input voltage.
Therefore, in cases where there is quite a large input voltage range with the circuit of
Figure 7a, the value of PoutB changes considerably. In this case it is recommended to use
the arrangement shown in Figure 7b, where the information on the converter's input voltage
is added to the voltage applied to the STBY pin. Due to the strongly non-linear relationship
between switching frequency and input voltage, it is more practical to find empirically the
right amount of correction RA / (RA + RB) needed to minimize the change of PoutB. Care
should be taken to choose a total value of RA + RB that is much greater than RC to minimize
the effect on the LINE pin voltage (see Section 6.6: Line sensing function).
Whichever circuit is used, its operation can be described as follows. As the load falls below
the value PoutB the frequency tries to exceed the maximum programmed value fmax and the
voltage on the STBY pin (VSTBY) falls below 1.24 V. The IC then stops with both gate-drive
outputs low, so that both MOSFETs of the half-bridge leg are in an OFF-state. The voltage
VSTBY now increases as a result of the feedback reaction to the energy delivery stop and, as
it exceeds 1.29 V, the IC starts switching again. After a while, VSTBY goes down again in
response to the energy burst and stops the IC. In this way the converter works in a burstmode fashion with a nearly constant switching frequency. A further load decrease then
causes a frequency reduction, which can go down to even a few hundred hertz. The timing
diagram of Figure 8 illustrates this kind of operation, showing the most significant signals. A
small capacitor (typically in the hundred pF range) from the STBY pin to ground, placed as
close to the IC as possible to reduce switching noise pick-up, helps get clean operation.
To help the designer meet energy saving requirements even in power-factor-corrected
systems, where a PFC pre-regulator precedes the DC-DC converter, the L6599AT allows
the PFC pre-regulator to be turned off during burst-mode operation, thereby eliminating the
16/31
Doc ID 15534 Rev 3
L6599AT
Application information
no-load consumption of this stage (0.5 1 W). There is no compliance issue because EMC
regulations on low-frequency harmonic emissions refer to nominal load, so no limit is
imposed when the converter operates with light or no load.
To do so, the L6599AT provides pin 9 (PFC_STOP): it is an open collector output, normally
open, that is asserted low when the IC is idle during burst-mode operation. This signal is
externally used for switching off the PFC controller and the pre-regulator as shown in
Figure 9. When the L6599AT is in UVLO the pin is kept open, to let the PFC controller start
first
Figure 8.
Load-dependent operating modes: timing diagram
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Figure 9.
How the L6599AT can switch off a PFC controller at light load
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Doc ID 15534 Rev 3
17/31
Application information
6.3
L6599AT
Soft-start
Generally speaking, the purpose of soft-start is to progressively increase the converter's
power capability when it is started up, so as to avoid excessive inrush current. In resonant
converters the deliverable power depends inversely on frequency, so soft-start is attained by
sweeping the operating frequency from an initial high value until the control loop takes over.
With the L6599AT, the converter's soft startup is easily achieved with the addition of an R-C
series circuit from pin 4 (RFmin) to ground (see Figure 10, left).
Initially, capacitor CSS is totally discharged, so that the series resistor RSS is effectively
parallel to RFmin and the resulting initial frequency is determined by RSS and RFmin only,
since the optocoupler's phototransistor is cut off (as long as the output voltage is not too far
from the regulated value):
Equation 4
fstart =
1
3 ⋅ CF ⋅ ( RFmin // R SS )
The CSS capacitor is progressively charged until its voltage reaches the reference voltage
(2 V) and, consequently, the current through RSS goes to zero. This typically takes 5 times
constants RSS·CSS. However, before this time interval completes, the output voltage comes
close to the regulated value and the feedback loop takes over, so that the optocoupler's
phototransistor determines the operating frequency from that moment onwards.
During this frequency sweep phase the operating frequency decays, following the
exponential charge of CSS. That is, initially it changes relatively quickly but the rate of
change gets slower and slower. This counteracts the non-linear frequency dependence of
the tank circuit that makes the converter's power capability change little as frequency is
away from resonance, and change very quickly as the frequency approaches the resonance
frequency (see Figure 10, right).
Figure 10. Soft-start circuit (left) and power vs. frequency curve in a resonant
half-bridge (right)
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As a result, the average input current increases smoothly, without the peaking that occurs
with linear frequency sweep, and the output voltage reaches the regulated value with almost
no overshoot.
Typically, RSS and CSS are selected based on the following relationships:
18/31
Doc ID 15534 Rev 3
L6599AT
Application information
Equation 5
RSS =
RFmin
3 ⋅ 10 −3
; CSS =
fstart
R SS
−1
fmin
where fstart is recommended to be at least 4 times fmin. The proposed criterion for CSS is
quite empirical and is a compromise between an effective soft-start action and an effective
OCP (see next section). Please refer to the timing diagram of Figure 10 to see some
significant signals during the soft-start phase.
6.4
Current sense, OCP and OLP
The resonant half-bridge is essentially voltage-mode controlled; hence a current sense input
only serves as overcurrent protection (OCP).
Unlike PWM-controlled converters, where energy flow is controlled by the duty cycle of the
primary switch (or switches), in a resonant half-bridge the duty cycle is fixed and energy flow
is controlled by its switching frequency. This impacts the way current limitation can be
realized. While in PWM-controlled converters energy flow can be limited simply by
terminating switch conduction beforehand when the sensed current exceeds a preset
threshold (this is commonly known as cycle-by-cycle limitation), in a resonant half-bridge the
switching frequency (that is, its oscillator frequency) must be increased and this cannot be
done as quickly as turning off a switch: it takes at least the next oscillator cycle to see the
frequency change. This implies that to have an effective increase, capable of changing the
energy flow significantly, the rate of change of the frequency must be slower than the
frequency itself. This, in turn, implies that cycle-by-cycle limitation is not feasible and that,
therefore, the information on the primary current fed to the current sensing input must be
somehow averaged. Of course, the averaging time must not be too long, to prevent the
primary current from reaching excessively high values.
In Figure 11, a few current sensing methods are illustrated that are described in the
following paragraphs. The circuit in Figure 11a is more simple, but the dissipation on the
sense resistor Rs may not be negligible, decreasing efficiency. The circuit in Figure 11b is
more complex, but virtually lossless and recommended when the efficiency target is very
high.
Doc ID 15534 Rev 3
19/31
Application information
L6599AT
Figure 11. Current sensing techniques: a) with sense resistor, b) “lossless”,
with capacitive shunt
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The L6599AT is equipped with a current sensing input (pin 6, ISEN) and a sophisticated
overcurrent management system. The ISEN pin is internally connected to the input of a first
comparator, referenced to 0.8 V, and to that of a second comparator referenced to 1.5 V. If
the voltage externally applied to the pin by either circuit in Figure 11 exceeds 0.8 V, the first
comparator is tripped and this causes an internal switch to be turned on and the soft-start
capacitor CSS to be discharged (see Section 6.3: Soft-start). This quickly increases the
oscillator frequency and thereby limits energy transfer. The discharge continues until the
voltage on the ISEN pin has dropped by 50 mV; this, with an averaging time in the range of
10/fmin, ensures an effective frequency rise. Under output short-circuit, this operation results
in a nearly constant peak primary current.
It is normal that the voltage on the ISEN pin could overshoot the 0.8 V. However, if the
voltage on the ISEN pin reaches 1.5 V, the second comparator is triggered and the L6599AT
shuts down and latches off with both the gate-drive outputs and the PFC_STOP pin low,
hence turning off the entire unit. The supply voltage of the IC must be pulled below the
UVLO threshold and then again above the start-up level in order to restart. Such an event
may occur if the soft-start capacitor CSS is too large, preventing it from discharging fast
enough, in cases of saturation of the transformer’s magnetizing inductance or a shorted
secondary rectifier.
In the circuit shown in Figure 11a, where a sense resistor Rs in series with the source of the
low-side MOSFET is used, note the specific connection of the resonant capacitor. In this
way, the voltage across Rs is related to the current flowing through the high-side MOSFET
and is positive most of the switching period, except for the time needed for the resonant
current to reverse after the low-side MOSFET has been switched off. Assuming that the time
constant of the RC filter is at least ten times the minimum switching frequency fmin, the
approximate value of Rs can be found using the empirical equation:
Equation 6
Rs =
Vs pkx
ICrpkx
≈
5 ⋅ 0. 8
4
≈
ICrpkx
ICrpkx
where ICrpkx is the maximum desired peak current flowing through the resonant capacitor
and the primary winding of the transformer, which is related to the maximum load and the
minimum input voltage.
20/31
Doc ID 15534 Rev 3
L6599AT
Application information
The circuit shown in Figure 11b can be operated in two different ways. If the resistor RA in
series to CA is small (not above a few hundred ohms, just to limit current spiking) the circuit
operates like a capacitive current divider; CA is typically selected equal to Cr/100 or less and
is a low-loss type, and the sense resistor RB is selected as:
Equation 7
RB =
C ⎞
0 .8 π ⎛
⎜1 + r ⎟
ICrpkx ⎜⎝ C A ⎟⎠
and CB is such that RB·CB is in the range of 10 /fmin.
If the resistor RA in series with CA is not small (in this case it is typically selected in the ten
kΩ range), the circuit operates like a divider of the ripple voltage across the resonant
capacitor Cr, which, in turn, is related to its current through the reactance of Cr. Again, CA is
typically selected equal to Cr/100 or less, this time not necessarily a low-loss type, while RB
(provided it is << RA) according to:
Equation 8
2
2
0 .8 π R A + X C A
RB =
ICrpkx
X Cr
where the reactance of CA (XCA) and Cr (XCr) should be calculated at the frequency where
ICrpk = ICrpkx. Again, CB is such that RB·CB is in the range of 10 /fmin.
Whichever circuit is used, the calculated values of Rs or RB should be considered
preliminary values that may need to be adjusted after experimental verification.
OCP is effective in limiting primary-to-secondary energy flow in case of an overload or an
output short-circuit, but the output current through the secondary winding and rectifiers
under these conditions might be so high that they endanger the converter’s safety if
continuously flowing. To prevent any damage during these conditions it is customary to force
the intermittent operation of the converter, in order to bring the average output current to
values such that the thermal stress for the transformer and the rectifiers can be easily
handled.
With the L6599AT the designer can externally program the maximum time TSH that the
converter is allowed to run overloaded or under short-circuit conditions. Overloads or shortcircuits lasting less than TSH do not cause any other action, hence providing the system with
immunity to short duration phenomena. If, instead, TSH is exceeded an overload protection
(OLP) procedure is activated that shuts down the L6599AT and, in cases of continuous
overload/short-circuit, results in continuous intermittent operation with a user-defined duty
cycle.
Doc ID 15534 Rev 3
21/31
Application information
L6599AT
Figure 12. Soft-start and delayed shutdown upon overcurrent timing diagram
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This function is achieved with pin 2 (DELAY), by means of a capacitor CDelay and a parallel
resistor RDelay connected to ground. As the voltage on the ISEN pin exceeds 0.8 V the first
OCP comparator, in addition to discharging CSS, turns on an internal current generator that
sources 150 µA from the DELAY pin and charges CDelay. During an overload/short-circuit
the OCP comparator and the internal current source are repeatedly activated and CDelay is
charged with an average current that depends essentially on the time constant of the current
sense filtering circuit, on CSS and the characteristics of the resonant circuit. The discharge
due to RDelay can be neglected, considering that the associated time constant is typically
much longer.
This operation continues until the voltage on CDelay reaches 2 V, which defines the TSH time.
There is not a simple relationship that links TSH to CDelay, thus it is more practical to
determine CDelay experimentally. As a rough indication, with CDelay = 1 µF, TSH is in the
order of 100 ms.
Once CDelay is charged at 2 V the internal switch that discharges CSS is forced low
continuously regardless of the OCP comparator’s output, and the 150 µA current source is
continuously on, until the voltage on CDelay reaches 3.5 V. This phase lasts:
Equation 9
TMP = 10 ⋅ CDelay
with TMP expressed in ms and CDelay in µF. During this time, the L6599AT runs at a
frequency close to fstart (see Section 6.3: Soft-start) to minimize the energy inside the
resonant circuit. As the voltage on CDelay is 3.5 V, the L6599AT stops switching and the
PFC_STOP pin is pulled low. Also, the internal generator is turned off, so that CDelay is now
slowly discharged by RDelay. The IC restarts when the voltage on CDelay is less than 0.3 V,
which takes:
Equation 10
TSTOP = RDelay CDelay ln 30..53 ≈ 2.5 RDelay CDelay
22/31
Doc ID 15534 Rev 3
L6599AT
Application information
The timing diagram in Figure 12 shows this operation. Note that if during TSTOP the supply
voltage of the L6599AT (Vcc) falls below the UVLO threshold the IC retains memory of the
event and does not restart immediately after Vcc exceeds the start-up threshold if V(DELAY)
is still higher than 0.3 V. Also the PFC_STOP pin stays low as long as V(DELAY) is greater
than 0.3 V. Note also that in case there is an overload lasting less than TSH, the value of TSH
for the next overload is lower if they are close to one another.
6.5
Latched shutdown
The L6599AT is equipped with a comparator having the non-inverting input externally
available at pin 8 (DIS) and with the inverting input internally referenced to 1.85 V. As the
voltage on the pin exceeds the internal threshold, the IC is immediately shut down and its
consumption reduced at a low value. The information is latched and it is necessary to let the
voltage on the Vcc pin go below the UVLO threshold to reset the latch and restart the IC.
This function is useful to implement latched overtemperature protection very easily by
biasing the pin with a divider from an external reference voltage (e.g. pin 4, RFmin), where
the upper resistor is an NTC physically located close to a heating element like the MOSFET,
or the secondary diode or the transformer.
An OVP can be implemented as well, e.g. by sensing the output voltage and transferring an
overvoltage condition via an optocoupler.
6.6
Line sensing function
This function basically stops the IC as the input voltage to the converter falls below the
specified range and allows restart as the voltage goes back within the range. The sensed
voltage can be either the rectified and filtered mains voltage, in which case the function acts
as brownout protection or, in systems with a PFC pre-regulator front-end, the output voltage
of the PFC stage, in which case the function serves as a power-on and power-off
sequencing.
L6599AT shutdown upon input undervoltage is accomplished by means of an internal
comparator, as shown in the block diagram of Figure 13, whose non-inverting input is
available at pin 7 (LINE). The comparator is internally referenced to 1.24 V and disables the
IC if the voltage applied at the LINE pin is below the internal reference. Under these
conditions the soft-start is discharged, the PFC_STOP pin is open and the consumption of
the IC is reduced. PWM operation is re-enabled as the voltage on the pin is above the
reference. The comparator is provided with current hysteresis instead of a more usual
voltage hysteresis: an internal 13 µA current sink is ON as long as the voltage applied at the
LINE pin is below the reference and is OFF if the voltage is above the reference.
This approach provides an additional degree of freedom: it is possible to set the ON
threshold and the OFF threshold separately by properly choosing the resistors of the
external divider (see below). With voltage hysteresis, instead, fixing one threshold
automatically fixes the other one depending on the built-in hysteresis of the comparator.
Doc ID 15534 Rev 3
23/31
Application information
L6599AT
Figure 13. Line sensing function: internal block diagram and timing diagram
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With reference to Figure 11, the following relationships can be established for the ON
(VinON) and OFF (VinOFF) thresholds of the input voltage:
Equation 11
Vin ON − 1.24
1.24
= 13 ⋅ 10 − 6 +
RL
RH
VinOFF − 1.24 1.24
=
RH
RL
which, solved for RH and RL, yield:
Equation 12
RH =
VinON − VinOFF
13 ⋅ 10 − 6
;
RL = RH
1.24
Vin OFF − 1.24
While the line undervoltage is active the start-up generator continues working but there is no
PWM activity, thus the Vcc voltage (if not supplied by another source) continuously oscillates
between the start-up and the UVLO thresholds, as shown in the timing diagram of
Figure 13.
As an additional measure of safety (e.g. in cases where the low-side resistor is open or
missing, or in non-power factor corrected systems in cases of abnormally high input voltage)
if the voltage on the pin exceeds 7 V, the L6599AT is shut down. If its supply voltage is
always above the UVLO threshold, the IC restarts as the voltage falls below 7 V.
The LINE pin, while the device is operating, is a high impedance input connected to high
value resistors, thus it is prone to pick up noise, which might alter the OFF threshold or give
origin to undesired switch-off of the IC during ESD tests. It is possible to bypass the pin to
ground with a small film capacitor (e.g. 1-10 nF) to prevent any malfunctioning of this kind. If
24/31
Doc ID 15534 Rev 3
L6599AT
Application information
the function is not used the pin must be connected to a voltage greater than 1.24 V but lower
than 6 V (worst-case value of the 7 V threshold).
6.7
Bootstrap section
The supply of the floating high-side section is obtained by means of bootstrap circuitry. This
solution normally requires a high voltage fast recovery diode (DBOOT, Figure 14a) to charge
the bootstrap capacitor CBOOT. In the L6599AT, a patented integrated structure replaces this
external diode. It is achieved by means of a high voltage DMOS, working in the third
quadrant and driven synchronously with the low side driver (LVG), with a diode in series to
the source, as shown in Figure 14b.
Figure 14. Bootstrap supply: a) standard circuit;
b) internal bootstrap synchronous diode
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The diode prevents any current flowing from the VBOOT pin back to Vcc if the supply is
quickly turned off when the internal capacitor of the pump is not fully discharged. To drive
the synchronous DMOS a voltage higher than the supply voltage Vcc is necessary. This
voltage is obtained by means of an internal charge pump (Figure 14b).
The bootstrap structure introduces a voltage drop while recharging CBOOT (i.e. when the
low side driver is on), which increases with the operating frequency and with the size of the
external power MOS. It is the sum of the drop across the R(DS)ON and the forward drop
across the series diode. At low frequency this drop is very small and can be neglected but,
as the operating frequency increases, it must be taken into account. In fact, the drop
reduces the amplitude of the driving signal and can significantly increase the R(DS)ON of the
external high-side MOSFET and then its conductive loss.
This concern applies to converters designed with a high resonance frequency (indicatively,
> 150 kHz), so that they run at high frequency also at full load. Otherwise, the converter runs
at high frequency at light load, where the current flowing in the MOSFETs of the half-bridge
leg is low, so that, generally, an R(DS)ON rise is not an issue. However, it is wise to check this
point anyway and the following equation is useful to compute the drop on the bootstrap
driver:
Doc ID 15534 Rev 3
25/31
Application information
L6599AT
Equation 13
VDrop = Ich arg eR(DS)on + VF =
Qg
Tch arg e
R(DS)on + VF
where Qg is the gate charge of the external power MOS, R(DS)ON is the on-resistance of the
bootstrap DMOS (150 W, typ.) and Tcharge is the ON-time of the bootstrap driver, which
equals about half the switching period minus the dead time TD. For example, using a
MOSFET with a total gate charge of 30 nC, the drop on the bootstrap driver is about 3 V at a
switching frequency of 200 kHz:
Equation 14
VDrop =
30 ⋅ 10 −9
2.5 ⋅ 10 − 6 − 0.27 ⋅ 10 −6
150 + 0.6 = 2.7 V
If a significant drop on the bootstrap driver is an issue, an external ultra-fast diode can be
used, thus saving the drop on the R(DS)ON of the internal DMOS.
26/31
Doc ID 15534 Rev 3
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L6599AT
Application information
Figure 15. Application example: 90 W AC-DC adapter using L6563 and L6599AT
!-V
27/31
Package mechanical data
7
L6599AT
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Figure 16. DIP16 mechanical data
mm
DIM.
MIN.
a1
0.51
B
0.77
TYP.
inch
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
OUTLINE AND
MECHANICAL DATA
3.3
0.130
DIP16
Z
28/31
1.27
0.050
Doc ID 15534 Rev 3
L6599AT
Package mechanical data
Figure 17. SO16N mechanical data
mm
inch
DIM.
MIN.
TYP.
A
a1
MAX.
MIN.
TYP.
1.75
0.1
0.25
a2
0.069
0.004
0.063
b
0.35
0.46
0.014
b1
0.19
0.25
0.007
0.5
c1
0.018
0.010
0.020
45°
(typ.)
D(1)
9.8
10
0.386
0.394
E
5.8
6.2
0.228
0.244
e
1.27
e3
8.89
0.050
0.350
3.8
4.0
G
4.60
5.30
0.181
0.208
L
0.4
1.27
0.150
0.050
F
(1)
M
S
OUTLINE AND
MECHANICAL DATA
0.009
1.6
C
MAX.
0.150
0.62
0.157
0.024
8 ° (max.)
SO16 (Narrow)
(1) "D" and "F" do not include mold flash or protrusions - Mold
flash or protrusions shall not exceed 0.15mm (.006inc.)
0016020 D
Doc ID 15534 Rev 3
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Revision history
8
L6599AT
Revision history
Table 6.
30/31
Document revision history
Date
Revision
Changes
05-Jun-2009
1
Initial release.
11-Aug-2009
2
Updated Table 5 on page 9
30-Oct-2009
3
Updated Table 5 on page 9
Doc ID 15534 Rev 3
L6599AT
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