TPD2E001 LOW-CAPACITANCE 2-CHANNEL ±15-kV ESD-PROTECTION ARRAY FOR HIGH-SPEED DATA INTERFACES www.ti.com SLLS684C – JULY 2006 – REVISED MAY 2007 FEATURES APPLICATIONS • • • • • • • • • • • • • • • ESD Protection Exceeds – ±15-kV Human-Body Model (HBM) – ±8-kV IEC 61000-4-2 Contact Discharge – ±15-kV IEC 61000-4-2 Air-Gap Discharge Low 1.5-pF Input Capacitance Low 1-nA (Max) Leakage Current Low 1-nA Supply Current 0.9-V to 5.5-V Supply-Voltage Range Two-Channel Device Space-Saving DRL, DRY, and QFN Package Options Alternate 3-, 4-, 6-Channel Options Available: TPD3E001, TPD4E001, and TPD6E001 USB 2.0 Ethernet FireWire™ Video Cell Phones SVGA Video Connections Glucosemeters DESCRIPTION/ORDERING INFORMATION The TPD2E001 is a low-capacitance ±15-kV ESD-protection diode array designed to protect sensitive electronics attached to communication lines. Each channel consists of a pair of diodes that steer ESD current pulses to VCC or GND. The TPD2E001 protects against ESD pulses up to ±15-kV Human-Body Model (HBM), ±8-kV Contact Discharge, and ±15-kV Air-Gap Discharge, as specified in IEC 61000-4-2. This device has a 1.5-pF capacitance per channel, making it ideal for use in high-speed data IO interfaces. The TPD2E001 is a two-channel device intended for USB and USB 2.0 applications. The TPD2E001 is available in DRL, DRY, and thin QFN packages and is specified for –40°C to 85°C operation. ORDERING INFORMATION PACKAGE (1) (2) TA –40°C to 85°C (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING NanoStar™– WCSP (DSBGA) – YFP (Pb-free) Tape and reel TPD2E001YFPR PREVIEW SOP – DZD Tape and reel TPD2E001DZDR PREVIEW 1.6 × 1.6 SOP (SOT-533) – DRL Reel of 4000 TPD2E001DRLR 2AR 1.45 × 1 SON – DRY Reel of 5000 TPD2E001DRYR 2A 3 × 3 QFN – DRS Reel of 1000 TPD2E001DRSR ZWK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar is a trademark of Texas Instruments. FireWire is a trademark of Apple Computer, Inc. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2007, Texas Instruments Incorporated TPD2E001 LOW-CAPACITANCE 2-CHANNEL ±15-kV ESD-PROTECTION ARRAY FOR HIGH-SPEED DATA INTERFACES www.ti.com SLLS684C – JULY 2006 – REVISED MAY 2007 DRL PACKAGE (TOP VIEW) DRY PACKAGE (TOP VIEW) VCC 1 N.C. N.C. 2 GND IO1 3 VCC 1 6 IO2 N.C. 2 5 IO1 3 4 DRS PACKAGE (TOP VIEW) IO2 5 IO1 4 1 P2R W IE N.C. 2 IO1 3 GND 6 IO2 5 N.C. 4 GND YFP PACKAGE (TOP VIEW) VCC EV 3 1 GND 4 DZD PACKAGE (TOP VIEW) GND VCC W I4E VCC V E IO2 GND 1 IO1 2 PR IO2 3 N.C. – Not internally connected LOGIC BLOCK DIAGRAM VCC IO2 IO1 GND PIN DESCRIPTION DRS NO. DRL NO. DRY NO. 1, 4 3, 5 3, 6 IOx 3 4 4 GND Ground 6 1 1 VCC Power-supply input. Bypass VCC to GND with a 0.1-µF ceramic capacitor. 5 2 2, 5 NC No connection. Not internally connected. EP Exposed pad. Connect to GND. EP 2 NAME FUNCTION ESD-protected channel Submit Documentation Feedback www.ti.com TPD2E001 LOW-CAPACITANCE 2-CHANNEL ±15-kV ESD-PROTECTION ARRAY FOR HIGH-SPEED DATA INTERFACES SLLS684C – JULY 2006 – REVISED MAY 2007 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC –0.3 7 V VIO –0.3 VCC + 0.3 V –65 150 °C 150 °C Tstg Storage temperature range TJ Junction temperature Bump temperature (soldering) Infrared (15 s) 220 Vapor phase (60 s) 215 Lead temperature (soldering, 10 s) (1) UNIT °C °C 300 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute-maximum-rating conditions for extended periods may affect device reliability. Electrical Characteristics VCC = 5 V ± 10%, TA = -40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS VCC Supply voltage ICC Supply current VF Diode forward voltage IF = 10 mA VBR Breakdown Voltage IBR = 10mA Channel clamp voltage (2) VC TYP (1) MAX 0.9 1 0.65 UNIT 5.5 V 100 nA 0.95 V 11 TA = 25°C, ±15-kV HBM, IF = 10 A Positive transients TA = 25°C, ±8-kV Contact Discharge (IEC 61000-4-2), IF = 24 A Positive transients TA = 25°C, ±15-kV Air-Gap Discharge (IEC 61000-4-2), IF = 45 A Positive transients Ii/o Channel leakage current Vi/o = GND to VCC Ci/o Channel input capacitance VCC = 5 V, Bias of VCC/2 (1) (2) MIN V VCC + 25 Negative transients –25 VCC + 60 Negative transients –60 V VCC + 100 Negative transients –100 ±1 1.5 nA pF Typical values are at VCC = 5 V and TA = 25°C Channel clamp voltage is not production tested. ESD Protection PARAMETER TYP UNIT ±15 kV IEC 61000-4-2 Contact Discharge ±8 kV IEC 61000-4-2 Air-Gap Discharge ±15 kV HBM Submit Documentation Feedback 3 TPD2E001 LOW-CAPACITANCE 2-CHANNEL ±15-kV ESD-PROTECTION ARRAY FOR HIGH-SPEED DATA INTERFACES www.ti.com SLLS684C – JULY 2006 – REVISED MAY 2007 TYPICAL OPERATING CHARACTERISTICS IO CAPACITANCE vs IO VOLTAGE (VCC = 5.0 V) 2.20 IO Capacitance (pF) 2.00 1.80 1.60 1.40 1.20 1.00 0.00 1.00 2.00 2.50 3.00 4.00 5.00 IO Voltage (V) IO LEAKAGE CURRENT vs TEMPERATURE (VCC = 5.5 V) IO Leakage Current (pA) 1000 100 10 1 –40 25 45 Temperature (°C) 4 Submit Documentation Feedback 65 85 TPD2E001 LOW-CAPACITANCE 2-CHANNEL ±15-kV ESD-PROTECTION ARRAY FOR HIGH-SPEED DATA INTERFACES www.ti.com SLLS684C – JULY 2006 – REVISED MAY 2007 APPLICATION INFORMATION VCC 0.1 µF VBUS RT IO1 D+ USB Controller RT D1 D– IO2 GND GND Detailed Description When placed near the connector, the TPD2E001 ESD solution offers little or no signal distortion during normal operation due to low IO capacitance and ultra-low leakage current specifications. The TPD2E001 ensures that the core circuitry is protected and the system is functioning properly in the event of an ESD strike. For proper operation, the following layout/ design guidelines should be followed: 1. Place the TPD2E001 solution close to the connector. This allows the TPD2E001 to take away the energy associated with ESD strike before it reaches the internal circuitry of the system board. 2. Place a 0.1-µF capacitor very close to the VCC pin. This limits any momentary voltage surge at the IO pin during the ESD strike event. 3. Make sure that there is enough metallization for the VCC and GND loop. During normal operation, the TPD2E001 consumes nA leakage current. But during the ESD event, VCC and GND may see 15 A to 30 A of current, depending on the ESD level. Sufficient current path enables safe discharge of all the energy associated with the ESD strike. 4. Leave the unused IO pins floating . 5. The VCC pin can be connected in two different ways: a. If the VCC pin is connected to the system power supply, the TPD2E001 works as a transient suppressor for any signal swing above VCC + VF. A 0.1-µF capacitor on the device VCC pin is recommended for ESD bypass. b. If the VCC pin is not connected to the system power supply, the TPD2E001 can tolerate higher signal swing in the range up to 10V. Please note that a 0.1µF capacitor is still recommended at the VCC pin for ESD bypass. Submit Documentation Feedback 5 PACKAGE OPTION ADDENDUM www.ti.com 17-May-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPD2E001DRLR ACTIVE SOT-553 DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPD2E001DRLRG4 ACTIVE SOT-553 DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPD2E001DRYR ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 18-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 18-May-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPD2E001DRLR DRL 5 HNT 180 9 1.78 1.78 0.69 4 8 Q3 TPD2E001DRYR DRY 6 NSE 179 8 1.2 1.65 0.7 4 8 Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) TPD2E001DRLR DRL TPD2E001DRYR DRY 5 HNT 201.0 192.0 26.0 6 NSE 220.0 205.0 50.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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