TI TLC59461PWP

TLC59461
www.ti.com............................................................................................................................................... SLVS896A – NOVEMBER 2008 – REVISED MARCH 2009
16-Channel, 12-Bit PWM LED Driver with
6-Bit Dot Correction
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
1
23
•
•
•
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16 Channels, Constant-Current Sink Output
40-mA Capability (Constant-Current Sink)
12-Bit (4096 Steps) Grayscale PWM Control
6-Bit (64 Steps) Dot Correction
LED Power-Supply Voltage up to 17 V
VCC = 3.0 V to 5.5 V
Constant-Current Accuracy:
– Channel-to-Channel = ±1% (typ)
– Device-to-Device = ±2% (typ)
30-MHz Data Transfer Rate
33-MHz Grayscale PWM Clock
Extended Serial Interface
CMOS Level I/O
Schmitt Buffer Input
Readable Error Information:
– Continuous Base LED Open Detection
(LOD)
– Thermal Error Flag (TEF)
Noise Reduction:
– 4-Channel Grouped Delay
Operating Temperature: –40°C to +85°C
VLED
•
•
Monochrome, Multicolor, Full-Color LED
Displays
LED Signboards
Display Backlighting
DESCRIPTION
The TLC59461 is a 16-channel, constant-current sink
LED driver. Each channel is individually adjustable
with 4096 pulse-width modulated (PWM) steps and
64 constant-current sink steps for dot correction. The
dot correction adjusts the brightness variations
between LEDs. Both grayscale control and dot
correction are accessible via serial interface. The
maximum current value of all 16 channels can be set
by a single external resistor.
The TLC59461 has two error information circuits: one
for LED open detection (LOD), and a thermal error
flag (TEF). LOD detects a broken or disconnected
LED during display period. TEF indicates an
over-temperature condition.
To allow lower power dissipation, the TLC59461 does
not implement the Auto Output Off function available
in the TLC5946.
VLED
VLED
VLED
VCC
¼
OUT0
OUT
XERR
¼
OUT0
OUT15
SOUT
TLC59461
IC1
MODE
BLANK
GSCLK
SOUT
SCLK
XLAT
MODE
OUT15
XERR
SCLK
XLAT
¼
SIN
XERR
SCLK
Controller
¼
SIN
¼
XLAT
VCC
MODE
TLC59461
ICn
VCC
BLANK
VCC
BLANK
VCC
GSCLK
XHALF
GSCLK
XHALF
IN
GND
IREF
RIREF
IREF
GND
RIREF
6
Typical Application Circuit (Multiple Daisy-Chained TLC59461s)
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2009, Texas Instruments Incorporated
TLC59461
SLVS896A – NOVEMBER 2008 – REVISED MARCH 2009............................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
(1)
PRODUCT
PACKAGE-LEAD
TLC59461
HTSSOP-28 PowerPAD™
ORDERING NUMBER
TRANSPORT MEDIA,
QUANTITY
TLC59461PWPR
Tape and Reel, 2000
TLC59461PWP
Tube, 50
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1) (2)
Over operating free-air temperature range, unless otherwise noted.
PARAMETER
VCC
TLC59461
Supply voltage: VCC
UNIT
–0.3 to +6.0
V
OUT0 to OUT15
50
mA
XERR
6
mA
–0.3 to VCC + 0.3
V
–0.3 to VCC + 0.3
V
IOUT
Output current (dc)
VIN
Input voltage range: SIN, SCLK, GSCLK, XLAT, BLANK, MODE, XHALF,
IREF
VOUT
Output voltage range
–0.3 to +18
V
TJ(ABS)
Operating temperature range: junction temperature
–40 to +150
°C
TSTG
Storage temperature range
–55 to +150
°C
2
kV
500
V
SOUT, XERR
OUT0 to OUT15
Human body model (HBM),
JEDEC JESD22-A114
ESD rating
(1)
(2)
Charged device model (CDM),
JEDEC JESD22-C101
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
All voltage values are with respect to network ground terminal.
DISSIPATION RATINGS
(1)
(2)
2
PACKAGE
OPERATING FACTOR
ABOVE TA = +25°C
TA < +25°C
POWER RATING
TA = +70°C
POWER RATING
TA = +85°C
POWER RATING
HTSSOP-28 with
PowerPAD soldered (1)
31.67 mW/°C
3958 mW
2533 mW
2058 mW
HTSSOP-28 with
PowerPAD not soldered (2)
16.21 mW/°C
2026 mW
1296 mW
1053 mW
With PowerPAD soldered onto copper area on printed circuit board (PCB); 2 oz. copper. For more information, see SLMA002 (available
for download at www.ti.com).
With PowerPAD not soldered onto copper area on PCB.
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TLC59461
www.ti.com............................................................................................................................................... SLVS896A – NOVEMBER 2008 – REVISED MARCH 2009
RECOMMENDED OPERATING CONDITIONS
At TA = –40°C to +85°C, unless otherwise noted.
TLC59461
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DC Characteristics: VCC = 3 V to 5.5 V
VCC
Supply voltage
VO
Voltage applied to output
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
IOLC
Constant output sink current
3.0
5.5
V
17
V
0.7 × VCC
VCC
V
GND
0.3 × VCC
OUT0 to OUT15
V
SOUT
–1
mA
SOUT
1
mA
XERR
5
mA
4
40
mA
TA
Operating free-air temperature
range
–40
+85
°C
TJ
Operating junction temperature
–40
+125
°C
OUT0 to OUT15, DC = 3Fh
AC Characteristics: VCC = 3 V to 5.5 V
fCLK (sclk)
Data shift clock frequency
fCLK (gsclk)
Grayscale control clock frequency
TWH0 / TWL0
SCLK pulse duration
TWH1 / TWL1
GSCLK pulse duration
TWH2
XLAT pulse duration
TWH3
BLANK pulse duration
SCLK, XHALF = H
30
MHz
GSCLK, XHALF = L
15
MHz
GSCLK
33
MHz
SCLK = H/L (see Figure 12)
10
ns
GSCLK = H/L (see Figure 12)
10
ns
XLAT = H (see Figure 12)
20
ns
BLANK = H (see Figure 12)
20
ns
TSU0
SIN–SCLK↑ (see Figure 12)
5
ns
TSU1
XLAT↑–SCLK↑
(see Figure 37, Figure 12)
100
ns
TSU2
MODE–SCLK↑ (see Figure 12)
10
ns
TSU3
MODE–XLAT↑ (see Figure 12)
10
ns
TSU4
Setup time
BLANK↓–GSCLK↑ (see Figure 12)
10
ns
TSU5
XLAT↑–GSCLK↑ (see Figure 12)
30
ns
TSU6
SCLK↓–XLAT↑
(see Figure 12, Figure 37)
10
ns
TH0
TH1
Hold time
TH2
SIN–SCLK↑ (see Figure 12)
3
ns
MODE–SCLK↓ (see Figure 12)
10
ns
MODE–XLAT↑ (see Figure 12)
100
ns
AC Characteristics: VCC = 3 V to 5.5 V, XHALF = L
TWL2
XLAT pulse duration
XLAT = L (see Figure 37)
20
ns
TSU7
Setup time
BLANK↑–XLAT↑ (see Figure 37)
20
ns
TH3
Hold time
BLANK↓–XLAT↓ (see Figure 37)
20
ns
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TLC59461
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ELECTRICAL CHARACTERISTICS
At VCC = 3.0 V to 5.5 V, TA = –40°C to +85°C, and RIREF = 1.3kΩ. Typical values at VCC = 3.3 V and TA = +25°C, unless
otherwise noted.
TLC59461
PARAMETER
VOH
TEST CONDITIONS
High-level output voltage
VOL
Low-level output voltage
IIN
IOH = –1 mA at SOUT
ICC1
ICC2
Supply current
TYP
MAX
VCC – 0.4
UNIT
V
IOL = 1 mA at SOUT
0.4
V
IOL = 5 mA at XERR
0.5
V
1
µA
VIN = VCC or GND at BLANK, XHALF, GSCLK, SCLK,
SIN, XLAT, and MODE pins
Input current
MIN
–1
No data transfer, all OUTn = OFF, VOUTn = 1 V,
DCn = 3Fh, RIREF = 13 kΩ
0.9
3
mA
No data transfer, all OUTn = OFF, VOUTn = 1 V,
DCn = 3Fh, RIREF = 2.7 kΩ
4
8
mA
ICC3
Data transfer at 30 MHz, all OUTn = ON, VOUTn = 1 V,
DCn = 3Fh, RIREF = 2.7 kΩ
13
25
mA
ICC4
Data transfer at 30 MHz, all OUTn = ON, VOUTn = 1 V,
DCn = 3Fh
20
45
mA
39.0
IOLC
Constant output current
All OUTn = ON, VOUTn = 1 V, VOUTfix = 1 V, DCn = 3Fh
42.5
mA
IOLK1
Output leakage current
All OUTn = OFF, VOUTn = 17 V, DCn = 3Fh
At OUT0 to OUT15
0.1
µA
IOLK2
Output leakage current
No error condition, VXERR = 5.5 V, at XERR
1
µA
ΔIOLC
Constant-current error
(channel-to-channel) (1)
All OUTn = ON, VOUTn = 1 V, VOUTfix = 1 V, DCn = 3Fh
±1
±3
%
ΔIOLC1
Constant-current error
(device-to-device) (2)
All OUTn = ON, VOUTn = 1 V, VOUTfix = 1 V, DCn = 3Fh
±2
±6
%
ΔIOLC2
Line regulation (3)
All OUTn = ON, VOUTn = 1 V, VOUTfix = 1 V,
VCC = 3.0 V to 5.5 V, DCn = 3Fh
±0.5
±1
%
ΔIOLC3
Load regulation (4)
All OUTn = ON, VOUTn = 1 V to 3 V,
VOUTfix = 1 V, DCn = 3Fh
±1
±3
%/V
(5)
35.5
TTEF
Thermal error flag threshold
Junction temperature
+150
+162
+175
°C
THYS
Thermal error hysteresis
Junction temperature (5)
+5
+10
+20
°C
VLOD
LED open detection threshold
All OUTn = ON
0.2
0.3
0.4
V
VIREF
Reference voltage output
1.16
1.20
1.24
V
(1)
The deviation of each output from the average of OUT0-OUT15 constant current. Deviation is calculated by the formula:
IOUTn
D (%) =
-1
´ 100
(IOUT0 + IOUT1 + ... + IOUT15)
(2)
16
.
The deviation of the OUT0-OUT15 constant-current average from the ideal constant-current value.
Deviation is calculated by the following formula:
(IOUT0 + IOUT1 + ... IOUT14 + IOUT15)
- (Ideal Output Current)
16
D (%) =
´ 100
Ideal Output Current
Ideal current is calculated by the formula:
1.20
IOUT(IDEAL) = 42.5 ´
(3)
RIREF
Line regulation is calculated by this equation:
D (%/V) =
(IOUTn at VCC = 5.5 V) - (IOUTn at VCC = 3.0 V)
(4)
(IOUTn at VOUTn = 3 V) - (IOUTn at VOUTn = 1 V)
100
´
(IOUTn at VOUTn = 1 V)
4
5.5 V - 3 V
Load regulation is calculated by the equation:
D (%/V) =
(5)
100
´
(IOUTn at VCC = 3.0 V)
3V-1V
Not tested. Specified by design.
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Product Folder Link(s): TLC59461
TLC59461
www.ti.com............................................................................................................................................... SLVS896A – NOVEMBER 2008 – REVISED MARCH 2009
SWITCHING CHARACTERISTICS
At VCC = 3.0 V to 5.5 V, TA = –40°C to +85°C, CL0 = 15 pF, RL0 = 100 Ω, CL1 = 100 pF, RL1 = 1 kΩ, RIREF = 1.3 kΩ,
VLED = 5 V, and VXERR = 5 V. Typical values at VCC = 3.3 V and TA = +25°C, unless otherwise noted.
TLC59461
PARAMETER
tR0
Rise time
tR1
tF0
TEST CONDITIONS
MIN
TYP
SOUT (see Figure 11)
16
OUTn, VCC = 5 V, DC = 3Fh (see Figure 11)
10
SOUT (see Figure 11)
tF1
Fall time
tF2
30
16
OUTn, VCC = 5 V, DC = 3Fh (see Figure 11)
10
XERR (see Figure 11)
(1)
tD0
SCLK to SOUT (see Figure 12)
tD1
BLANK↑ to OUT0 sink current off (see Figure 12)
tD2
GSCLK↑ to OUT0/4/8/12 (see Figure 12)
tD3
MAX
30
UNIT
ns
ns
100
ns
25
ns
20
40
ns
5
18
40
ns
GSCLK↑ to OUT1/5/9/13 (see Figure 12)
20
42
73
ns
tD4
GSCLK↑ to OUT2/6/10/14 (see Figure 12)
35
66
106
ns
tD5
GSCLK↑ to OUT3/7/11/15 (see Figure 12)
50
90
140
ns
tD6
XLAT↑ to OUTn (dot correction)
00h to 3Fh, 3Fh to 00h (see Figure 12)
100
ns
10
ns
Propagation delay time
tON_ERR
(1)
Output on-time error
tOUTON – tGSCLK, GSn = 001h, GSCLK = 33 MHz
(see Figure 13)
–20
XHALF = H: rising edge of SCLK to SOUT; XHALF = L: falling edge of SCLK to SOUT.
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TLC59461
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FUNCTIONAL BLOCK DIAGRAM
BLANK, XLAT, SCLK
3
MODE
XERR
XERR
Control
Thermal
Detection
XHALF
MODE, XHALF
LSB
MSB
Shift Register
(96 Bits)
0
MODE, XHALF
2
LSB
MSB
Shift Register
(96 Bits)
SIN
Control
95
2
SOUT
Control
96
SOUT
191
SIN
16
MODE, XHALF
LOD
Data Latch
2
SCLK
Control
SCLK
96
96
33rd GSCLK
MODE, XHALF
2
XLAT
Control
XLAT
GS Data Latch
(OUT8 to OUT15)
GS Data Latch
(OUT0 to OUT7)
96
GSCLK
Grayscale
Counter
96
96
12-Bit PWM Timing Control
16
16
BLANK
Four Grouped Output Delay
16
LSB
MSB
Dot Correction Data Latch
(6 Bits ´ 16 Channels)
0
IREF
Reference
Current
Control
95
96
Constant Current Driver with Dot Correction
VCC
LED Open Detection (LOD)
GND
GND
OUT0
6
OUT1
¼
OUT14
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OUT15
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TLC59461
www.ti.com............................................................................................................................................... SLVS896A – NOVEMBER 2008 – REVISED MARCH 2009
DEVICE INFORMATION
HTSSOP-28
PWP PACKAGE
(TOP VIEW)
GND
1
28
VCC
BLANK
2
27
IREF
XLAT
3
26
XHALF
SCLK
4
25
GSCLK
SIN
5
24
SOUT
MODE
6
23
XERR
OUT0
7
22
OUT15
OUT1
8
21
OUT14
OUT2
9
20
OUT13
OUT3
10
19
OUT12
OUT4
11
18
OUT11
OUT5
12
17
OUT10
OUT6
13
16
OUT9
OUT7
14
15
OUT8
PowerPAD
Thermal Pad
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TERMINAL FUNCTIONS
TERMINAL
NAME
I/O
DESCRIPTION
2
I
Blank (all constant-current outputs off). When BLANK is high, all constant-current outputs (OUT0 through
OUT15) are forced off, the Grayscale PWM timing controller initializes and the Grayscale counter resets
to '0'. When BLANK is low, all constant-current outputs are controlled by the Grayscale PWM timing
controller.
GND
1
—
GSCLK
25
I
IREF
27
I/O
This pin sets the constant-current value. OUT0 through OUT15 sink constant-current is set to desired
value by connecting an external resistor between IREF and GND.
MODE
6
I
Input mode pin. When MODE is high, the input mode is dot correction (DC). When MODE is low, the
input mode is grayscale (GS).
NC
—
—
No connection
OUT0
7
O
Constant-current output
OUT1
8
O
Constant-current output
OUT2
9
O
Constant-current output
OUT3
10
O
Constant-current output
OUT4
11
O
Constant-current output
OUT5
12
O
Constant-current output
OUT6
13
O
Constant-current output
OUT7
14
O
Constant-current output
OUT8
15
O
Constant-current output
OUT9
16
O
Constant-current output
OUT10
17
O
Constant-current output
OUT11
18
O
Constant-current output
OUT12
19
O
Constant-current output
OUT13
20
O
Constant-current output
OUT14
21
O
Constant-current output
OUT15
22
O
Constant-current output
SCLK
4
I
Serial data shift clock
SIN
5
I
Serial data input
SOUT
24
O
Serial data output
VCC
28
I
Power-supply voltage
XERR
23
O
Error output. Open-drain output. XERR goes low when LOD or TEF is detected.
XHALF
26
I
Extended serial interface. When XHALF is high, the device operates normally. When XHALF is low, the
extended serial interface is activated.
XLAT
3
I
Edge triggered latch signal. At the rising edge of XLAT, the TLC59461 writes data from the input shift
register to either the Dot Correction register (MODE = high) or the Grayscale register (MODE = low).
BLANK
8
PWP
Ground
Reference clock for Grayscale PWM control.
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PARAMETER MEASUREMENT INFORMATION
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
VCC
INPUT
SOUT
GND
GND
Figure 1. SIN, SCLK, GSCLK, XLAT,
BLANK, MODE, XHALF
Figure 2. SOUT
VCC
XERR
IREF
GND
GND
Figure 3. IREF
Figure 4. XERR
OUTn
GND
Figure 5. OUT0 Through OUT15
TEST CIRCUITS
RL0
VCC
VCC
VCC
OUTn
IREF
(1)
RIREF
VLED
SOUT
VCC
CL0
GND
(1)
(1)
CL0 includes measurement probe and jig
capacitance.
Figure 6. Rise Time and Fall Time Test Circuit for OUTn
VCC
GND
VCC
IREF
VXERR
CL1
OUT0
RIREF
OUTn
¼
(1)
CL0 includes measurement probe and jig
capacitance.
Figure 7. Rise Time and Fall Time Test Circuit for SOUT
¼
XERR
(1)
VCC
RL1
VCC
CL0
GND
GND OUT15
VOUTn
VOUTFIX
(1)
CL1 includes measurement probe and jig
capacitance.
Figure 8. Rise Time and Fall Time Test Circuit for XERR
Figure 9. Constant-current Test Circuit for OUTn
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TIMING DIAGRAMS
TWH0, TWL0, TWH1, TWL1, TWH2, TWL2, TWH3
VCC
INPUT
(1)
50%
GND
TWH
TWL
TSU0, TSU1, TSU2, TSU3, TSU4, TSU5, TSU6, TSU7, TH0, TH1, TH2, TH3
VCC
CLOCK
INPUT
(1)
50%
GND
TSU
TH
VCC
DATA/CONTROL
INPUT
(1)
50%
GND
(1)
Input pulse rise and fall time is 1 ns to 3 ns. Input pulse high level is VCC and low level is GND.
Figure 10. Input Timing
tR0, tR1, tF0, tF1, tF2, tD0, tD1, tD2, tD3, tD4, tD5, tD6:
VCC
INPUT
(1)
50%
GND
tD
VOH or VOUTnH
90%
OUTPUT
50%
10%
VOL or VOUTnL
tR or tF
(1)
Input pulse rise and fall time is 1 ns to 3 ns.
Figure 11. Output Timing
10
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(DC Data Input Mode)
(GS Data Input Mode)
MODE
tH2
tWH2
tSU3
XLAT
(1st GS Data Input Cycle)
SIN
DC
MSB
DC
LSB
(2nd GS Data Input Cycle)
GS1
MSB
tH1
GS1
LSB
tSU2
GS2
MSB
tSU6
GS2
LSB
tSU1
GS3
MSB
tSU0
tWH0
tH0
SCLK
1
SOUT
96
¾
1
DC
MSB
¾
192
1
GS1
MSB
¾
tWL0
SID1
MSB
192
1
tD0
SID1
LSB
SID1
MSB-1
SID2
MSB
SID2
MSB-1
tWH3
(1st GS Data Output Cycle)
BLANK
(2nd GS Data Output Cycle)
tSU5
tSU4
tWH1
GSCLK
1
tD6
4096
tD2
tD1
1
tWL1
tD2
OUT0/4/8/12
(Voltage)
tD3
tD3
OUT1/5/9/13
(Voltage)
tD4
tD4
OUT2/6/10/14
(Voltage)
tD5
tD5
OUT3/7/11/15
(Voltage)
NOTE: DC = Dot Correction, GS = Grayscale.
Figure 12. Timing Diagram (GS Data = 003h, XHALF = High)
BLANK
tGSCLK
GSCLK
tOUTON
OUTn
(Voltage)
tON_ERR = tOUTON - tGSCLK
Figure 13. Output On-Time Error Timing Diagram (GS Data = 001h, GSCLK = 33 MHz)
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TYPICAL CHARACTERISTICS
At VCC = 3.3 V and TA = +25°C, unless otherwise noted.
REFERENCE RESISTOR vs
OUTPUT CURRENT
POWER DISSIPATION RATE
vs FREE-AIR TEMPERATURE
4000
Power Dissipation Rate (mW)
Reference Resistor (W)
100k
12750
10k
5100
3400
2550
2040
1700
2000
TLC59461PWP
PowerPAD Not Soldered
1000
0
30
20
10
3000
1275
1457
1k
0
TLC59461PWP
PowerPAD Soldered
50
40
-40
20
0
-20
80
60
40
Figure 14.
Figure 15.
OUTPUT CURRENT vs
OUTPUT VOLTAGE
OUTPUT CURRENT vs
OUTPUT VOLTAGE
45
45
IO = 40 mA
Output Current, IO (mA)
Output Current, IO (mA)
TA = +25°C
DCn = 3Fh
35
IO = 30 mA
30
25
IO = 20 mA
20
15
IO = 10 mA
10
43
42
41
TA = -40°C
40
39
38
TA = +25°C
37
5
36
IO = 5 mA
0
TA = +85°C
35
0
1.5
1.0
0.5
2.0
0
3.0
2.5
1.0
0.5
1.5
2.0
2.5
Output Voltage, VO (V)
Output Voltage, VO (V)
Figure 16.
Figure 17.
CONSTANT-CURRENT ERROR vs
AMBIENT TEMPERATURE
CONSTANT-CURRENT ERROR vs
OUTPUT CURRENT
4
3.0
4
IO = 40 mA
DCn = 3Fh
3
2
2
1
1
0
-1
-2
TA = +25°C
DCn = 3Fh
3
DIOLC (%)
DIOLC (%)
IO = 40 mA
DCn = 3Fh
44
40
0
-1
-2
VCC = 3.3 V
-3
VCC = 3.3 V
-3
VCC = 5.0 V
-4
VCC = 5.0 V
-4
-40
12
100
Free-Air Temperature (°C)
Output Current (mA)
-20
0
20
40
60
80
100
0
10
20
Ambient Temperature, TA (°C)
Output Current (mA)
Figure 18.
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 3.3 V and TA = +25°C, unless otherwise noted.
DOT CORRECTION LINEARITY
(ABS Value)
DOT CORRECTION LINEARITY
(ABS Value)
45
45
IOLCMax = 40 mA
TA = +25°C
40
40
30
25
IOLCMax = 20 mA
20
15
10
Output Current, IO (mA)
Output Current, IO (mA)
IOLCMax = 40 mA
35
IOLCMax = 5 mA
35
30
25
20
15
TA = -40°C
10
5
5
0
0
0
10
20
30
40
50
60
TA = +25°C
TA = +85°C
0
70
10
20
30
40
50
Dot Correction Data (dec)
Dot Correction Data (dec)
Figure 20.
Figure 21.
60
70
CONSTANT-CURRENT OUTPUT
VOLTAGE WAVEFORM
CH1 (2 V/div)
CH2 (2 V/div)
CH3 (2 V/div)
CH1-GSCLK
(33 MHz)
CH2-OUT0
(GSData = 001h)
IOLCMax = 40 mA, DCn = 3Fh
TA = +25°C,RL0 = 100 W
CL0 = 15 pF, VLED = 5 V
CH3-OUT15
(GSData = 001h)
Time (25 ns/div)
Figure 22.
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DETAILED DESCRIPTION
SETTING FOR THE MAXIMUM OUTPUT CURRENT VALUE
The maximum output current of each channel (IOLCMax) is set by a single external resistor (RIREF), placed between
the IREF pin and the GND pin. The voltage on IREF is generated with an internal bandgap, VIREF, which has a
typical value of 1.20 V. The RIREF resistor value is calculated by Equation 1:
RIREF (kW) = 42.5 ´
VIREF (V)
IOLCMax (mA)
(1)
Where:
•
•
VIREF = 1.20 V
RIREF = User-selected external resistor
IOLCMax is the largest current for all outputs. Each output sinks the IOLCMax current when it is turned on and its dot
correction is set to the maximum value of 3Fh (63d). The sink current for each output can be reduced by
lowering the respective output dot correction value.
RIREF must be between 1.275 kΩ (typ) and 12.75 kΩ (typ) in order to keep IOLCMax between 4 mA and 40 mA.
The output current may be unstable if IOLCMax is less than 4 mA. Output currents lower than 4 mA can be
achieved by setting IOLCMax to 4 mA or higher and then using dot correction.
Figure 14 illustrates the maximum output current versus RIREF. RIREF is the value of the resistor between the
IREF terminal to GND. A variable power supply may be connected to the IREF pin through a resistor to change
the maximum output current per output. The maximum output current is 42.5 times the current flowing out of the
IREF pin.
DOT CORRECTION (DC) FUNCTION
The TLC59461 is able to individually adjust the output current of each channel (OUT0 to OUT15). This function is
called dot correction (DC). The DC function allows the user to individually adjust the brightness and color
deviations of LEDs connected to the outputs OUT0 to OUT15. Each respective channel output current can be
adjusted in 64 steps from 0% to 100% of the maximum output current, IOLCMax. Dot correction data are entered
into the TLC59461 via the serial interface.
The output current is calculated by Equation 2:
IOUTn = IOLCMax ´
DCn
63
(2)
Where:
•
•
IOLCMax = the maximum output current of each output
DCn = the programmed dot correction value of output n (DCn = 0 to 63)
When MODE is high, the input shift register works as a DC shift register. The shift registers and data latches are
each 96 bits in length, and are used to individually adjust the constant-current values for each constant-current
driver. Each channel can be adjusted from 0% to 100% of the maximum LED current with 6-bit resolution.
Figure 23 illustrates the DC serial data configuration. Figure 12 illustrates the timing chart for writing data into the
shift registers and data latches. Each channel LED current is dot-corrected by the percentage corresponding to
the data in its DC data latch. DC data present on the SIN pin are clocked into the shift register with each rising
edge of the SCLK pin. Data are shifted in MSB first. The data are latched from the shift register into the DC data
latch with a rising edge on the XLAT pin.
The BLANK signal does not need to be high to latch in new data. When XLAT goes high, the new dot-correction
data immediately become valid and change the output currents if the output is on. When the IC is powered on,
the data in the shift register and DC data latch are not set to any default values. Therefore, DC data must be
written to the DC latch before turning on the constant-current output.
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LSB
MSB
95
90
89
6
5
0
DC 15.5
DC 15.0
DC 14.5
DC 1.0
DC 0.5
DC 0.0
DC OUT15
DC OUT14 to DC OUT1
DC OUT0
Figure 23. Dot Correction Serial Data Configuration
GRAYSCALE (GS) FUNCTION (PWM Operation)
Pulse width modulation (PWM) operation is controlled by a 12-bit grayscale counter that is clocked on each rising
edge of the grayscale reference clock (GSCLK). The counter is reset to zero when the BLANK signal is set high.
The counter value is held at zero while BLANK is high, even if the GSCLK input toggles high and low. After the
falling edge of BLANK, the counter increments with each rising edge of GSCLK. Any constant-current sink output
(OUT0 through OUT15) with a non-zero value in its corresponding grayscale latch starts to sink current after the
first rising edge of GSCLK following a high-to-low transition of BLANK. The internal counter keeps track of the
number of GSCLK pulses. Each output channel stays on as long as the internal counter is equal to or less than
the respective output GS data. Each channel turns off at the rising edge of GSCLK when the grayscale counter
value is larger than the grayscale latch value.
For example, an output that has a grayscale latch value of '1' turns on at the first rising edge of GSCLK after
BLANK goes low. It turns off at the second rising edge of GSCLK. Figure 24 shows the PWM output timing.
When the counter becomes FFFh, the counter stops and output does not turn on until the next grayscale cycle.
Pulling BLANK high before the counter becomes FFFh immediately resets the counter to zero.
BL ANK
2
1
3
4095
4096
GSCLK
OUTn
(GS Data = 0d)
OFF
tOUTON = tGSCLK ´ 1
OFF
OUTn
(GS Data = 1d)
ON
tOUTON = tGSCLK ´ 2
OUTn
(GS Data = 2d)
¼
tOUTON = tGSCLK ´ 4094
OUTn
(GS Data = 4094d)
tOUTON = tGSCLK ´ 4095
OUTn
(GS Data = 4095d)
Figure 24. PWM Output Timing
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When the IC powers on, the data in the shift register and latch are not set to any default value. Therefore, GS
data must be written to the GS latch before turning the constant-current output on. Additionally, BLANK should
be high when the device is powered on, to prevent the outputs from turning on before the proper grayscale and
dot correction values are written. All constant-current outputs are always off when BLANK is high.
Each output (OUTn) on-time (tOUTON) is calculated by Equation 3:
tOUTON (ns) = tGSCLK (ns) ´ GSn
(3)
Where:
•
•
tGSCLK = the period of GSCLK
GSn = the programmed grayscale value of output n (GSn = 0 to 4095d)
If XLAT goes high during a grayscale cycle, then new GS data are immediately latched into the GS latch. This
action can cause the outputs to turn on or off unexpectedly. For proper operation, GS data should only be
latched into the IC at the end of a GS period when BLANK is high.
When MODE is low, the input shift register works as a GS shift register. The shift registers and data latches are
each 192 bits in length, and are used to set the PWM timing for each constant-current driver. Figure 25 shows
the GS serial data configuration. Refer to Figure 12 for a timing diagram for writing data into the shift register and
latch. The driver on-time is set by the data in the GS data latch. GS data present on the SIN pin are clocked into
the shift register with each rising edge of the SCLK pin. Data are shifted in MSB first. Data are latched from the
shift register into the GS data latch with a rising edge on the XLAT pin.
If there are any unconnected output LED lamps (including connection failures or short-circuits), the grayscale
data corresponding to the unconnected output should be set to '0' before turning on the LEDs. Otherwise, the
VCC supply current (IVCC) increases while the constant-current outputs are on.
MSB
LSB
191
180
179
12
11
0
GS 15.11
GS 15.0
GS 14.11
GS 1.0
GS 0.11
GS 0.0
GS OUT15
GS OUT14 to GS OUT1
GS OUT0
Figure 25. Grayscale Serial Data Configuration
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STATUS INFORMATION DATA (SID)
Status information data (SID) are 17-bit, read-only data, accessible in the grayscale data input mode (MODE =
GND). Both the LED open detection (LOD) error and the thermal error flag (TEF) are shifted out of the SOUT pin
with each rising edge of SCLK. The 16 LOD bits for each channel and the TEF bit are written into the 17 most
significant bits (MSBs) of the shift register at the rising edge of the first SCLK after XLAT goes high. As a result,
the previous data in the 17 MSBs are lost at the same time. Figure 26 shows the bit assignments, Table 1
describes the SID data definition, and Figure 27 illustrates the read timing for the status information data.
LSB
MSB
191
176
175
174
0
LOD 15
LOD 0
TEF
X
X
LOD Data
Reserved
TEF
Figure 26. Status Information Data Configuration (XHALF = High)
Table 1. SID Data Definition
DEFINITION
SID DATA
LODn
TEF
0
No LED open error
No thermal error
1
LED is open or shorted to GND
Over temperature
Low Level
MODE
High Level
XHALF
XLAT
SIN
GS0
1
GS0
0
191
192
GS15 GS15 GS15
10A
9A
11A
1
2
3
GS14 GS14 GS14 GS14 GS14
6A
5A
9A
8A
7A
15
16
17
18
19
GS0
2A
GS0
1A
GS0
0A
190
191
192
SCLK
SOUT
Not
Valid
GS15
11
LOD
15
LOD
14
LOD
13
LOD
1
LOD
0
TEF
Not
Valid
Not
Valid
Not
Valid
Not
Valid
GS15
11A
Figure 27. Status Information Data Read Timing (XHALF = High)
The LOD data are updated at the rising edge of the 33rd GSCLK pulse after BLANK goes low; the LOD data are
retained until the next 33rd GSCLK. LOD data are only checked for outputs that are turned on during the rising
edge of the 33rd GSCLK pulse. A '1' in a LOD bit indicates an open LED condition for the corresponding
channel. A '0' indicates normal operation. The GS data should be equal to or higher than 21h (33d) to detect an
open LED in every PWM cycle. When the IC is powered on, LOD data do not show correct values. Therefore,
LOD data must be read at the rising edge of the 33rd GSCLK pulse after BLANK goes low.
The TEF bit indicates that the IC temperature is too high. A '1' in the TEF bit means that the IC temperature
exceeds the detect temperature threshold, TTEF. A '0' in the TEF bit indicates normal operating temperature
conditions.
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ERROR INFORMATION OUTPUT
The TLC59461 has two error detection circuits: LED open detection (LOD) and a thermal error flag (TEF). LOD
detects a broken or disconnected LED during the display period. The TEF indicates an over-temperature
condition. A low-level output of XERR indicates that an LOD error or TEF is detected. XERR pins of more than
two ICs can be connected together and pulled up to VCC with a single resistor because XERR is an open-drain
output; see the SCLK and GSCLK Frequency section. Table 2 shows the XERR truth table. BLANK = H masks
LOD to distinguish between LOD and TEF. When the IC is powered on, XERR does not show correct values.
XERR shows a correct signal when LOD data become valid at the rising edge of the 33rd GSCLK pulse after
BLANK goes low. Also, both the LOD error and the TEF are shifted out of the SOUT pin; see the Status
Information Data (SID) section.
Table 2. XERR Truth Table
CONDITION
ERROR DATA
INPUT
LOD (Internal)
TEF (Internal)
BLANK
0
0
XERR
0
1
1
0
1
1
L
0
0
H
0
1
1
0
1
1
H
L
H
L
L
L
H
L
CONTINUOUS BASE LED OPEN DETECTION (LOD)
The LOD function automatically updates LOD data at the rising edge of the 33rd GSCLK pulse after BLANK goes
low; the LOD data are retained until the next 33rd GSCLK. LOD data are only checked for outputs that are
turned on during the rising edge of the 33rd GSCLK pulse. The internal LOD data becomes '1' when the voltage
of the OUTn pin is less than the LED open detection threshold (VLOD = 0.3 V, typical).
To eliminate false detection of open LEDs, the LED driver design must ensure that the TLC59461 output voltage
is greater than VLOD when the outputs are on. The GS data should be greater than or equal to 21h (33d) to
detect LED open in every PWM cycle.
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AUTO OUTPUT OFF
The TLC59461 does not implement the Auto Output Off functionality that is available in the TLC5946. This
revised architecture allows the voltage at the OUTn pins of the IC to be reduced to a voltage lower than the LED
open detection threshold VLOD (0.3V typical) specified in the TLC5946 data sheet and continue to have OUTn
remain turned on. Reducing the voltage at OUTn minimizes the power dissipation in the IC.
THERMAL ERROR FLAG (TEF)
The TLC59461 has a thermal error flag (TEF) function to indicate an over-temperature condition. If the junction
temperature exceeds the threshold temperature, +162°C typical, TEF toggles to '1' and the XERR pin goes to a
low level. Once TEF becomes '1', it remains a '1' until the first falling edge of SCLK after XLAT goes high, as
shown in Figure 28. If the junction temperature (TJ) remains higher than the threshold temperature, TEF remains
'1', even after the first falling edge of SCLK. TEF is also shifted out of the SOUT pin; see the Status Information
Data (SID) section.
XLAT
BLANK
SCLK
1
2
3
4
1
2
3
GSCLK
IC Junction
Temperature (TJ)
TJ < TTEF
TJ ³ TTEF
TJ < TTEF - THYS
TJ ³ TTEF
'1'
TEF
(Internal)
'0'
'0'
Hi-Z
XERR
Low
Figure 28. TEF and XERR Timing
NOISE REDUCTION
Large surge currents can flow through the IC and the board if all 16 LED channels fully turn on simultaneously at
the start of each grayscale cycle. These large current surges could introduce detrimental noise and
electromagnetic interference (EMI) into other circuits. The TLC59461 turns on the LED channels in a series
delay, to provide a current soft-start feature. The output current sinks are grouped into four groups of four
channels each. The first group is OUT0, 4, 8, 12; the second group is OUT1, 5, 9, 13; the third group is OUT2, 6,
10, 14; and the fourth group is OUT3, 7, 11, 15. Each group turns on sequentially with a small delay between
groups; see Figure 12. Both turn-on and turn-off are delayed.
OUTPUT ENABLE
When BLANK is high, all constant-current outputs turn off and the grayscale counter is reset. When BLANK is
low, all constant-current outputs are controlled by the GS PWM timing controller. If BLANK goes low and then
toggles high again in a very short time, all outputs that are programmed to turn on do so, for either the
programmed number of grayscale clocks or the length of time that the BLANK signal was low, whichever is
lower. For example, if all outputs are programmed to turn on for 1 ms, but the BLANK signal is only low for 50 ns,
all outputs turn on for 50 ns, even though some outputs will turn on after the BLANK signal has already gone
high.
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SERIAL INTERFACE
The TLC59461 has a flexible serial interface that can be connected to microcontrollers or digital signal
processors in various ways. Only three pins are needed to input data into the device. More than two TLC59461s
can be connected in series by connecting an SOUT pin from one device to the SIN pin of the next device.
Cascaded two TLC59461s are shown in Figure 29 and Figure 30. The SOUT pin can also be connected to the
controller to receive status information from the TLC59461; see the SCLK and GSCLK Frequency section.
TLC59461 (a)
SIN(a)
SIN
SOUT
TLC59461 (b)
SOUT(b)
SOUT
SIN
SCLK, XLAT,
BLANK, GSCLK,
MODE
Figure 29. Cascading Two TLC59461 Devices
MODE
XLAT
SIN(a)
DCb
MSB
DCa
LSB
GSb1
MSB
GSa1
LSB
GSb2
MSB
GSa2
LSB
GSb3
MSB
SCLK
192
1
SOUT(b)
¾
384
1
DCb
MSB
¾
¾
384
1
GSb1
MSB
SIDb1 SIDb1
MSB MSB-1
1
SIDa1
LSB
SIDb2 SIDb2
MSB MSB-1
BLANK
1
1
GSCLK
4096
OFF
OUT0/4/8/12
(Voltage)
ON
OUT1/5/9/13
(Voltage)
OUT2/6/10/14
(Voltage)
OUT3/7/11/15
(Voltage)
Figure 30. Timing Diagram of Two Cascaded TLC59461 Devices (XHALF = High)
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SERIAL INTERFACE MODE
The serial interface has two input modes defined by the MODE pin, as Table 3 shows. XLAT must be low when
the MODE pin goes high-to-low or low-to-high to change back and forth between GS mode and DC mode.
Table 3. Serial Interface Input Mode
MODE
INPUT MODE
INPUT SHIFT REGISTER
GND
Grayscale PWM data
192 bits
VCC
Dot correction data
96 bits
SCLK AND GSCLK FREQUENCY
Figure 31 shows a cascading connection of n TLC59461 devices connected to a single controller, building a
basic module of an LED display system. There is no limitation to the maximum number of ICs that can be
cascaded. However, the maximum number of cascading TLC59461 devices depends on the application system
and is in the range of 40 devices. Equation 4 and Equation 5 show the minimum frequencies for GSCLK and
SCLK.
fGSCLK = 4096 ´ fUPDATE
(4)
fSCLK = 192 ´ fUPDATE ´ n
(5)
where:
•
•
•
•
fGSCLK = minimum frequency of GSCLK
fSCLK = minimum frequency of SCLK
fUPDATE = update rate of entire cascading system
n = number of cascaded TLC59461 devices
VLED
VLED
VLED
VLED
VCC
¼
OUT0
OUT
XERR
SCLK
XLAT
Controller
¼
SIN
¼
SOUT
GSCLK
¼
XERR
SCLK
SCLK
XLAT
VCC
MODE
OUT15
SOUT
SIN
XERR
TLC59461
IC1
MODE
BLANK
OUT0
OUT15
XLAT
MODE
¼
TLC59461
ICn
VCC
BLANK
VCC
BLANK
VCC
GSCLK
XHALF
GSCLK
XHALF
IN
GND
IREF
RIREF
IREF
GND
RIREF
6
Figure 31. Cascading Device Connections
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POWER DISSIPATION CALCULATION
The device power dissipation must be below the power dissipation rate of the device package to ensure correct
operation. Equation 6 calculates the power dissipation of the device:
PD = (VCC ´ ICC) + VOUT ´ IOLCMax ´ N ´
DCn
´ dPWM
63d
(6)
Where:
•
•
•
•
•
•
•
•
PD = device power dissipation
VCC = device supply voltage
ICC = device supply current
VOUT = OUTn voltage when driving LED current
IOLCMax = LED current adjusted by RIREF resistor
DCn = maximum DC value for OUTn
N = number of OUTn driving LED at the same time
dPWM = duty cycle defined by BLANK pin or GS PWM value
EXTENDED SERIAL INTERFACE
The TLC59461 has an extended serial interface with the following functions:
1. Independently accessible GS shift register of OUT0 to OUT7 or OUT8 to OUT15
2. SOUT half clock delay
When XHALF is low, the extended serial interface becomes active. Either the OUT0 to OUT7 GS shift register or
the OUT8 to OUT15 GS shift register is selected in advance by counting the XLAT pulses while BLANK is high
(one XLAT pulse selects the OUT0 to OUT7 GS shift register and two XLAT pulses select the OUT8 to OUT15
GS shift register), as shown in Figure 32. One or two XLAT pulses while BLANK is high must be input before
sending the serial data.
SOUT outputs serial data at the falling edge of SCLK, delaying half a clock longer than the normal serial
interface mode. SIN reads data at the rising edge of SCLK at the same as the normal serial interface mode. This
configuration ensures a longer distance serial interface. Figure 33 shows the output timing of the extended serial
interface mode.
SOUT outputs the status information data only when the data of OUT8 to OUT15 are shifted in, as shown in
Figure 34 and Figure 35. The status information data configuration when XHALF is low is shown in Figure 36.
Figure 37 shows the recommended ac timing widths of the extended serial interface. Note that tWL2, tSU7, and tH3
are only effective when XHALF is low.
Figure 38 and Figure 39 show power-on sequence examples of this mode. BLANK should be high when the
device is powered on to prevent the outputs from turning on before the proper GS and DC values are written.
The extended serial interface mode is available only in the GS PWM mode (MODE = low). When MODE is high
in the extended serial interface mode (XHALF = low), the TLC59461 becomes the DC mode that is the same as
the normal DC mode.
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Low Level
XHALF
BLANK
XLAT
SCLK
OUT0 to OUT7 PWM Data
OUT8 to OUT15 PWM Data
SIN
Not
Valid
SOUT
Not
Valid
Not
Valid
Not
Valid
Not
Valid
LOD
15
LOD
14
SCLK Rising Edge: Read Data
SCLK Falling Edge: Output Data
Figure 32. Extended Serial Interface
Low Level
XHALF
BLANK
XLAT
SCLK
¼
¼
¼
¼
OUT8 to OUT15 N
OUT0 to OUT7 N+1
OUT8 to OUT15 N+1
PWM Data
SIN
GSCLK
OUT0 to OUT7 N
¼
¼
¼
¼
PWM Output
IOUT0 to IOUT7
OUT0 to OUT7 N-1
OUT0 to OUT7 N
OUT0 to OUT7 N
OUT0 to OUT7 N+1
IOUT8 to IOUT15
OUT8 to OUT15 N-1
OUT8 to OUT15 N-1
OUT8 to OUT15 N
OUT8 to OUT15 N
Figure 33. Output Timing of Extended Serial Interface
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Product Folder Link(s): TLC59461
23
TLC59461
SLVS896A – NOVEMBER 2008 – REVISED MARCH 2009............................................................................................................................................... www.ti.com
Low Level
MODE
Low Level
XHALF
BLANK
XLAT
SIN
GS8
1
GS8
0
GS7
11
GS7
10
GS7
9
GS0
2
GS0
1
GS0
0
95
96
1
2
3
94
95
96
No t
Valid
N ot
Valid
No t
Valid
No t
Valid
SCLK
Not GS15
Valid
11
SOUT
No t
Valid
GS7
11
Figure 34. Extended Serial Interface (OUT0 to OUT7)
Low Level
MODE
Low Level
XHALF
BLANK
XLAT
SIN
GS0
1
GS0
0
95
96
GS15 GS15 GS15
10
9
11
1
2
3
LOD
15
LOD
14
GS14 GS14 GS14 GS14 GS14
6
5
9
8
7
15
16
17
18
LOD
1
LOD
0
TEF
GS8
2
GS8
1
GS8
0
94
95
96
19
SCLK
SOUT
Not
Valid
GS7
11
LOD
13
Not
Valid
Not Not
Valid Valid
Not GS15
Valid
11
Figure 35. Extended Serial Interface (OUT8 to OUT15)
MSB
LSB
95
80
79
78
0
LOD 15
LOD 0
TEF
X
X
LOD Data
TEF
Reserved
Figure 36. Status Information Data Configuration (XHALF = Low)
24
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Product Folder Link(s): TLC59461
TLC59461
www.ti.com............................................................................................................................................... SLVS896A – NOVEMBER 2008 – REVISED MARCH 2009
BLANK
tH3
tSU7
tSU7
tH3
tWL2
XLAT
tSU1
tSU6
tSU6
tSU1
SCLK
Figure 37. AC Timing in Extended Serial Interface Mode (XHALF = Low)
VCC
MODE
XLAT
SIN
SCLK
SOUT
BLANK
GSCLK
IOUTn
XERR
Figure 38. Power-On Sequence—1 (XHALF = Low)
(BLANK goes high immediately after power-on)
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TLC59461
SLVS896A – NOVEMBER 2008 – REVISED MARCH 2009............................................................................................................................................... www.ti.com
VCC
MODE
XLAT
SIN
SCLK
SOUT
BLANK
GSCLK
IOUTn
XERR
Figure 39. Power-On Sequence—2 (XHALF = Low)
(BLANK stays high after power-on, GS mode starts with BLANK = High)
26
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TLC59461PWP
ACTIVE
HTSSOP
PWP
28
TLC59461PWPR
ACTIVE
HTSSOP
PWP
28
50
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-May-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TLC59461PWPR
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
28
Reel
Reel
Diameter Width
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
7.1
10.4
1.6
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-May-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLC59461PWPR
HTSSOP
PWP
28
2000
346.0
346.0
33.0
Pack Materials-Page 2
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