STMICROELECTRONICS STB4N62K3

STB4N62K3,
STD4N62K3
N-channel 620 V, 1.7 Ω, 3.8 A SuperMESH3™ Power MOSFET
in D2PAK and DPAK packages
Datasheet — production data
Features
Order codes
VDSS
RDS(on) max
ID
Pw
STB4N62K3
STD4N62K3
620 V
<2Ω
3.8 A
70 W
TAB
TAB
3
■
100% avalanche tested
■
Extremely high dv/dt capability
■
Gate charge minimized
■
Very low intrinsic capacitance
■
Improved diode reverse recovery
characteristics
■
Zener-protected
1
DPAK
Figure 1.
D²PAK
Internal schematic diagram
Application
■
3
1
D(2,TAB)
Switching applications
Description
G(1)
These devices are made using the
SuperMESH3™ Power MOSFET technology that
is obtained via improvements applied to
STMicroelectronics’ SuperMESH™ technology
combined with a new optimized vertical structure.
The resulting product has an extremely low on
resistance, superior dynamic performance and
high avalanche capability, making it especially
suitable for the most demanding applications.
Table 1.
S(3)
AM01476v1
Device summary
Order codes
Marking
Package
Packaging
STB4N62K3
STD4N62K3
4N62K3
D²PAK
DPAK
Tape and reel
April 2012
This is information on a product in full production.
Doc ID 18337 Rev 2
1/18
www.st.com
18
Contents
STB4N62K3, STD4N62K3
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................ 6
3
Test circuits
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/18
.............................................. 9
Doc ID 18337 Rev 2
STB4N62K3, STD4N62K3
1
Electrical ratings
Electrical ratings
Table 2.
Absolute maximum ratings
Value
Symbol
Parameter
Unit
D²PAK
DPAK
VDS
Drain-source voltage
620
V
VGS
Gate- source voltage
± 30
V
ID
Drain current (continuous) at TC = 25 °C
3.8
A
ID
Drain current (continuous) at TC = 100 °C
2
A
15.2
A
Total dissipation at TC = 25 °C
70
W
IAR
Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max)
3.8
A
EAS
Single pulse avalanche energy
(starting Tj = 25°C, ID = IAR, VDD = 50V)
115
mJ
VESD(G-S)
Gate source ESD(HBM-C = 100 pF,
R = 1.5 kΩ)
2500
V
dv/dt (2)
Peak diode recovery voltage slope
12
V/ns
IDM
(1)
PTOT
Drain current (pulsed)
VISO
Insulation withstand voltage (RMS) from
all three leads to external heat sink
(t = 1 s; TC = 25 °C)
Tstg
Storage temperature
V
Max. operating junction temperature
Tj
- 55 to 150
°C
150
°C
1. Pulse width limited by safe operating area.
2. ISD ≤ 3.8 A, di/dt = 400 A/µs, VDD = 80% V(BR)DSS, VDS peak ≤ V(BR)DSS.
Table 3.
Thermal data
Value
Symbol
Parameter
Unit
DPAK
Rthj-case
Rthj-pcb
(1)
Thermal resistance junction-case max
1.79
Thermal resistance junction-pcb max
50
D²PAK
°C/W
30
°C/W
1. When mounted on 1inch² FR-4 board, 2 oz Cu.
Doc ID 18337 Rev 2
3/18
Electrical characteristics
2
STB4N62K3, STD4N62K3
Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 4.
Symbol
On /off states
Parameter
V(BR)DSS
Drain-source
breakdown voltage
IDSS
Zero gate voltage
drain current
IGSS
Gate-body leakage
current
Test conditions
VGS = 0, ID = 1 mA
Max.
Unit
620
V
1
µA
VGS = 0
VDS = 620V, TC=125 °C
50
µA
VDS = 0, VGS = ± 20 V
± 10
µA
3.75
4.5
V
1.7
2
Ω
Min.
Typ.
Max.
Unit
Gate threshold voltage VDS = VGS, ID = 50 µA
RDS(on
Static drain-source onVGS = 10 V, ID = 1.9 A
resistance
Symbol
Typ.
VGS = 0, VDS = 620V
VGS(th)
Table 5.
Min.
3
Dynamic
Parameter
Test conditions
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS = 50 V, f = 1 MHz,
VGS = 0
-
550
42
7
-
pF
pF
pF
Equivalent output
capacitance
VDS = 0 to 496 V, VGS = 0
-
27
-
pF
RG
Intrinsic gate
resistance
f = 1 MHz open drain
2
5
10
Ω
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD = 496 V, ID = 3.8 A,
VGS = 10 V
(see Figure 18)
-
22
4
13
-
nC
nC
nC
Ciss
Coss
Crss
Coss eq.(1)
1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS
Table 6.
Symbol
td(on)
tr
td(off)
tf
4/18
Switching times
Parameter
Turn-on delay time
Rise time
Turn-off-delay time
Fall time
Test conditions
VDD = 300 V, ID = 1.9 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 17)
Doc ID 18337 Rev 2
Min.
Typ.
-
10
9
29
19
Max.
Unit
-
ns
ns
ns
ns
STB4N62K3, STD4N62K3
Table 7.
Electrical characteristics
Source drain diode
Symbol
Parameter
ISD
ISDM (1)
Source-drain current
Source-drain current (pulsed)
VSD (2)
Forward on voltage
trr
Qrr
IRRM
trr
Qrr
IRRM
Test conditions
Min.
Typ.
Max. Unit
-
3.8
15.2
A
A
ISD = 3.8 A, VGS = 0
-
1.6
V
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 3.8 A, di/dt = 100 A/µs
VDD = 60 V (see Figure 22)
-
220
1.4
13
ns
µC
A
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 3.8 A, di/dt = 100 A/µs
VDD = 60 V, Tj = 150 °C
(see Figure 22)
-
270
1.9
14
ns
µC
A
Min.
Typ.
1. Pulse width limited by safe operating area.
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
Table 8.
Symbol
BVGSO
Gate-source Zener diode
Parameter
Test conditions
Gate-source breakdown
voltage
Igs=± 1 mA (open drain)
30
Max. Unit
-
V
The built-in back-to-back Zener diodes have specifically been designed to enhance not only
the device’s ESD capability, but also to make them safely absorb possible voltage transients
that may occasionally be applied from gate to source. In this respect the Zener voltage is
appropriate to achieve an efficient and cost-effective intervention to protect the device’s
integrity. These integrated Zener diodes thus avoid the usage of external components.
Doc ID 18337 Rev 2
5/18
Electrical characteristics
STB4N62K3, STD4N62K3
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area for D²PAK
Figure 3.
Thermal impedance for D²PAK
Figure 5.
Thermal impedance for DPAK
Figure 7.
Transfer characteristics
AM07172v1
ID
(A)
10
is
10µs
D
S(
on
)
O
Li per
m at
ite io
d ni
by n
m this
ax a
R rea
100µs
1
1ms
10ms
0.1
Tj=150°C
Tc=25°C
Single pulse
0.01
0.1
10
1
Figure 4.
100
VDS(V)
Safe operating area for DPAK
10
10µs
n)
100µs
D
S(
o
O
Li per
m at
ite io
d ni
by n
m this
ax a
R rea
is
ID
(A)
AM07173v1
1
1ms
10ms
Tj=150°C
Tc=25°C
0.1
Single pulse
0.01
0.1
Figure 6.
10
1
100
VDS(V)
Output characteristics
AM07175v1
ID (A)
8
VGS=10V
7V
7
AM07176v1
ID
(A)
VDS=15V
6
5
6
4
5
4
6V
3
3
2
2
1
1
5V
0
0
6/18
5
10
15
20
25
VDS(V)
Doc ID 18337 Rev 2
0
0
2
4
6
8
VGS(V)
STB4N62K3, STD4N62K3
Figure 8.
Electrical characteristics
Gate charge vs gate-source voltage Figure 9.
AM07177v1
VGS
(V) VDS
12
VGS
VDD=496V
ID=3.8A
Static drain-source on resistance
AM07178v1
RDS(on)
(Ω)
VGS=10V
500
10
1.9
400
1.8
8
300
6
1.7
200
4
100
2
0
0
10
5
0
25 Qg(nC)
20
15
Figure 10. Capacitance variations
1.5
0
2
1
3
ID(A)
Figure 11. Output capacitance stored energy
AM07179v1
C
(pF)
1.6
AM07180v1
Eoss
(µJ)
3.0
1000
Ciss
2.5
2.0
100
1.5
Coss
10
1.0
Crss
0.5
1
0.1
1
100
10
Figure 12. Normalized gate threshold voltage
vs temperature
AM07181v1
VGS(th)
0
0
VDS(V)
(norm)
1.10
100
200 300
400 500 600
VDS(V)
Figure 13. Normalized on-resistance vs
temperature
AM07182v1
RDS(on)
(norm)
2.5
2.0
1.00
1.5
0.90
1.0
0.80
0.70
-75
0.5
-25
25
75
125
TJ(°C)
Doc ID 18337 Rev 2
-75
-25
25
75
125
TJ(°C)
7/18
Electrical characteristics
STB4N62K3, STD4N62K3
Figure 14. Maximum avalanche energy vs
starting Tj
EAS
(mJ)
120
110
100
90
80
70
60
50
40
30
20
10
0
0
AM07184v1
ID=3.8 A
VDD=50 V
Figure 15. Normalized BVDSS vs temperature
1.10
1.05
1.00
0.95
20
40
60
80
100 120 140 TJ(°C)
0.90
-75
Figure 16. Source-drain diode forward
characteristics
VSD (V)
1.0
AM08888v1
TJ=150°C
TJ=25°C
0.9
0.8
0.7
TJ=-50°C
0.6
0.5
0.4
0.3
0.2
0.1
0
8/18
AM07183v1
BVDSS
(norm)
1
2
3
4
5
ISD(A)
Doc ID 18337 Rev 2
-25
25
75
125
TJ(°C)
STB4N62K3, STD4N62K3
3
Test circuits
Test circuits
Figure 17. Switching times test circuit for
resistive load
Figure 18. Gate charge test circuit
VDD
12V
47kΩ
1kΩ
100nF
3.3
μF
2200
RL
μF
VGS
IG=CONST
VDD
100Ω
Vi=20V=VGMAX
VD
RG
2200
μF
D.U.T.
D.U.T.
VG
2.7kΩ
PW
47kΩ
1kΩ
PW
AM01468v1
AM01469v1
Figure 19. Test circuit for inductive load
Figure 20. Unclamped Inductive load test
switching and diode recovery times
circuit
A
A
D.U.T.
FAST
DIODE
B
B
L
A
D
G
VD
L=100μH
S
3.3
μF
B
25 Ω
1000
μF
D
VDD
2200
μF
3.3
μF
VDD
ID
G
RG
S
Vi
D.U.T.
Pw
AM01470v1
Figure 21. Unclamped inductive waveform
AM01471v1
Figure 22. Switching time waveform
ton
V(BR)DSS
tdon
VD
toff
tr
tdoff
tf
90%
90%
IDM
10%
ID
VDD
10%
0
VDD
VDS
90%
VGS
AM01472v1
0
Doc ID 18337 Rev 2
10%
AM01473v1
9/18
Package mechanical data
4
STB4N62K3, STD4N62K3
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
Table 9.
DPAK (TO-252) mechanical data
mm
Dim.
Min.
Typ.
A
2.20
2.40
A1
0.90
1.10
A2
0.03
0.23
b
0.64
0.90
b4
5.20
5.40
c
0.45
0.60
c2
0.48
0.60
D
6.00
6.20
D1
E
5.10
6.40
6.60
E1
4.70
e
2.28
e1
4.40
4.60
H
9.35
10.10
L
1
1.50
L1
2.80
L2
0.80
L4
0.60
1
R
V2
10/18
Max.
0.20
0°
8°
Doc ID 18337 Rev 2
STB4N62K3, STD4N62K3
Package mechanical data
Figure 23. DPAK (TO-252) drawing
0068772_I
Figure 24. DPAK footprint(a)
6.7
1.8
3
1.6
2.3
6.7
2.3
1.6
AM08850v1
a. All dimension are in millimeters
Doc ID 18337 Rev 2
11/18
Package mechanical data
Table 10.
STB4N62K3, STD4N62K3
D²PAK (TO-263) mechanical data
mm
Dim.
Min.
Typ.
A
4.40
4.60
A1
0.03
0.23
b
0.70
0.93
b2
1.14
1.70
c
0.45
0.60
c2
1.23
1.36
D
8.95
9.35
D1
7.50
E
10
E1
8.50
10.40
e
2.54
e1
4.88
5.28
H
15
15.85
J1
2.49
2.69
L
2.29
2.79
L1
1.27
1.40
L2
1.30
1.75
R
V2
12/18
Max.
0.4
0°
8°
Doc ID 18337 Rev 2
STB4N62K3, STD4N62K3
Package mechanical data
Figure 25. D²PAK (TO-263) drawing
0079457_T
Figure 26. D²PAK footprint(b)
16.90
12.20
5.08
1.60
3.50
9.75
Footprint
b. All dimension are in millimeters
Doc ID 18337 Rev 2
13/18
Packaging mechanical data
5
STB4N62K3, STD4N62K3
Packaging mechanical data
Table 11.
DPAK (TO-252) tape and reel mechanical data
Tape
Reel
mm
mm
Dim.
Dim.
Min.
Max.
A0
6.8
7
A
B0
10.4
10.6
B
1.5
12.1
C
12.8
1.6
D
20.2
G
16.4
50
B1
Min.
330
13.2
D
1.5
D1
1.5
E
1.65
1.85
N
F
7.4
7.6
T
K0
2.55
2.75
P0
3.9
4.1
Base qty.
2500
P1
7.9
8.1
Bulk qty.
2500
P2
1.9
2.1
R
40
T
0.25
0.35
W
15.7
16.3
Table 12.
18.4
22.4
D²PAK (TO-263) tape and reel mechanical data
Tape
Reel
mm
mm
Dim.
14/18
Max.
Dim.
Min.
Max.
A0
10.5
10.7
A
B0
15.7
15.9
B
1.5
D
1.5
1.6
C
12.8
D1
1.59
1.61
D
20.2
E
1.65
1.85
G
24.4
F
11.4
11.6
N
100
K0
4.8
5.0
T
P0
3.9
4.1
P1
11.9
12.1
Base qty
1000
P2
1.9
2.1
Bulk qty
1000
Doc ID 18337 Rev 2
Min.
Max.
330
13.2
26.4
30.4
STB4N62K3, STD4N62K3
Table 12.
Packaging mechanical data
D²PAK (TO-263) tape and reel mechanical data (continued)
Tape
Reel
mm
mm
Dim.
Dim.
Min.
Max.
R
50
T
0.25
0.35
W
23.7
24.3
Min.
Max.
Figure 27. Tape for DPAK (TO-252) and D²PAK (TO-263)
10 pitches cumulative
tolerance on tape +/- 0.2 mm
T
P0
Top cover
tape
P2
D
E
F
K0
W
B0
A0
P1
D1
User direction of feed
R
Bending radius
User direction of feed
AM08852v2
Doc ID 18337 Rev 2
15/18
Packaging mechanical data
STB4N62K3, STD4N62K3
Figure 28. Reel for DPAK (TO-252) and D²PAK (TO-263)
T
REEL DIMENSIONS
40mm min.
Access hole
At sl ot location
B
D
C
N
A
Full radius
Tape slot
in core for
tape start 25 mm min.
width
G measured at hub
AM08851v2
16/18
Doc ID 18337 Rev 2
STB4N62K3, STD4N62K3
6
Revision history
Revision history
Table 13.
Document revision history
Date
Revision
16-Dec-2010
1
First release.
2
Added min and max values for RG in Table 5: Dynamic and
Section 5: Packaging mechanical data.
Updated Section 4: Package mechanical data.
Minor text changes.
26-Apr-2012
Changes
Doc ID 18337 Rev 2
17/18
STB4N62K3, STD4N62K3
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Doc ID 18337 Rev 2