CHlNA P0VVER sUPPLY sURVEY Ⅶ PER28低 待机功率开关 电源转换器 原理 与应用 作者 :高 思恩 (山 东沂光电子股份有限公司 ) PwM控 制 器和 SrlOv高 压功 率MOSFET于 同 1w,适 用于机顶盒 、DVD播 放机 、录音机 i费 类与 家用设备 的辅助 电源和 LED照 明 电 作 ;频 率抖 动 ;突 发模 式 其它功能和 电路主 要有两 电平过 电流保护 、过 电压和 -、 概 述 意法半导体 (ST)公 司推 出的离线 过载保护 、滞后热保护 、软启动和故障解除之后的 自 (off line) —— 高 压 变 换 器 系 列 IC又 增 加 了 一 个 新 的 成 员 VIPER28。 这 种 新 型 器 件 是 一 种 将 800V功 率 MOSFET 动重新启动 。突发 (burst)模 式操作和非常低 的功率 和高性能低压 PWM控 制器 组合在一起 的IC。 Ⅵ PEV8 可以降低 电磁干扰 消耗满足待机 (stalldby)节 能规范 。先进 的频率抖动 s R BVRsT-M0DE REFERENCEs 图1 VIPER28芯 片 电路 Q (EMI)滤 波器 的成本 。高压启动 CHlNA P0WER sUPPLY sURVEY 技术研 究与应 用 表1 引脚 名称 功能 丐 1 GND IC控 制 电路地 ,同 时也是功率 M0sFET源 极 2 VDD 控 制 电路 电源 电压 ,该 引脚在启 动期 间为外部 电容器提 供 充 电电流 3 CONT 4 FB 5 EPT 控 制 引脚 ,可 以选择 下面的功能 1.电 流 限制设定点调 节 。连接该 引脚 到地 的 一个 电阻 ,逐 周 电流 限制的设置 缺省 (默 认 )置 减 少 2输 出电压监视 。该 引脚上 的 一个超 过 3V的 电压将关 闭 IC减 少器件消耗 : 占空 因数控 制输入 。 内部 电流产 生器为环路调节提 供偏 置 电流 ;一 个低 于0,6V的 电压激活 突发操作 一 个接近 33V的 电平意味着 lC接 近逐周过 电流设定点 该引脚允许 为 附加 电源管理连接一个外部 电容 。如果该功能不用 ,这 个 引脚必须接地 MOsFET高 压漏极端 ,内 部开关启 动偏 置 电流也从该 引脚汲取 7,8 MOsFET由 于 带 有 各 种 无 损 耗 电流感 测 特 性 ,故 被 称 GND VDD DRAIN V|PER28 ‘ ‘ 丿氵 senscFET” ' 形与引脚排列如图2所 示 。 VIPEV8的 各个引脚功能见表 1。 EPT FB D丨 三 、主要性 能 与特点 P-7 VIPEV8的 主要性能与特点有 图2VIPER28外 形 与 引脚 排 列 电路 已嵌 入 到 芯 片 上 。VIPER28的 工 作 频 率 有 60KHz (VIPER28LN)和 115KHz(VIPEVSHN)两 种 。 VIPEV8主 要 由高性能低压PWM控 制器和带 电流 感测 的高压 MOSFET两 个部分 组 成 ,芯 片 电路组成如 围AC输 入的反激 式离线转换器 。 荡器 、 带软 启 动特征 的启 动 电路 、 PWM逻 辑 、 带可 电源 电压VDD在 导通之后的范 围为8.5~23.5V, VDD启 动门限 电平是 14V± (3)SenseFET的 (。 ,脉 冲漏极 电流达3A,最 大漏极 电流限制在 VIPEV8适 用功率如表2所 示 。 08A。 表2vIPER28适 用功 率 230Vac (EPT)电 路 、 欠 电 电路 等 。栅极 驱 动器 驱动一个 BVDs冫 800v、 RDs(。 n) =7Ω (在 25℃ 时 )的 N沟 道 功率 MOsFET。 这种 集成 B VDss≥ 800V,导 通态 电阻 RDs n)兰 7Ω 调设定点 的 电流 限制 电路 、 第 二 过 电流保护 电路 、 突 (UVLo)电 路 、 自动重新启 动 电路 和热保 护 lV,欠 电压关 闭门限 电平 是8V± 0.5V,钳 位 电压彐 3,5V(ID疒 ⒛1nA)。 图 1所 示 。 VIPER28的 控制器 电路包 含带频率颤抖特性 的振 : (1)集 低压PWM控 制器与800V的 scnseFET与 同一 芯片上 ,仅 需外加少量元件 ,即 可构建 高性能的宽范 (⑷ 二、ⅥPER2aJ0基 本结构和引脚功能 发模 式管理 电路 、 额外 电源管理 。 vIPER28采 用 7引 脚 双 列直 插 式 (DIP)封 装 ,外 DRAIN C0NT 压锁 定 ; 85~265VaC 适配器 敞开架构 适 配器 敞开 架构 18VV 24W 10VV 13W CHlNA P0VVER sUPPLY SURVEY (⑶ 工 作频率有 ω KHZ(L型 )和 115KHz(H型 ) 两种版本 ,PWM操 作带频率颤抖具有低 EMI。 (5)在 265响 c下 的待机 (“ andby)功 率 <50mW。 (6)提 供 软 启 动 和 故 障状 态 之 后 的 自动 重 新 启 通 ,从 引脚VDD流 出3mA的 电流对 C3充 电。对于故 障之后 的 自动 重 新启动模 式 ,充 电C3的 电流减少到 06n1A。 当VDEl电 压达 到启 动 门限VDLl。 n(约 14V)时 ,U1 动。 中的功率 MOsFET开 始开 关 ,HV电 流产 生器 关 断 c (7)供 两 电平 过 电流 保 护 、 过 载 保 护 、 可 调 过 电压保 护及 门限是 170℃ (带 30℃ 滞 后 )的 热 关 闭保 U1开 始 正 常 工 作 后 ,绕 组 Nb感 生 的高频 电压 经 D4整 护。 式计算 流和 R5、 C3滤 波 ,为 VDD引 脚供 电 。VDD电 容根据下 : C3= ・ rD￡ )c″ rssJ″ . =3P,a/× r$夕 莎 $四 〃.=3r9F/× J庄 -’ 67 ’ 14/-8/ %D口 ″ fDDl,f/ 式中tssaux是 偏置 (辅 助 )绕 组Nb进 入稳态所需要 四 、功 能与 工作 原 理 1.典 型 应 用 电路 由 VIPER28组 成 的 离 线 反 激 式 开 关 电 源 的时间 。 如果 VDD电 压降至 VDIl。 疒 8Ⅴ 以下 ,U1中 的功率 R5和 C3组 MOSFET将 被关断 ,传 送到IC的 能量 中断 。如果变换 器输入DC电 压VⅨ 低于 80V,启 动时序被禁 止 。 (2)自 动重新启动操作 如果在变换器掉 电后 ,VIN高 于 80V,启 动 时序 流滤波 电路 ,变 压器 T1辅 助绕组Nb、 成 VIPER28(U1)的 D4、 VDD偏 置 电源 电路 ,R1、 C2和 D2组 成 RCD型 初级 NP钳 位 电路 ,D5、 C6组 成次级输 出整流滤波 电路 ,R8汊 9、 U2(TL431)和 光 电耦合 则不被禁 止 ,并 且 在 VDD电 压降至 VDEl(REsTA 器 U3等 组成反馈环路 。 RT)门 限 (4,5V)以 下 时被激活 。这意味着HV启 动 吧流产 生 2.工 作 原 理 器重新开始对VDD电 容 C3充 电。在一个故障之后 ,对 ㈠ )启 动 ,DC高 压加至U1 (HV)电 流产 生器启动导 当 电容 C1上 的电压超过 80V时 的DRAIN引 脚 ,内 部高压 C3的 充 电电流是 0.6mA,而 正 常启动变换器 时的充 电电流是 3mA。 在 一 个故 障之后 ,IC重 新启 动有一 个 非常 长 的重 复 率 ,变 换 器 安 全 工 作 ,仅 有 非常低 的功率通 过 量 (througllptlt)。 图4为 发 生短 路 后 的IC特 性 。 (3)振 荡器 VIPER28的 开 关频 率 固定在 60KHz或 I15KHz,在 250Hz的 速 上↑⊥〓 率 上利 用 ±4KHZ(60KHZ版 本 ) 或 ±8KHZ(115KHz版 本 )对 开 关频率进行调制 。扩展频谱影响 开 关频 率 每 个 谐 波 上 的分 布 能 量 ,但 总 的说来在若干边带 上 的 谐波有相 同的能量 ,只 是幅度较 /l、 。 ‘(4)电 图3VIPER28组 成 的 离线反 激 式 开 关 电 源 电路 护 流限制与过 电压保 (oVP) 2010年 10期 |63 屮 一△∷〓 (SMPs)电 路如 图3所 示 。其 中 ,D1和 C1为 桥式整 CHlNA P0WER sUPPLY sURVEY 技术研 究与应 用 VDD 式 中 :V。 vP=3V,为 oVP门 限 ;Nb/Ns为 偏置绕组 、 /DD。 n VDD° 与次级绕组 匝数 比 ;V。 uT。 vP为 设计者设置 的激活 oVP “ VDD(REst^Rη 的变换器输 出 电压值 ;VDs℃ 是次级整流二极管 的正 向 VDs ˉˉˉ^ˉ 弯 电压降 。 Trep^ =ˉ DD_cH御 R3电 阻值可 以表示 为 in仰 Ρ矧 R3=R4× : [ll-Κ @/P)/JCε /P] (5)反 馈与过载保护 (oLP) 电流型控 制器 的反馈 引脚FB控 制PWM操 作和突 发模式 ,并 用来激活过载保 护 (oLP)。 FB引 脚 上 的 图4在 发 生短路后 的Ic相 关波形 VIPER28中 MOSFET漏 极 电流 被 内部 Rscnse感 测 并转换 为 电压输 入到 PWM比 较器 的 同相 输 入端 ,并 与 引脚 FB上 的 电压进 行 比较 。通 过 引脚 CoNT,可 以调 节 电流 限制 设 置 点 。MOsFET的 最 大 漏 极 限制 电流 是 08A。 在 T1的 辅 助 (即 偏 置 )绕 组 Nb上 ,连 接 一 个 电阻 R3/R4。 分压器 在 MOsFET关 断期 间 ,偏 置 绕 组 产 生 一 个 跟踪 输 出 的一 个 电压 ,并 利 用 U1的 CONT引 脚 来监视变换器 输 出电压 。当引脚 CONT上 的电压超过 3V的 参考 时 ,通 过 内部计数器在 4个 连续的时间中 , 电压在0,6V与 3,5V之 间 ,PWM比 较器非反相输入端上 的电流感测信号通过分压器在逐周偏置上与引脚FB上 的一个 电压相比较 。当两个 电压相等时 ,PWM逻 辑命 令功率MOSFET关 断 。在过载情况下 ,引 脚FB上 的电 压增加 。当VF沪 35v时 ,MOSFET漏 极 电流被限制 PWM比 较器失能 ,内 部 电流产生器开始充 电反馈 电容 C5。 时间与c5值 有关 ,计 算公式是 ‰ 控制器能够识 别过 电压故 障 。 当在 一 个振荡周期 中 。″ = R4 R3+R4 (Ⅳ b/Ⅳs)(%(∫ Tc,Ⅱ +%跖 C)-%"c. 鄂 =6叩 阴 ⒁ 当负载减小 时 ,反 馈 端 上 的 电压 VF:降 低 。 只要 VF:达 到 : ⑾ =6× : (6)突 发摸式操作 oVP信 号不被触发时 ,计 数器则复位 ,如 图5所 示 。 Κ 当反馈 电压达到48V的 过载关闭门限时 ,变 换器 关断 ,同 时启动状态被激活 。从过载检测到U1关 闭的 , UI引 脚CONT上 的分压比K。 xfP可 表示为 , 突 出 模 式 门 限 V":M(06V),MOSFET就 会停 止 开关 。在 MOSFET截 止 之 后 ,由 于 反馈 的反 作 用 ,在 引脚 FB上 的 电压 增 加 。 当 VF:比 VF::M高 出 0,1V 时 ,MOSFET再 次开始开关 CONT (pin4) , 如 图 6所 示 。在 突 发模 式操作 3V 期 间 ,MOSFET漏 极 电流 被 限制 在 IDs田 M)=16omA。 进 入 sTROBE 突 发模 式后 ,VFIl降 低 。一 旦 0VP VF:=0.6V,开 关 则 又 一 次停 COUNTER 止 。突 发模 式工 作 频 率 远 低 REsET COUNTER sTATUs FAULT 1→ 2 ∶2→ 0 ∶ o 293 ∶∶3,4 o→ 1 于正 常操作频率 ,可 大大减 小 轻 载 或 无 载 时 的功 率 损 耗 正常工作 暂时干扰 : ∴ 反馈回路故障 图5过 电压保护(OⅥ ))相 关波 形 , 致 使 在 265Vac时 的待 机 功 率 CHlNA POWER SUPPLY SURVEY 技术研 究与应 用 被 接 受 ,保 护 逻 辑 在 其 空 闲状 态 将 复 位 。如 果 在 两 个 连 续 开 关 周 期 中 超过第 二 个 oCP门 限 (12A),功 率 MOsFET将 关断 。如果故 障状态不解 除 ,IC进 入重 新 启 动模 式 ,并 导 致 “ 低频 间歇操作 ,即 所谓 打嗝模式操 ” 作 ,在 功率 电路上仅有非常小 的应 i | ˉ |(-ˉ Norma卜 mode- Burst m。 力 。 图7为 打嗝模 式0CP定 时图 。 突发 模 式 de 图6突 发 模 式 操 作 五 、结 束语 secondary diode is shorted here 流传 感 的功率 SCnscFET和 高性 能低 压 PWM控 制器 集 成在 一 起 的 组 合 离 线 转 换 器 IC。 基 于 VIPER28的 反 激 式 sMPs,仅 需 用很少量 的元件 ,即 可输 出 10~24W的 功率 。突 发模 式操 作 ,使 待 机 功耗 (50mW,满 足 待机 节能规 范 。 先进 的PWM操 作 带 频率 <50mW。 抖动 ,有 非常低 的EMI。 高压启 动 电 图7打 嗝 模 式 O CP定 时 图 路嵌 入到芯 片 上 ,无 需外加启动元件 即可使 IC启 动 。ⅤIPER28提 供 两 电平 oCP、 过 电压保护 、滞后过热保护 、过载保护和故障 (7)额 外 电源管理 (EPT) VIPER28引 脚 EPT上 连接 一个 电容 C4(CEPT), 用逐 周 5uA的 电流对 其充 电和放 电 。 当MOsFET漏 极 电流增加到 限制值 IDLIIvl的 85%时 ,Ul内 部 的 电流产 生 器对 C4充 电 ;一 旦漏 极 电流低于 0.85IDuM,C4放 电 。 如果 C4上 电压达 到 4V的 门 限VEPT,变 换 器 关 闭 。在 (典 型 变换器 关 闭之 亏 ,VDD电 压降至启 动 门限VD以 。 Ⅱ 值 是 14,5V)以 下 。为 了重新启动操作 ,VDD必 须低子 门限 电平 45V,才 能对 VDD电 容 C3充 电 。 当引脚 EPT 上 的 电压低于 06V的 门限VE町 (RE阢 A町 )时 ,PWM操 作 重新赋能 。如果 EPT功 能不 用 ,U1的 引脚 EPT可 以接 地。 (8)第 二 电平过 电流保 护和打 嗝模式 (hiccup mode) 后的安全重新启动 。VIPER28可 以用于机顶盒 、DVD 播放机和录音机及wh∞ goods等 sMPs,也 可用于ATX 辅助电源 、低/中 功率Aα DC适 配器 以及消费类和家用 电器 的辅助电源 ,还 可以用于LED照 明电源 。∷ 钮 ∷ |∷ 参考 文献 : [11VIPER28of— hnc st con△ hlgh voltagc convcrtc‘ Ⅵ、 V、厂 ,2008,9 I2]叶 慧 贞 ,杨 兴洲 新 颖开关稳压 电源 [Ml北 京 : 国防 工业 出版社 ,,ll00 [3]沙 占友 ,马 洪 涛 特 种 集成 电源设 计 与应 用 IMl北 京 :中 国电力 出版社 ,⒛ Clb VIPER28对 次级整 流器短路 、 次级绕 组短 路和反 激变压器硬饱和提供保护 。为从 一 个干扰信号辨别真 正 的故 障 ,在 第一个信号 断开之后则进入预警状态 。 如果在连 续 的开关周期 中信号不断开 ,一 个暂 时干扰 zOi0钔 0期 卜 ∞∷ 一 一一∷ ∷∷扌∷ ∷〓∵ ∷一 VIPER28是 一 种 将 800V的 带 电 次级二极管短路 VIPER28 Off-line high voltage converters Features ■ 800 V avalanche rugged power section ■ PWM operation with frequency jittering for low EMI ■ Operating frequency: – 60 kHz for L type – 115 kHz for H type SDIP10 SO16 narrow Description ■ Standby power < 50 mW at 265 VAC ■ Limiting current with adjustable set point ■ Adjustable and accurate over-voltage protection ■ On-board soft-start ■ Safe auto-restart after a fault condition ■ Hysteretic thermal shutdown ■ Delayed overload protection DIP-7 SO 16 The device is an off-line converter with an 800 V rugged power section, a PWM control, two levels of over-current protection, over-voltage and overload protections, hysteretic thermal protection, soft-start and safe auto-restart after any fault condition removal. Burst mode operation and device very low consumption helps to meet the standby energy saving regulations. Advance frequency jittering reduces EMI filter cost. The extra power timer allows the management of output peak power for a designed time window. Application ■ Auxiliary power supply for consumer and home equipment ■ ATX auxiliary power supply ■ Low / medium power AC-DC adapters ■ SMPS for set-top boxes, DVD players and recorders, white goods The high voltage start-up circuit is embedded in the device. Figure 1. Typical topology + + DC input high voltage wide range DC Output voltage DRAIN DRAIN EPT VIPER28 GND Table 1. VDD CONT FB Device summary Order codes Package VIPER28LN / VIPER28HN DIP-7 VIPER28LE / VIPER28HE SDIP10 Packaging Tube VIPER28HD / VIPER28LD SO16 narrow VIPER28HDTR / VIPER28LDTR October 2009 Tape and reel Doc ID 15028 Rev 3 1/32 www.st.com 32 Contents VIPER28 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 Operation descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1 Power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2 High voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.3 Power-up and soft-start up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.4 Power down operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.5 Auto restart operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.6 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.7 Current mode conversion with adjustable current limit set point . . . . . . . 18 7.8 Over-voltage protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.9 About CONT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.10 Feed-back and overload protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . 20 7.11 Burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 23 7.12 Extra power management function (EPT) . . . . . . . . . . . . . . . . . . . . . . . . 24 7.13 2nd level over-current protection and hiccup mode . . . . . . . . . . . . . . . . . 24 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2/32 Doc ID 15028 Rev 3 VIPER28 Block diagram 1 Block diagram Figure 2. Block diagram Vcc VDD DRAIN LEB Internal Supply bus & Ref erence Voltages EPT Tov l BLOCK EPT Tovl SUPPLY & UVLO HV_ON UVLO OSCILLATOR Istart-up THERMAL SHUTDOWN OLP SOFT START OCP BLOCK - CONT TURN-ON LOGIC BURST OCP + OVP DETECTION + LOGIC PWM BLOCK LEB R Q S HV_ON R 2nd OCP + + - Q PWM - OVP OTP S Disable 2nd OCP LOGIC OTP OVP OLP Rsense BURST-MODE REFERENCES BURST-MODE LOGIC BURST FB GND 2 Typical power Table 2. Typical power 230 VAC Part number VIPER28 85-265 VAC Adapter(1) Open frame(2) Adapter(1) Open frame(2) 18 W 24 W 10 W 13 W 1. Typical continuous power in non ventilated enclosed adapter measured at 50 °C ambient. 2. Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate heat sinking. Doc ID 15028 Rev 3 3/32 Pin settings 3 VIPER28 Pin settings Figure 3. Connection diagram (top view) '.$ $2!). 6$$ $2!). #/.4 $2!). &" $2!). %04 $2!). &15 &15 3$)0 $)0 3/. Note: The copper area for heat dissipation has to be designed under the DRAIN pins. Table 3. Pin description Pin n. Name Function SDIP10 DIP-7 SO16N 1 1 4 GND This pin represents the device ground and the source of the power section. 2 2 5 VDD Supply voltage of the control section. This pin also provides the charging current of the external capacitor during start-up time. 3 3 6 Control pin. The following functions can be selected: 1. current limit set point adjustment. The internal set default value of the cycleby-cycle current limit can be reduced by connecting to ground an external CONT resistor. 2. output voltage monitoring. A voltage exceeding 3 V shuts the IC down reducing the device consumption. This function is strobed and digitally filtered for high noise immunity. 4 4 7 FB 5 5 8 EPT 6...10 7,8 4/32 Control input for duty cycle control. Internal current generator provides bias current for loop regulation. A voltage below 0.6 V activates the burst-mode operation. A level close to 3.3 V means that the device is approaching the cycle-by-cycle over-current set point. This pin allows the connection of an external capacitor for the extra power management. If the function is not used, the pin has to be connected to GND. High voltage drain pin. The built-in high voltage switched start-up bias current 13...16 DRAIN is drawn from this pin too. Pins connected to the metal frame to facilitate heat dissipation. Doc ID 15028 Rev 3 VIPER28 Electrical data 4 Electrical data 4.1 Maximum ratings Table 4. Absolute maximum ratings Value Symbol Parameter Unit Min Max VDRAIN Drain-to-source (ground) voltage V EAV Repetitive avalanche energy (limited by TJ = 150 °C) 5 mJ IAR Repetitive avalanche current (limited by TJ = 150 °C) 1.5 A 3 A IDRAIN Pulse drain current VCONT Control input pin voltage (with ICONT = 1 mA) -0.3 Self limited V VFB Feed-back voltage -0.3 5.5 V VEPT EPT input pin voltage -0.3 5 V VDD Supply voltage (IDD = 25 mA) -0.3 Self limited V IDD Input current 25 mA Power dissipation at TA < 50 °C 1 W PTOT TJ TSTG 4.2 800 Operating junction temperature range -40 150 °C Storage temperature -55 150 °C Thermal data Table 5. Thermal data Max value Symbol Parameter Unit SO16N DIP7 SDIP10 RthJP Thermal resistance junction pin (Dissipated power = 2 W) 20 40 25 °C/W RthJA Thermal resistance junction ambient (Dissipated power = 2 W) 50 100 75 °C/W RthJA Thermal resistance junction ambient (1) (Dissipated power = 2 W) 40 80 55 °C/W 1. When mounted on a standard single side FR4 board with 100 mm2 (0.155 sq in) of Cu (35 µm thick) Doc ID 15028 Rev 3 5/32 Electrical data 4.3 VIPER28 Electrical characteristics (TJ = -25 to 125 °C, VDD = 14 V; unless otherwise specified) Table 6. Symbol VBVDSS IOFF RDS(on) COSS Table 7. Symbol Power section Parameter Break-down voltage OFF state drain current Drain-source on state resistance Effective (energy related) output capacitance Test condition Min IDRAIN = 1 mA, VFB = GND TJ = 25 °C 800 Typ Max Unit V VDRAIN = max rating, 60 μA IDRAIN = 0.4 A, VFB = 3 V, VEPT = GND, TJ = 25 °C 7 Ω IDRAIN = 0.4 A, VFB = 3 V, VEPT = GND, TJ = 125 °C 14 Ω VFB = GND VDRAIN = 0 to 640 V 40 pF Supply section Parameter Test condition Min Typ Max Unit 60 80 100 V VDRAIN = 120 V, VEPT = GND, VFB = GND, VDD = 4 V -2 -3 -4 mA VDRAIN = 120 V, VEPT = GND, VFB = GND, VDD = 4 V after fault. -0.4 -0.6 -0.8 mA Operating voltage range After turn-on 8.5 23.5 V VDD clamp voltage IDD = 20 mA 23.5 Voltage VDRAIN_START IDDch VDD VDDclamp Drain-source start voltage Start up charging current V 13 14 15 V VEPT = GND, VFB = GND 7.5 8 8.5 V VDD restart voltage threshold VDRAIN = 120 V, VEPT = GND, VFB = GND 4 4.5 5 V IDD0 Operating supply current, not switching VFB = GND, FSW = 0 kHz, VEPT = GND, VDD = 10 V 0.9 mA IDD1 Operating supply current, switching VDRAIN = 120 V, FSW = 60 kHz 2.5 mA VDRAIN = 120 V, FSW = 115 kHz 3.5 mA 400 uA 270 uA VDDon VDD start up threshold VDDoff VDD under voltage shutdown threshold VDD(RESTART) VDRAIN = 120 V, Current 6/32 IDD_FAULT Operating supply current, with protection tripping IDD_OFF Operating supply current with VDD < VDD_OFF VDD = 7 V Doc ID 15028 Rev 3 VIPER28 Electrical data Table 8. Controller section (TJ = -25 to 125 °C, VDD = 14 V; unless otherwise specified) Symbol Parameter Test condition Min Typ Max Unit Feed-back pin VFBolp Over-load shut down threshold 4.5 4.8 5.2 V VFBlin Linear dynamics upper limit 3.2 3.5 3.7 V VFBbm Burst mode threshold Voltage falling 0.6 V VFBbmhys Burst mode hysteresis Voltage rising 100 mV IFB RFB(DYN) HFB Feed-back sourced current VFB = 0.3 V -150 3.3 V < VFB < 4.8 V Dynamic resistance VFB < 3.3 V ΔVFB / ΔID -200 -280 -3 uA uA 14 20 kΩ 2 6 V/A CONT pin VCONT_l Low level clamp voltage ICONT = -100 µA 0.5 V Current limitation IDlim Max drain current limitation tSS Soft-start time TON_MIN td tLEB ID_BM VFB = 4 V, ICONT = -10 µA TJ = 25 °C 0.75 0.80 0.85 8.5 Minimum turn ON time 220 400 A ms 480 ns Propagation delay 100 ns Leading edge blanking 300 ns 160 mA Peak drain current during burst mode VFB = 0.6 V Oscillator section VIPER28L FOSC FD VDD = operating voltage range, VFB = 1 V VIPER28H Modulation depth FM Modulation frequency DMAX Maximum duty cycle 54 60 66 kHz 103 115 127 kHz VIPER28L ±4 kHz VIPER28H ±8 kHz 250 Hz Doc ID 15028 Rev 3 70 80 % 7/32 Electrical data VIPER28 Table 8. Controller section (continued) (TJ = -25 to 125 °C, VDD = 14 V; unless otherwise specified) Symbol Parameter Test condition Min Typ Max Unit Over-current protection (2nd OCP) IDMAX Second over-current threshold 1.2 A Over-voltage protection VOVP Over-voltage protection threshold TSTROBE Over-voltage protection strobe time 2.7 3 3.3 V 2.2 us 85% IDLIM A 4 V 0.6 V 5 μA 160 °C 30 °C Extra power management IDLIM_EPT Drain current limit with EPT function VEPT(STOP) EPT shut down threshold VEPT(RESTART) EPT restart threshold IEPT Sourced EPT current ICONT < -10 μA TJ = 25 °C ICONT < -10 μA Thermal shutdown 8/32 TSD Thermal shutdown temperature THYST Thermal shutdown hysteresis Doc ID 15028 Rev 3 150 VIPER28 Electrical data Figure 4. Minimum turn-on time test circuit EPT Figure 5. OVP threshold test circuits EPT (The OVP protection is triggered after four consecutive oscillator cycles) Doc ID 15028 Rev 3 9/32 Typical electrical characteristics VIPER28 5 Typical electrical characteristics Figure 6. Current limit vs TJ Figure 7. Switching frequency vs TJ Figure 8. Drain start-up voltage vs TJ Figure 9. HFB vs TJ Figure 10. Operating supply current (no switching) vs TJ 10/32 Figure 11. Operating supply current (switching) vs TJ Doc ID 15028 Rev 3 VIPER28 Typical electrical characteristics Figure 12. Current limit vs RLIM Figure 13. Power MOSFET on-resistance vs TJ Figure 14. Power MOSFET break down voltage vs TJ Doc ID 15028 Rev 3 11/32 Typical electrical characteristics VIPER28 Figure 15. Thermal shutdown TJ TSD THYST t VDD VDD ON VDD OFF VDD RESTART t VDS t 12/32 Doc ID 15028 Rev 3 VIPER28 6 Typical circuit Typical circuit Figure 16. Min-features flyback application EPT Figure 17. Full-feature flyback application EPT Doc ID 15028 Rev 3 13/32 Operation descriptions 7 VIPER28 Operation descriptions VIPER28 is a high-performance low-voltage PWM controller chip with an 800 V, avalanche rugged power section. The controller includes: the oscillator with jittering feature, the start up circuits with soft-start feature, the PWM logic, the current limit circuit with adjustable set point, the second over-current circuit, the burst mode management circuit, the EPT circuit, the UVLO circuit, the auto-restart circuit and the thermal protection circuit. The current limit set-point is set by the CONT pin. The burst mode operation guaranties high performance in the stand-by mode and helps in the energy saving norm accomplishment. All the fault protections are built in auto restart mode with very low repetition rate to prevent IC's overheating. 7.1 Power section and gate driver The power section is implemented with an avalanche ruggedness n-channel power MOSFET, which guarantees safe operation within the specified energy rating as well as high dv/dt capability. The power section has a BVDSS of 800 V min. and a typical RDS(on) of 7 Ω at 25 °C. The integrated SenseFET structure allows a virtually loss-less current sensing. The gate driver is designed to supply a controlled gate current during both turn-on and turnoff in order to minimize common mode EMI. Under UVLO conditions an internal pull-down circuit holds the gate low in order to ensure that the Power section cannot be turned on accidentally. 7.2 High voltage startup generator The HV current generator is supplied through the DRAIN pin and it is enabled only if the input bulk capacitor voltage is higher than VDRAIN_START threshold, 80 VDC typically. When the HV current generator is ON, the IDDch current (3 mA typical value) is delivered to the capacitor on the VDD pin. In case of Auto Restart mode after a fault event, the IDDch current is reduced to 0.6 mA, typ. in order to have a slow duty cycle during the restart phase. See Figure 18 on page 15. 14/32 Doc ID 15028 Rev 3 VIPER28 7.3 Operation descriptions Power-up and soft-start up If the input voltage rises up till the device start level (VDRAIN_START), the VDD voltage begins to grow due to the IDDch current (see Table 6 on page 6) coming from the internal high voltage start up circuit. If the VDD voltage reaches VDDon threshold (~14 V) the power MOSFET starts switching and the HV current generator is turned OFF. See Figure 19 on page 16. The IC is powered by the energy stored in the capacitor on the VDD Pin, CVDD, until the selfsupply circuit (typically an auxiliary winding of the transformer and a steering diode) develops a voltage high enough to sustain the operation. CVDD capacitor must be sized enough to avoid fast discharge and keep the needed voltage value higher than VDDoff threshold: a too low capacitance value could terminate the switching operation before the controller receives any energy from the auxiliary winding. The following formula can be used for the VDD capacitor calculation: Equation 1 I DDch × t SSaux C VDD = ---------------------------------------V DDon – V DDoff The tSSaux is the time needed for the steady state of the auxiliary voltage. This time is estimated by applicator according to the output stage configurations (transformer, output capacitances, etc.). During the converter start up time, the drain current limitation is progressively increased to the maximum value. In this way the stress on the secondary diode is considerably reduced. It also helps to prevent transformer saturation. The soft-start time lasts 8.5 ms and the feature is implemented for every attempt of start up converter or after a fault. See Figure 20 on page 16. Figure 18. Start up IDD current IDD VDS = 120V FSW = 0 kHz AFTER FAULT 2 mA 1 mA IDD0 IDD_FAULT IDD_OFF IDS_CH_FAULT -1 mA VDDrestart VDDoff VDDon VDD -2 mA -3 mA IDS_CH -4 mA Doc ID 15028 Rev 3 15/32 Operation descriptions VIPER28 Figure 19. Timing diagram: normal power-up and power-down sequences Vin VStart VVcc DD regulation is lost here t VVcc DD ON VVcc DD OFF VVcc DD restart t VDRAIN IDDch Icharge t 3 mA Normal operation Power -on t Power -off Figure 20. Soft-start: timing diagram I DRAIN tss IDLIM t V FB V FB OLP V FB_lin t 16/32 Doc ID 15028 Rev 3 VIPER28 7.4 Operation descriptions Power down operation At converter power down, the system loses regulation as soon as the input voltage is so low that the peak current limitation is reached. The VDD voltage drops and when it falls below the VDDoff threshold (8 V typical) the power MOSFET is switched OFF, the energy transfer to the IC is interrupted and consequently the VDD voltage continues to decreases, Figure 19 on page 16. Later, if the VIN is lower than VDRAIN_START (80 V typical), the start up sequence is inhibited and the power down completed. This feature is useful to prevent converter’s restart attempts and ensures monotonic output voltage decay during the system power down. 7.5 Auto restart operation If after a converter power down, the VIN is higher than VDRAIN_START, the start up sequence is not inhibited and will be activated only when the VDD voltage drops down the VDDrestart threshold (4.5 V typical). This means that the HV start up current generator restarts the VDD capacitor charging only when the VDD voltage drops below VDDrestart. The scenario above described is for instance a power down because of a fault condition. After a fault condition, the charging current is 0.6 mA (typ.) instead of the 3 mA (typ.) of a normal start up converter phase. This feature together with the low VDDrestart threshold (4.5 V) ensures that, after a fault, the restart attempts of the IC has a very long repetition rate and the converter works safely with extremely low power throughput. The Figure 21 shows the IC behavioral after a short circuit event. Figure 21. Timing diagram: behavior after short circuit VDD Short circuit occurs here VDDon DD VDDoff DD VDD(RESTART) VDS Trep t < 0.03Trep t t IDD_CH 0.6 mA FB Pin t 4.8 V 3.3 V t Doc ID 15028 Rev 3 17/32 Operation descriptions 7.6 VIPER28 Oscillator The switching frequency is internally fixed to 60 kHz or 115 kHz. In both case the switching frequency is modulated by approximately ±4 kHz (60 kHz version) or ±8 kHz (115 kHz version) at 250 Hz (typical) rate, so that the resulting spread-spectrum action distributes the energy of each harmonic of the switching frequency over a number of side-band harmonics having the same energy on the whole but smaller amplitudes. 7.7 Current mode conversion with adjustable current limit set point The device is a current mode converter: the drain current is sensed and converted in voltage that is applied to the non inverting pin of the PWM comparator. This voltage is compared with the one on the feed-back pin through a voltage divider on cycle by cycle basis. The VIPER28 has a default current limit value, IDLIM, that the designer can adjust according the electrical specification, by the RLIM resistor connected to the CONT see Figure 12 on page 11. The CONT pin has a minimum current sunk needed to activate the IDLIM adjustment: without RLIM or with high RLIM (i.e. 100 kΩ) the current limit is fixed to the default value (see IDLIM, Table 8 on page 7). 7.8 Over-voltage protection (OVP) The device can monitor the converter output voltage. This operation is done by CONT pin during power MOSFET OFF-time, when the voltage generated by the auxiliary winding tracks converter's output voltage, through turn ratio N See Figure 22. AUX -------------N SEC In order to perform the output voltage monitor, the CONT pin has to be connected to the aux winding through a resistor divider made up by RLIM and ROVP (see Figure 17 (R3, R4 are respectively ROVP and RLIM)and Figure 23). If the voltage applied to the CONT pin exceeds the internal 3 V reference for four consecutive times the controller recognizes an over-voltage condition. This special feature uses an internal counter; that is to reduce sensitivity to noise and prevent the latch from being erroneously activated. see Figure 22 on page 19. The counter is reset every time the OVP signal is not triggered in one oscillator cycle. Referring to the Figure 17, the resistors divider ratio kOVP will be given by: Equation 2 V OVP k OVP = -------------------------------------------------------------------------------------------------N AUX -------------- ⋅ ( V OUTOVP + V DSEC ) – V DAUX N SEC 18/32 Doc ID 15028 Rev 3 VIPER28 Operation descriptions Equation 3 R LIM k OVP = --------------------------------R LIM + R OVP Where: ● VOVP is the OVP threshold (see Table 8 on page 7) ● VOUT OVP is the converter output voltage value to activate the OVP set by designer ● NAUX is the auxiliary winding turns ● NSEC is the secondary winding turns ● VDSEC is the secondary diode forward voltage ● VDAUX is the auxiliary diode forward voltage ● ROVP together RLIM make the output voltage divider Than, fixed RLIM, according to the desired IDLIM, the ROVP can be calculating by: Equation 4 1 – k OVP R OVP = R LIM × ----------------------k OVP The resistor values will be such that the current sourced and sunk by the CONT pin be within the rated capability of the internal clamp. Figure 22. OVP timing diagram VDS t VAUX 0 CONT (pin 4) t 3V t 2 µs STROBE 0.5 µs t OVP t COUNTER RESET COUNTER STATUS t 0 0 0 0 →1 1 →2 2 →0 0 0 →1 1 →2 2 →3 FAULT 3 →4 t NORMAL OPERATION TEMPORARY DISTURBANCE Doc ID 15028 Rev 3 FEEDBACK LOOP FAILURE t 19/32 Operation descriptions 7.9 VIPER28 About CONT pin Referring to the Figure 23, through the CONT PIN, the below features can be implemented: 1. Current limit set point 2. Over-voltage protection on the converter output voltage The Table 9 on page 20 referring to the Figure 23, lists the external resistance combinations needed to activate one or plus of the CONT pin functions. Figure 23. CONT pin configuration Rov p SOFT START CONT OCP Comparator Current Limit Curr. Lim. BLOCK - Daux + Auxiliary winding To PWM Logic OVP DETECTION Rlim LOGIC From SenseFET To OVP Protection Table 9. 7.10 CONT pin configurations Function / component RLIM ROVP DAUX IDlim reduction See Figure 6 No No OVP ≥ 80 KΩ See Equation 4 Yes IDlim reduction + OVP See Figure 6 See Equation 4 Yes Feed-back and overload protection (OLP) The VIPER28 is a current mode converter: the feedback pin controls the PWM operation, controls the burst mode and actives the overload protection of the device. Figure 24 on page 22 and Figure 25 show the internal current mode structure. With the feedback pin voltage between VFB_bm and VFBlin, (respectively 0.6 V and 3.5 V, typical values) the drain current is sensed and converted in voltage that is applied to the non inverting pin of the PWM comparator. This voltage is compared with the one on the feedback pin through a voltage divider on cycle-by-cycle basis. When these two voltages are equal, the PWM logic orders the switch off of the power MOSFET. The drain current is always limited to IDLIM value. 20/32 Doc ID 15028 Rev 3 VIPER28 Operation descriptions In case of overload the feedback pin increases in reaction to this event and when it goes higher than VFBlin the drain current is limited or to the default IDLIM value or the one imposed through a resistor at the CONT pin (using the RLIM, see Figure 6 on page 10); the PWM comparator is disabled. At the same time an internal current generator starts to charge the feedback capacitor (CFB) and when the feedback voltage reaches the VFBolp threshold, the converter is turned off and the start up phase is activated with reduced value of Icharge to 0.6 mA. During the first start up phase of the converter, after the soft-start up time (typical value is 8.5 ms) the output voltage could force the feedback pin voltage to rise up to the VFBolp threshold that switches off the converter itself. To avoid this event, the appropriate feedback network has to be selected according to the output load. More the network feedback fixes the compensation loop stability. The Figure 24 on page 22 and Figure 25 on page 23 show the two different feedback networks. The time from the overload detection (VFB = VFBlin) to the device shutdown (VFB = VFBolp) can be calculated by CFB value (see Figure 24 on page 22 and Figure 25), using the formula: Equation 5 V FBolp – V FBlin T OLP – delay = C FB × ---------------------------------------3μA In the Figure 24, the capacitor connected to FB pin (CFB) is used as part of the circuit to compensate the feedback loop but also as element to delay the OLP shut down owing to the time needed to charge the capacitor (see 5). After the start up time, 8.5 ms typ value, during which the feedback voltage is fixed at VFBlin, the output capacitor could not be at its nominal value and the controller interpreters this situation as an overload condition. In this case, the OLP delay helps to avoid an incorrect device shut down during the start up face. Owing to the above considerations, the OLP delay time must be long enough to by-pass the initial output voltage transient and check the overload condition only when the output voltage is in steady state. The output transient time depends from the value of the output capacitor and from the load. When the value of the CFB capacitor calculated for the loop stability is too low and cannot ensure enough OLP delay, an alternative compensation network can be used and it is showed in Figure 25 on page 23. Using this alternative compensation network, two poles (fPFB, fPFB1) and one zero (fZFB) are introduced by the capacitors CFB and CFB1 and the resistor RFB1. The capacitor CFB introduces a pole (fPFB) at higher frequency than fZB and fPFB1. This pole is usually used to compensate the high frequency zero due to the ESR (Equivalent Series Resistor) of the output capacitance of the fly-back converter. The mathematical expressions of these poles and zero frequency, considering the scheme in Figure 25 are reported by the equations below: Doc ID 15028 Rev 3 21/32 Operation descriptions VIPER28 Equation 6 fZFB = 1 2 ⋅ π ⋅ CFB1 ⋅ RFB1 Equation 7 fPFB = RFB(DYN) + RFB1 2 ⋅ π ⋅ CFB ⋅ RFB(DYN) ⋅ RFB1 ( ) 1 2 ⋅ π ⋅ CFB1 ⋅ RFB1 + RFB(DYN) ) Equation 8 fPFB1 = ( The RFB(DYN) is the dynamic resistance seen by the FB pin and reported on Table 8 on page 7. The CFB1 capacitor fixes the OLP delay and usually CFB1 results much higher than CFB. The equation 5 can be still used to calculate the OLP delay time but CFB1 has to be considered instead of CFB. Using the alternative compensation network, the designer can satisfy, in all case, the loop stability and the enough OLP delay time alike. Figure 24. FB pin configuration From sense FET PWM To PWM Logic + PWM CONTROL - Cfb BURST BURST-MODE REFERENCES BURST-MODE LOGIC OLP comparator + 4.8V 22/32 Doc ID 15028 Rev 3 - To disable logic VIPER28 Operation descriptions Figure 25. FB pin configuration From sense FET PWM To PWM Logic + PWM CONTROL - Rfb1 Cfb BURST Cfb1 BURST-MODE REFERENCES BURST-MODE LOGIC OLP comparator + 4.8V 7.11 To disable logic - Burst-mode operation at no load or very light load When the load decrease the feedback loop reacts lowering the feedback pin voltage. As the voltage reach the burst mode threshold VFBbm MOSFET stops switching. After the MOSFET stops, as a result of the feedback reaction to the energy delivery stop, the feedback pin voltage increases and exceeding VFBbm threshold of 100 mV, the burst mode hysteresis typical value MOSFET the power device start switching again. Figure 26 shows this behavior called burst mode. Systems alternates period of time where power MOSFET is switching to period of time where power MOSFET is not switching. The power delivered to output during switching periods exceeds the load power demands; the excess of power is balanced from not switching period where no power is processed. The advantage of burst mode operation is an average switching frequency much lower then the normal operation working frequency, up to some hundred of hertz, minimizing all frequency related losses. During the burst mode operation the drain current is limited to ID_BM, 160 mA typ. value. Figure 26. Burst mode timing diagram, light load management FB 100 50 mV hyster. VFBBM I t DS Normal -mode Burst-mode Doc ID 15028 Rev 3 Normal -mode t 23/32 Operation descriptions 7.12 VIPER28 Extra power management function (EPT) Some applications need an extra power for a limited time window during which the converter regulation has to be guaranteed. The extra power management function allows to design a converter that can satisfy this request and is provided by the EPT pin, see Table 8 on page 8. This function requires the use of a capacitor on EPT pin (CEPT) that is charged or discharged by means of a 5 µA current cycle by cycle. When the drain current raises over 85% of Idlim value, see IDLIM_EPT (Table 8 on page 7), the current generator charges CEPT while when the drain current is below IDLIM_EPT discharges the capacitor. If CEPT ‘s voltage reaches the VEPT threshold (typical, 4 V), the converter is shut down. After the converter shut down, the VDD voltage will drop below the VDD(ON) start up threshold (typ. 14.5 V) and according to the auto restart operation (see Section 7.5 on page 17) the VDD pin voltage have to fall below the VDD(RESTART) threshold (typical, 4.5 V) in order to charge again the VDD capacitor. Moreover the PWM operation is enabled again only when the voltage on EPT pin, drop below the VEPT(RESTART) (typical, 0.6 V). The low CEPT discharge current in combination with its low restart threshold, ensures safe operations and avoids overheating in case of repeated overload events. The value of CEPT has to be selected in order to prevent the device overheating. The EPT pin can be connected to GND if the function is not used. 7.13 2nd level over-current protection and hiccup mode The VIPER28 is protected against short circuit of the secondary rectifier, short circuit on the secondary winding or a hard-saturation of fly-back transformer. Such as anomalous condition is invoked when the drain current exceed 1 A typical. To distinguish a real malfunction from a disturbance (e.g. induced during ESD tests) a “warning state” is entered after the first signal trip. If in the subsequent switching cycle the signal is not tripped, a temporary disturbance is assumed and the protection logic will be reset in its idle state; otherwise if the 2nd OCP threshold is exceeded for two consecutive switching cycles a real malfunction is assumed and the power MOSFET is turned OFF. The shutdown condition is latched as long as the device is supplied. While it is disabled, no energy is transferred from the auxiliary winding; hence the voltage on the VDD capacitor decays till the VDD under voltage threshold (VDDoff), which clears the latch. The start up HV current generator is still off, until VDD voltage goes below its restart voltage, VDD(RESTART). After this condition the VDD capacitor is charged again by 600 µA current, and the converter switching restart if the VDDon occurs. If the fault condition is not removed the device enters in auto-restart mode. This behavioral, results in a low-frequency intermittent operation (Hiccup-mode operation), with very low stress on the power circuit. See the timing diagram of Figure 27. 24/32 Doc ID 15028 Rev 3 VIPER28 Operation descriptions Figure 27. Hiccup-mode OCP: timing diagram VDD Vcc Secondary diode is shorted here VDDON VDD OFF VVcc DDrest t IDRAIN IDmax t V DS t Doc ID 15028 Rev 3 25/32 Package mechanical data 8 VIPER28 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 10. DIP-7 mechanical data mm Dim. Typ Min A 5,33 A1 0,38 A2 3,30 2,92 4,95 b 0,46 0,36 0,56 b2 1,52 1,14 1,78 c 0,25 0,20 0,36 D 9,27 9,02 10,16 E 7,87 7,62 8,26 E1 6,35 6,10 7,11 e 2,54 eA 7,62 eB L M (6)(8) N 10,92 3,30 2,92 3,81 0,40 0,60 2,508 0,50 N1 O (7)(8) 0,60 0,548 1- The leads size is comprehensive of the thickness of the leads finishing material. 2- Dimensions do not include mold protrusion, not to exceed 0,25 mm in total (both side). 3- Package outline exclusive of metal burrs dimensions. 4- Datum plane “H” coincident with the bottom of lead, where lead exits body. 5- Ref. POA MOTHER doc. 0037880 6- Creepage distance > 800 V 7- Creepage distance 250 V 8- Creepage distance as shown in the 664-1 CEI / IEC standard. 26/32 Max Doc ID 15028 Rev 3 VIPER28 Package mechanical data Figure 28. Package dimensions Doc ID 15028 Rev 3 27/32 Package mechanical data Table 11. VIPER28 SO16 narrow mechanical data mm Dim. Min. Typ. A 1.75 A1 0.1 A2 1.25 b 0.31 0.51 c 0.17 0.25 D 9.8 9.9 10 E 5.8 6 6.2 E1 3.8 3.9 4 e 0.25 1.27 h 0.25 0.5 L 0.4 1.27 k 0 8 ccc 28/32 Max. 0.1 Doc ID 15028 Rev 3 VIPER28 Package mechanical data Figure 29. SO16 narrow mechanical data SO-16 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.25 b 0.35 b1 0.19 a2 0.068 0.004 0.010 0.46 0.013 0.018 0.25 0.007 0.010 1.64 C MAX. 0.063 0.5 0.019 c1 45° (typ.) D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244 e 1.27 e3 8.89 F 3.8 G L M S 0.050 0.350 4.0 0.149 0.157 4.6 5.3 0.181 0.208 0.5 1.27 0.019 0.62 0.050 0.024 8° (max.) 0016020D Doc ID 15028 Rev 3 29/32 Package mechanical data Table 12. VIPER28 SDIP10 mechanical data mm Dim. Min. Typ. A 5.33 A1 0.38 A2 2.92 4.95 b 0.36 0.56 b2 0.51 1.15 c 0.2 0.36 D 9.02 10.16 E 7.62 8.26 E1 6.1 7.11 E2 7.62 E3 10.92 e L 1.77 2.92 Figure 30. SDIP10 mechanical drawing 30/32 Max. Doc ID 15028 Rev 3 3.81 VIPER28 9 Revision history Revision history Table 13. Document revision history Date Revision Changes 30-Sep-2008 1 Initial release 22-Jan-2009 2 Updated Figure 3 on page 4 21-Oct-2009 3 Added SO16N and SDIP10 packages Doc ID 15028 Rev 3 31/32 VIPER28 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 32/32 Doc ID 15028 Rev 3