bq2202 SRAM NV Controller With Reset Features General Description ä Power monitoring and switching for nonvolatile control of SRAMs ä Write-protect control ä Input decoder allows control of up to 2 banks of SRAM ä 3-volt primary cell input ä 3-volt rechargeable battery input/output ä Reset output for system power-on reset ä Les s t han 10ns chip e nable propagation delay ä 5% or 10% supply operation The CMOS bq2202 SRAM Nonvolatile Controller With Reset provides all the necessary functions for converting one or two banks of standard CMOS SRAM into nonvolatile read/write memory. A precision comparator monitors the 5V VCC input for an out-of-tolerance condition. When out-of-tolerance is de t e cte d , th e tw o co n d i ti o n e d chip-enable outputs are forced inactive to write-protect both banks of SRAM. Pin Connections Power for the external SRAMs is switched from the VCC supply to the battery-backup supply as VCC decays. On a subsequent power--up, the V OUT supply is automatically switched from the backup supply to the VCC supply. The external SRAMs are write-protected until a powervalid condition exists. The reset output provides power-fail and power-on resets for the system. During power-valid operation, the input decoder selects one of two banks of SRAM. Pin Names VOUT 1 16 VCC BCP 2 15 BCS NC 3 14 CE A 4 13 CECON1 NC 5 12 CECON2 NC 6 11 NC THS 7 10 RST VSS 8 9 NC VOUT RST THS CE CECON1, CECON2 A BCP BCS NC VCC VSS 16-Pin Narrow DIP or SOIC PN220201.eps Supply output Reset output Threshold select input Chip enable active low input Conditioned chip enable outputs Bank select input 3V backup supply input 3V rechargeable backup supply input/output No connect +5 volt supply input Ground Functional Description If THS is tied to VCC, power-fail detection occurs at 4.37V typical for 10% supply operation. The THS pin must be tied to VSS or VCC for proper operation. Two banks of CMOS static RAM can be battery-backed using the VOUT and conditioned chip-enable output pins from the bq2202. As the voltage input VCC slews down during a power failure, the two conditioned chip enable outputs, CE CON1 and CE CON2 , are forced inactive independent of the chip enable input CE. If a memory access is in process to any of the two external banks of SRAM during power-fail detection, that memory cycle continues to completion before the memory is write-protected. If the memory cycle is not terminated within time tWPT (150µsec maximum), the two chip enable outputs are unconditionally driven high, writeprotecting the controlled SRAMs. This activity unconditionally write-protects external SRAM as VCC falls to an out-of-tolerance threshold VPFD. VPFD is selected by the threshold select input pin, THS. If THS is tied to VSS, the power-fail detection occurs at 4.62V typical for 5% supply operation. Sept. 1997 D 1 bq2202 As the supply continues to fall past VPFD, an internal switching device forces VOUT to the internal backup energy source. CECON1 and CECON2 are held high by the VOUT energy source. The reset output (RST) goes active within tPFD (150µsec maximum) after VPFD, and remains active for a minimum of 40ms (120ms maximum) after power returns valid. The RST output can be used as the power-on reset for a microprocessor. Access to the external RAM may begin when RST returns inactive. During power-up, VOUT is switched back to the 5V supply as VCC rises above the backup cell input voltage sourcing VOUT. Outputs CECON1 and CECON2 are held inactive for time t CER (120ms maximum) after the power supply has reached VPFD, independent of the CE input, to allow for processor stabilization. Energy Cell Inputs—BCP, BCS Two backup energy source inputs are provided on the bq2202—a primary cell BCP and a secondary cell BCS. The primary cell input is designed to accept any 3V primary battery (non-rechargeable), typically some type of lithium chemistry. If a primary cell is not to be used, the BCP pin should be grounded. The secondary cell input BCS is designed to accept constant-voltage currentlimited rechargeable cells. During power-valid operation, the CE input is passed through to one of the two CECON outputs with a propagation delay of less than 10ns. The CE input is output on one of the two CECON output pins; depending on the level of bank select input A, as shown in the Truth Table. During normal 5V power valid operation, 3.3V is output on the BCS pin and is current-limited internally. Bank select input A is usually tied to a high-order address pin so that a large nonvolatile memory can be designed using lower-density memory devices. Nonvolatility and decoding are achieved by hardware hookup as shown in Figure 1. 5V VOUT VCC bq2202 From Address Decoder A CECON1 CE CECON2 BCP VCC VCC CMOS SRAM CMOS SRAM CE CE BCS THS RST To Microprocessor VSS FG220201.eps Figure 1. Hardware Hookup (5% Supply Operation) Sept. 1997 D 2 bq2202 If a secondary cell is not to be used, the BCS pin must be tied directly to VSS. If both inputs are used, during power failure the VOUT and CECON outputs are forced high by the secondary cell so long as it is greater than 2.5V. Only the secondary cell is loaded by the data retention current of the SRAM until the voltage at the BCS pin falls below 2.5V. When and if the voltage at BCS falls below 2.5V, an internal isolation switch automatically transfers the load from the secondary cell to the primary cell. VPFD VCC VSO To prevent battery drain when there is no valid data to retain, VOUT, CECON1, and CECON2 are internally isolated from BCP and BCS by either: ■ Initial connection of a battery to BCP or BCS or ■ Presentation of an isolation signal on CE. 0.5 VCC CE 700ns TD220201.eps A valid isolation signal requires CE low as VCC crosses both VPFD and VSO during a power-down. See Figure 2. Between these two points in time, CE must be brought to VCC ∗ (0.48 to 0.52) and held for at least 700ns. The isolation signal is invalid if CE exceeds VCC * 0.54 at any point between VCC crossing VPFD and VSO. Figure 2. Battery Isolation Signal The battery is connected to V OUT, CE CON1 , and CECON2 immediately on subsequent application and removal of VCC. Truth Table Input Output CE A CECON1 CECON2 H X H H L L L H L H H L Sept. 1997 D 3 bq2202 Absolute Maximum Ratings Value Unit VCC Symbol DC voltage applied on VCC relative to VSS Parameter -0.3 to +7.0 V VT DC voltage applied on any pin excluding VCC relative to VSS -0.3 to +7.0 V TOPR Operating temperature TSTG Conditions VT ≤ VCC + 0.3 0 to +70 °C Commercial -40 to +85 °C Industrial “N” Storage temperature -55 to +125 °C TBIAS Temperature under bias -40 to +85 °C TSOLDER Soldering temperature 260 °C IOUT VOUT current 200 mA Note: For 10 seconds Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability. Recommended DC Operating Conditions (TA = TOPR) Symbol VCC Parameter Supply voltage VBCP VBCS Backup cell input voltage Minimum Typical Maximum Unit 4.75 5.0 5.5 V THS = VSS 4.50 5.0 5.5 V THS = VCC 2.0 - 4.0 2.5 - 4.0 V VCC < VBC 0 0 0 V VSS Supply voltage VIL Input low voltage -0.3 - 0.8 V VIH Input high voltage 2.2 - VCC + 0.3 V THS Threshold select -0.3 - VCC + 0.3 V Note: Notes Typical values indicate operation at TA = 25°C, VCC = 5V or VBC. Sept. 1997 D 4 bq2202 DC Electrical Characteristics (TA = TOPR, VCC = 5V ± 10%) Symbol Parameter Minimum Typical Maximum Unit - - ±1 µA Conditions/Notes ILI Input leakage current VOH Output high voltage 2.4 - - V IOH = -2.0mA VOHB VOH, backup supply VBC - 0.3 - - V VBC > VCC, IOH = -10µA VOL Output low voltage - - 0.4 V IOL = 4.0mA ICC Operating supply current - 3 6 mA 4.55 4.62 4.75 V THS = VSS VPFD Power-fail detect voltage 4.30 4.37 4.50 V THS = VCC VSO Supply switch-over voltage - VBC - V ICCDR Data-retention mode current - - 100 nA VCC - 0.2 - - V VCC > VBC, IOUT = 100mA VOUT1 VOUT voltage VCC - 0.3 - - V VCC > VBC, IOUT = 160mA VOUT2 VOUT voltage VBC - 0.2 - - V VCC < VBC, IOUT = 100µA - VBCS - V VBCS > 2.5V VBC Active backup cell voltage - VBCP - V VBCS < 2.5V RBCS BCS charge output internal resistance 500 1000 1750 Ω VBCSO ≥ 3.0V VBCSO BCS charge output voltage 3.0 3.3 3.6 V VCC > VPFD, RST inactive, full charge or no load IOUT1 VOUT current - - 160 mA VOUT ≥ VCC - 0.3V IOUT2 VOUT current - 100 - µA VOUT ≥ VBC - 0.2V Note: VIN = VSS to VCC No load on VOUT, CECON1, and CECON2 No load on VOUT, CECON1, and CECON2 Typical values indicate operation at TA = 25°C, VCC = 5V or VBC. Capacitance (TA = 25°C, F = 1MHz, VCC = 5.0V) Minimum Typical Maximum Unit CIN Symbol Input capacitance - - 8 pF Input voltage = 0V COUT Output capacitance - - 10 pF Output voltage = 0V Note: Parameter This parameter is sampled and not 100% tested. Sept. 1997 D 5 Conditions bq2202 AC Test Conditions Parameter Test Conditions Input pulse levels 0V to 3.0V Input rise and fall times 5ns Input and output timing reference levels 1.5V (unless otherwise specified) 5V 960 CECON 510 100pF FG220102.eps Figure 3. Output Load Power-Fail Control (TA = TOPR) Min. Typ. Max. Unit tPF Symbol VCC slew 4.75 to 4.25V 300 - - µs tFS VCC slew 4.25 V to VSO 10 - - µs tPU VCC slew 4.25 to 4.75V 0 - - µs tCED Chip-enable propagation delay - 7 10 ns tCER Chip-enable recovery time tRR - tRR ms Time during which SRAM is writeprotected after VCC passes VPFD on power-up tRR VPFD to RST inactive 40 80 120 ms Time, after VCC becomes valid, before RST is cleared tAS Input A set up to CE 0 - - ns tWPT Write-protect time tR - tR µs Delay after VCC slews down past VPFD before SRAM is write-protected tR VPFD to RST active 40 100 150 µs Delay after VCC slews down past VPFD before RST is active Note: Parameter Conditions Typical values indicate operation at TA = 25°C, VCC = 5V. Sept. 1997 D 6 bq2202 Power-Down Timing tPF 4.75 VPFD tFS 4.25 VCC VSO CE tWPT VOHB CECON tR RST TD220202.eps Power-Up Timing tPU VCC 4.75 VPFD 4.25 VSO tCER CE CECON tCED VOHB tCED tRR RST TD220203.eps Address-Decode Timing A tAS CE tCED CECON1 tCED CECON2 TD220204.eps Sept. 1997 D 7 bq2202 16-Pin SOIC Narrow 16-Pin SOIC Narrow (SN) D e Dimension A A1 B C D E e H L B E H Minimum 0.060 0.004 0.013 0.007 0.385 0.150 0.045 0.225 0.015 Maximum 0.070 0.010 0.020 0.010 0.400 0.160 0.055 0.245 0.035 All dimensions are in inches. A C A1 .004 L 16-Pin DIP Narrow 16-Pin DIP Narrow (PN) Dimension A A1 B B1 C D E E1 e G L S Minimum 0.160 0.015 0.015 0.055 0.008 0.740 0.300 0.230 0.300 0.090 0.115 0.020 Maximum 0.180 0.040 0.022 0.065 0.013 0.770 0.325 0.280 0.370 0.110 0.150 0.040 All dimensions are in inches. Sept. 1997 D 8 bq2202 Data Sheet Revision History Change No. Page No. 1 2 Deleted last sentence Clarification 1 5 VBCSO—BCS charge output voltage Was: 3.15 min, 3.3 typ, 3.45 max Is: 3.0 min, 3.3 typ, 3.6 max 2 5 Changed maximum charge output internal resistance (RBCS) Was: 1500Ω Is: 1750Ω 3 1, 4, 5 10% supply operation Was: THS tied to VOUT Is: THS tied to VCC Note: Description Nature of Change Change 1 = Dec. 1992 B changes from Sept. 1991 A. Change 2 = Nov. 1994 C changes from Dec. 1992 B. Change 3 = Sept. 1997 D changes from Nov. 1994 C. Ordering Information bq2202 Temperature Range: blank = Commercial (0 to +70°C) N = Industrial (-40 to +85°C) Package Option: PN = 16-pin narrow plastic DIP SN = 16-pin narrow SOIC Device: bq2202 SRAM Nonvolatile Controller With Reset Sept. 1997 D 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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