SLUS581 − FEBRUARY 2004
FEATURES
D Power Monitoring and Switching for
D
D
D
D
D
D
D
DESCRIPTION
The CMOS bq2205 SRAM non-volatile controller
with reset provides all the necessary functions for
converting one or two banks of standard CMOS
SRAM into non-volatile read/write memory.
Non-Volatile Control of SRAMs
Input Decoder Allows Control of 1 or 2 Banks
of SRAM
Write-Protect Control
3-V Primary Cell Input
3.3-V Operation
Reset Output for System Power-On Reset
Less than 20-ns Chip Enable Propagation
Delay
Small 16-Lead TSSOP Package
A precision comparator monitors the 3.3-V VCC
input for an out-of-tolerance condition. When
out-of-tolerance is detected, the two conditioned
chip-enable outputs are forced inactive to
write-protect both banks of SRAM.
Power for the external SRAMs, VOUT, is switched
from the VCC supply to the battery-backup supply
as VCC decays. On a subsequent power-up, the
VOUT supply is automatically switched from the
backup supply to the VCC supply. The external
SRAMs are write-protected until a power-valid
condition exists. The reset output provides
power-fail and power-on resets for the system.
During power-valid operation, the input decoder, A,
selects one of two banks of SRAM.
APPLICATIONS
D NVSRAM Modules
D Point-of-Sale Systems
D Facsimile, Printers and Photocopiers
D Internet Appliances
D Servers
D Medical Instrumentation and Industrial
Products
Main Supply
From Address
Selector
VCC
bq2205LYPW
VCC
VDC
12 VCC
BW
GND
1
RST 16
Backup Supply
A
11 CE
VDC
9 BCP
GND
4
VSS
5
VSS
8
VSS
15
To Microprocessor
VCC
VOUT 13
CECON1 10
VCC
VCC
CE
CE
SRAM Bank 1
Pushbutton
Reset
(Optional)
SRAM Bank 2
CECON2 14
UDG−03129
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
!"#$%! & '("")% $& ! *(+'$%! ,$%)
"!,('%& '!!"# %! &*)''$%!& *)" %-) %)"#& ! ).$& &%"(#)%&
&%$,$", /$""$%0 "!,('%! *"!')&&1 ,!)& !% )')&&$"+0 '+(,)
%)&%1 ! $++ *$"$#)%)"&
Copyright 2004, Texas Instruments Incorporated
www.ti.com
1
SLUS581 − FEBRUARY 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
−20°C to 70°C
OPERATION
PART NUMBER(1)
SYMBOL
3.3 V
bq2205LYPW
bq2205LY
(1) The PW package is available taped and reeled. Add an R suffix to the device type (i.e. bq2205LYPWR) to order quantities of 2,000 devices
per reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(2)
bq2205LY
Input voltage range
VCC, (wrt VSS)
BCP, (wrt VSS)
all other pins, (wrt VSS)
UNIT
−0.3 to 6.0
−0.3 to 4.5
V
−0.3 to VCC + 0.3
Operating temperature range, TA
−20 to 70
Storage temperature, Tstg
−55 to 125
Temperature under bias, TJbias
−40 to 85
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
300
(2) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions”
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
Supply voltage, VCC
Supply voltage from backup cell, VBC
2
MAX
3.0
3.6
2.0
4.0
Low-level input voltage, VIL
−0.3
0.8
High-level input voltage, VIH
2.2
VCC + 0.3
0.4
RST low-level input voltage, VIL
−0.3
RST high-level input voltage, VIH
2.2
Operating temperature range, TA
−20
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VCC + 0.3
70
UNIT
V
°C
SLUS581 − FEBRUARY 2004
ELECTRICAL CHARACTERISTICS
(TA = 25°C, VCC(min) ≤ VCC ≤ VCC(max) unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC supply current, ICC(vcc)
VCC > VCC(MIN)
CE = low
CECONX = 0 mA
Backup Battery Supply Current, ICC(BC)
VBC > VBC(MIN), VCC = 0 V
CE = low
CECONX = 0 mA
Output voltage (VOUT)
I(VOUT) = 80 mA, VCC > V(SO)
I(VOUT)= 100µ A, VCC < V(SO)
Power fail detect voltage, VPFD
MIN
TYP
MAX
UNIT
210
500
µA
50
150
nA
2.9
2.95
Vcc−0.3
VBC−0.3
2.85
Supply switch-over voltage, VSO
VBC > V(PFD)
VBC < V(PFD)
RST output voltage
I(RST) = 1 mA
0.4
BW output voltage
I(BW)= 1 mA
0.4
Input leakage current on A and CE pins
VPFD
VBC
−1
1
Voh CEcon1,2
Ioh = 0.5 mA
2.4
Vol CEcon1,2
Iol = 2.0 mA
(1)
0.4
Battery warning level VBW
V
µA
V
0.677xVCC
Capacitance
Output capacitance
VOUT = 0 V
7
Input capacitance
VOUT = 0 V
5
pF
Power-Down and Power-Up Timing, Refer to Figure 1 through 3
VCC slew rate fall time, tF
3.0 V to 0.0 V
300
VCC slew rate rise time, tR
VSO to VPFD(max)
100
VPFD to RST active, tRST
(reset active timeout period)
Chip-enable recovery time, tCER
µss
30
85
30
85
ms
(2)
Chip-enable propagation delay time to external
See Figure 2
15
25
ns
SRAM, tCED
Push-button low time, tPBL
RST pin
1
µs
(1) Battery warning level is detected on power up and the BW pin is latched at tCER time after VCC passes through VPFD on power up.
(2) Time during which external SRAM is write protected after VCC passes through VPFD on power up.
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3
SLUS581 − FEBRUARY 2004
AC TEST CONDITIONS, INPUT PULSE LEVELS 0 V ≤ VIN ≤ 3 V, tR = tF = 5 NS
TTL
CECONX
CL
(including scope
and JIG)
Figure 1. Output Load
tF
tR
VCC
VPFD(max)
VPFD
VCC
VPFD
VSO
VSO
tCED
tCER
tCED
CE
CECONX
tRST
RST
Figure 2. Power-Down/Power-Up Timing Diagram
tPBL
RST
tRST
VPBRH
VPBRL
Figure 3. Push-Button Reset Timing
4
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SLUS581 − FEBRUARY 2004
TERMINAL FUNCTIONS
TERMINAL
NAME
A
bq2205LY
1
I/O
DESCRIPTION
I
SRAM bank select input
BCP
9
I
Backup supply input
BW
15
O
Battery warning output (open-drain)
CE
11
I
Chip enable input (active low)
CECON1
CECON2
10
O
Conditioned chip enable output 1
14
O
Conditioned chip enable output 2
N/C
2, 3, 6, 7
−
No connect. These pins must be left floating.
RST
16
O
Power-up reset to system CPU output (open-drain)
VCC
VOUT
12
I
Main supply input
13
O
SRAM supply output
4, 5, 8
−
Ground input
VSS
PW PACKAGE
(TOP VIEW)
A
N/C
N/C
VSS
VSS
N/C
N/C
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RST
BW
CECON2
VOUT
VCC
CE
CECON1
BCP
N/C no connection
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5
SLUS581 − FEBRUARY 2004
FUNCTIONAL DESCRIPTION
Two banks of CMOS static RAM can be battery-backed using the VOUT and conditioned chip-enable output
pins from the bq2205. As the voltage input VCC slews down during a power failure, the two-conditioned chip
enable outputs, CECON1 and CECON2, are forced inactive independent of the chip enable input, CE. This activity
unconditionally write-protects the external SRAM as VCC falls to an out-of-tolerance threshold VPFD. As the
supply continues to fall past VPFD, an internal switching device forces VOUT to the backup energy source.
CECON1 and CECON2 are held high by the VOUT energy source.
During power-up, VOUT is switched back to the 3.3-V supply as VCC rises above the backup cell input voltage
sourcing VOUT. Outputs CECON1 and CECON2 are held inactive for time tCER after the power supply has reached
VPFD, independent of the CE input, to allow for processor stabilization.
During power-valid operation, the CE input is passed through to one of the two CECONx outputs with a
propagation delay of less than tCED. The CE input is output on one of the two CECONx output pins; depending
on the level of bank select input A. See truth table below.
Table 1. Truth Table
INPUT
CE
OUTPUT
A
H
x
CECON1
H
CECON2
H
L
L
L
H
L
H
H
L
Bank select input A is usually tied to a high-order address pin so that a large nonvolatile memory can be
designed using lower-density memory devices. Non-volatility and decoding are achieved by hardware hookup
as shown in the application diagram.
The RST output can be used as the power-on reset for a microprocessor. Access to the external RAM may begin
when RST returns inactive.
BATTERY BACKUP INPUT
Backup energy source, BCP, input is provided on the bq2205 for use with an external primary cell. The primary
cell input is designed to accept any 3-V primary battery (non-rechargeable), typically some type of lithium
chemistry.
Power-Down and Power-Up Cycle
The bq2205 continuously monitors VCC for out-of-tolerance. During a power failure, when VCC falls below
VPFD, the bq2205 write-protects the external SRAM. The power source is switched to BCP when VCC is less
than VPFD and BCP is greater than VPFD, or when VCC is less than BCP and BCP is less than VPFD. When VCC
is above VPFD, the power source is VCC. Write-protection continues for tCER time after VCC rises above VPFD.
An external CMOS static RAM is battery-backed using the VOUT and chip enable output pins from the bq2205.
As the voltage input VCC slews down during a power failure, the chip enable output, CECONx, is forced inactive
independent of the chip enable input CE.
As the supply continues to fall past VPFD, an internal switching device forces VOUT to the external backup
energy source. CECONx is held high by the VOUT energy source.
6
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SLUS581 − FEBRUARY 2004
FUNCTIONAL DESCRIPTION
During power up, VOUT is switched back to the main supply as VCC rises above the backup cell input voltage
sourcing VOUT. If VPFD < BCP on the bq2205 the switch to the main supply occurs at VPFD. CECONx is held
inactive for time tCER after the power supply has reached VPFD, independent of the CE input, to allow for
processor stabilization.
Power-On Reset
The bq2205 provides a power-on reset, which pulls the RST pin low on power down and remains low on power
up for tRST after VCC passes VPFD. With valid battery voltage on BCP, RST remains valid for VCC = VSS. The
pull-up resistor on this pin should not exceed 10 kΩ if a push button reset is used.
Battery Low Warning
The bq2205 checks the battery voltage on power-up. The threshold for the battery warning comparator is VBW,
and a low level is sensed after power valid on each power up and latched after tCER time. The latched value
is presented at BW pin where a low indicates a low battery.
APPLICATION INFORMATION
PCB LAYOUT INFORMATION
It is important to pay special attention to the PCB layout. The following provides some guidelines:
D To obtain optimal performance, the decoupling capacitor from input terminals to VSS should be placed as
close as possible to the bq2205, with short trace runs to both signal and VSS pins.
D All low-current VSS connections should be kept separate from the high-current paths from the inputs
supplies. Use a single-point ground technique incorporating both the small signal ground path and the
power ground path.
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7
SLUS581 − FEBRUARY 2004
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°−ā 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
8
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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