TI SN65LVDS301ZQE

SN65LVDS301
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SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006
PROGRAMMABLE 27-BIT DISPLAY SERIAL INTERFACE TRANSMITTER
FEATURES
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FlatLink™3G serial interface technology
Compatible with FlatLink3G receivers such as
SN65LVDS302
Input supports 24-bit RGB video mode
interface
24-Bit RGB Data, 3 Control Bits, 1 Parity Bit
and 2 Reserved Bits Transmitted over 1, 2 or 3
Differential Lines
SubLVDS Differential Voltage Levels
Effective Data Throughput up to 1755 Mbps
Three Operating Modes to Conserve Power
– Active-Mode QVGA 17.4 mW (typ)
– Active-Mode VGA 28.8 mW (typ)
– Shutdown Mode ≈ 0.5 µA (typ)
– Standby Mode ≈ 0.5 µA (typ)
Bus Swap for Increased PCB Layout
Flexibility
1.8-V Supply Voltage
ESD Rating > 2 kV (HBM)
Typical Application: Host-Controller to
Display-Module Interface
Pixel Clock Range of 4 MHz–65 MHz
Failsafe on all CMOS Inputs
Packaging: 80 Pin 5mm × 5mm µBGA®
Very low EMI meets SAE J1752/3 'M'-spec
DESCRIPTION
The SN65LVDS301 serializer device converts 27
parallel data inputs to 1, 2, or 3 Sub Low-Voltage
Differential Signaling (SubLVDS) serial outputs. It
loads a shift register with 24 pixel bits and 3 control
bits from the parallel CMOS input interface. In
addition to the 27 data bits, the device adds a parity
bit and two reserved bits into a 30-bit data word.
Each word is latched into the device by the pixel
clock (PCLK). The parity bit (odd parity) allows a
receiver to detect single bit errors. The serial shift
register is uploaded at 30, 15, or 10 times the
pixel-clock data rate depending on the number of
serial links used. A copy of the pixel clock is output
on a separate differential output.
FPC
cabling
typically
interconnects
the
SN65LVDS301 with the display. Compared to
parallel signaling, the LVDS301 outputs significantly
reduce the EMI of the interconnect by over 20 dB.
The electromagnetic emission of the device itself is
very low and meets the meets SAE J1752/3
'M'-spec. (see Figure 37)
The SN65LVDS301 supports three power modes
(Shutdown, Standby and Active) to conserve power.
When transmitting, the PLL locks to the incoming
pixel clock PCLK and generates an internal
high-speed clock at the line rate of the data lines.
The parallel data are latched on the rising or falling
edge of PCLK as selected by the external control
signal CPOL. The serialized data is presented on the
serial outputs D0, D1, D2 with a recreated PCLK
generated from the internal high-speed clock, output
on the CLK output. If PCLK stops, the device enters
a standby mode to conserve power
The parallel (CMOS) input bus offers a bus-swap
feature. The SWAP pin configures the input order of
the pixel data to be either R[7:0]. G[7:0], B[7:0], VS,
HS, DE or B[0:7]. G[0:7], R[0:7], VS, HS, DE. This
gives a PCB designer the flexibility to better match
the bus to the host controller pinout or to put the
transmitter device on the top side or the bottom side
of the PCB.
Flatlinkä3G
LCD
Driver
LVDS302
CLK
DATA
LVDS301
1
2
3
4
5
6
7
8
9
*
0
#
Application
Processor
with
RGB
Video
Interface
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments.
µBGA is a registered trademark of Tessera, Inc..
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
SN65LVDS301
www.ti.com
SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
Two Link Select lines LS0 and LS1 control whether 1, 2 or 3 serial links are used. The TXEN input may be used
to put the SN65LVDS301 in a shutdown mode. The SN65LVDS301 enters an active Standby mode if the input
clock PCLK stops. This minimizes power consumption without the need for controlling an external pin. The
SN65LVDS301 is characterized for operation over ambient air temperatures of –40°C to 85°C. All CMOS inputs
offer failsafe features to protect them from damage during power-up and to avoid current flow into the device
inputs during power-up. An input voltage of up to 2.165 V can be applied to all CMOS inputs while VDD is
between 0V and 1.65V.
Functional Block Diagram
Parity
Calc
D0+
SWAP
Bit29
Bit28=0
1
Bit27=0
0
R[0:7]
G[0:7]
B[0:7]
8
[0..26]
8
8
HS
VS
3x10, 2x15, or 1x30−bit parallel to serial conversion
SubLVDS
D0−
D1+
SubLVDS
D1−
D2+
SubLVDS
D2−
CLK+
SubLVDS
DE
CLK−
PCLK
0
1
CPOL
iPCLK
x10, x15, or x30
x1
PLL
multiplier
LS0
Control /
LS1
TXEN
2
Glitch
supression
standby Monitor
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SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006
PINOUT - TOP VIEW
SWAP PIN FUNCTIONALITY
The SWAP pin allows the pcb designer to reverse the RGB bus to minimize potential signal crossovers in the
PCB routing. The two drawings beneath show the RGB signal pin assignment based on the SWAP-pin setting.
1
2
3
4
5
6
7
8
G6
R0
R2
R4
R6
9
A
1
2
3
4
5
6
7
8
9
A
G2
G4
B
G5
G3
G1
B7
B5
B3
B1
G7
G6
G4
G2
G0
B6
B4
B2
R1
R0
B
G0
G1
G3
G5
G7
R1
R3
R5
R7
C
B0
C
B6
B7
SN65LVDS301
D
B4
D
B5
R3
Top View
E
B3
R2
E
Top View
R4
F
SN65LVDS301
F
B1
B2
G
R6
R5
PCLK
R7
HS
VS
G
PCLK
B0
H
H
HS
VS
J
J
DE
SWAP
DE
1.8V
SWAP=0
Figure 1. SWAP PIN = 0
SWAP=1
SWAP
Figure 2. SWAP PIN = 1
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SN65LVDS301
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SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006
Table 1. NUMERIC PIN LIST
PIN
SWAP
SIGNAL
A1
—
GND
0
G2
1
G5
0
G4
1
G3
C3
F3
—
VDD
0
G6
C4
—
VDD
F4
—
GND
1
G1
C5
—
GND
F5
—
GND
0
R0
C6
—
VDD
F6
—
GND
1
B7
C7
—
VDD
F7
—
GND
0
R2
C8
—
GND
F8
—
VDDPLLD
1
B5
C9
—
LS0
F9
—
D1+
0
R4
0
B4
G1
—
PCLK
1
B3
1
R3
0
R6
0
B5
1
B1
1
R2
G3
—
VDD
—
GND
D3
—
VDD
G4
—
GND
0
G0
D4
—
GND
G5
—
GND
1
G7
D5
—
GND
G6
—
GND
0
G1
D6
—
GND
G7
—
GND
1
G6
D7
—
GND
G8
—
GNDLVDS
0
G3
D8
—
LS1
G9
—
D1–
1
G4
D9
—
D2+
H1
—
HS
0
G5
0
B3
H2
—
VS
1
G2
1
R4
H3
—
GND
0
G7
E2
—
GND
H4
—
GNDLVDS
1
G0
E3
—
VDD
H5
—
VDDLVDS
0
R1
E4
—
GND
H6
—
GNDPLLA
1
B6
E5
—
GND
H7
—
VDDPLLA
0
R3
E6
—
GND
H8
—
VDDLVDS
1
B4
E7
—
GND
H9
—
CPOL
0
R5
E8
—
GNDPLLD
J1
—
GND
1
B2
E9
—
D2–
J2
—
DE
0
R7
J3
—
TXEN
1
B0
J4
—
D0–
J5
—
D0+
J6
—
CLK–
J7
—
CLK+
J8
—
SWAP
J9
—
GNDLVDS
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
4
PIN
C1
C2
D1
D2
E1
SWAP .
SIGNAL
0
B6
1
R1
0
B7
1
R0
UNPOPULATED
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PIN
F1
F2
G2
SWAP
SIGNAL
0
B1
1
R6
0
B2
1
R5
0
B0
1
R7
SN65LVDS301
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SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006
TERMINAL FUNCTIONS
NAME
I/O
DESCRIPTION
D0+, D0–
SubLVDS Data Link (active during normal operation)
D1+, D1–
SubLVDS Data Link (active during normal operation when LS0 = high and LS1 = low, or
LS0 = low and LS1=high; high impedance if LS0 = LS1 = low)
SubLVDS Out
D2+, D2–
SubLVDS Data Link (active during normal operation when LS0 = low and LS1 = high,
high-impedance when LS1 = low)
CLK+, CLK–
SubLVDS output Clock; clock polarity is fixed
R0–R7
Red Pixel Data (8); pin assignment depends on SWAP pin setting
G0–G7
Green Pixel Data (8); pin assignment depends on SWAP pin setting
B0–B7
Blue Pixel Data (8); pin assignment depends on SWAP pin setting
HS
Horizontal Sync
VS
Vertical Sync
DE
Data Enable
PCLK
LS0, LS1
Input Pixel Clock; rising or falling clock polarity is selected by control input CPOL
CMOS IN
Link Select (Determines active SubLVDS Data Links and PLL Range) See Table 2
Disables the CMOS Drivers and Turns Off the PLL, putting device in shutdown mode
1 – Transmitter enabled
0 – Transmitter disabled
(Shutdown)
TXEN
Note: The TXEN input incorporates glitch-suppression logic to avoid device malfunction
on short input spikes. It is necessary to pull TXEN high for longer than 10 µs to enable
the transmitter. It is necessary to pull the TXEN input low for longer than 10 µs to
disable the transmitter. At power up, the transmitter is enabled immediately if TXEN = 1
and disabled if TXEN = 0
Input Clock Polarity Selection
CPOL
SWAP
CMOS In
CMOS In
0 – rising edge clocking
1 – falling edge clocking
Bus Swap swaps the bus pins to allow device placement on top or bottom of pcb. See
pinout drawing for pin assignments.
0 – data input from B0...R7
1 – data input from R7...B0
VDD
Supply Voltage
GND
Supply Ground
VDDLVDS
SubLVDS I/O supply Voltage
GNDLVDS
VDDPLLA
Power Supply (1)
SubLVDS Ground
PLL analog supply Voltage
GNDPLLA
PLL analog GND
VDDPLLD
PLL digital supply Voltage
GNDPLLD
PLL digital GND
(1)
For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all ground terminals
directly to this plane.
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SN65LVDS301
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FUNCTIONAL DESCRIPTION
Serialization Modes
The SN65LVDS301 transmitter has three modes of operation controlled by link-select pins LS0 and LS1.
Table 2 shows the serializer modes of operation.
Table 2. Logic Table: Link Select Operating Modes
LS1
LS0
0
0
1ChM
1-channel mode (30-bit serialization rate)
Mode of Operation
D0 active;
D1, D2 high-impedance
Data Links Status
0
1
2ChM
2-channel mode (15-bit serialization rate)
D0, D1 active;
D2 high-impedance
1
0
3ChM
3-channel mode (10-bit serialization rate)
D0, D1, D2 active
1
1
Reserved
Reserved
1-Channel Mode
While LS0 and LS1 are held low, the SN65LVDS301 transmits payload data over a single SubLVDS data pair,
D0. The PLL locks to PCLK and internally multiplies the clock by a factor of 30. The internal high-speed clock is
used to serialize (shift out) the data payload on D0. Two reserved bits and the parity bit are added to the data
frame. Figure 3 illustrates the timing and the mapping of the data payload into the 30-bit frame. The internal
high-speed clock is divided by a factor of 30 to recreate the pixel clock, and presented on the SubLVDS CLK
output. While in this mode, the PLL can lock to a clock that is in the range of 4 MHz through 15 MHz. This mode
is intended for smaller video display formats (e.g. QVGA to HVGA) that do not require the full bandwidth
capabilities of the SN65LVDS301.
CLK–
CLK+
D0 +/– CHANNEL
0 CP R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 VS HS DE 0
0
0 CP R7 R6
Figure 3. Data and Clock Output in 1-Channel Mode (LS0 and LS1 = low).
2-Channel Mode
While LS0 is held high and LS1 is held low, the SN65LVDS301 transmits payload data over two SubLVDS data
pairs, D0 and D1. The PLL locks to PCLK and internally multiplies it by a factor of 15. The internal high-speed
clock is used to serialize the data payload on D0, and D1. Two reserved bits and the parity bit are added to the
data frame. Figure 4 illustrates the timing and the mapping of the data payload into the 30-bit frame and how the
frame becomes split into the two output channels. The internal high-speed clock is divided by 15 to recreate the
pixel clock, and presented on SubLVDS CLK. The PLL can lock to a clock that is in the range of 8 MHz through
30 MHz in this mode. Typical applications for using the 2-channel mode are HVGA and VGA displays.
CLK–
CLK +
D0 +/– Channel CP R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 VS 0 CP R7 R6
D1 +/– Channel
0 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 HS DE 0 G3 G2
Figure 4. Data and Clock Output in 2-Channel Mode (LS0 = high; LS1 = low).
6
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3-Channel Mode
While LS0 is held low and LS1 is held high, the SN65LVDS301 transmits payload data over three SubLVDS
data pairs D0, D1, and D2. The PLL locks to PCLK, and internally multiplies it by 10. The internal high-speed
clock is used to serialize the data payload on D0, D1, and D2. Two reserved bits and the parity bit are added to
the data frame. Figure 5 illustrates the timing and the mapping of the data payload into the 30-bit frame and how
the frame becomes split over the three output channels. The internal high speed clock is divided back down by a
factor of 10 to recreate the pixel clock and presented on SubLVDS CLK output. While in this mode, the PLL can
lock to a clock in the range of 20 MHz through 65 MHz. The 3-channel mode supports applications with very
large display resolutions such as VGA or XGA.
CLK CLK +
D0 +/- CHANNEL CP R7 R6 R5 R4 R3 R2 R1 R0 VS CP R7 R6
D1 +/- CHANNEL
0 G7 G6 G5 G4 G3 G2 G1 G0 HS 0 G7 G6
D2 +/- CHANNEL
0 B7 B6 B5 B4 B3 B2 B1 B0 DE 0 B7 B6
Figure 5. Data and Clock Output in 3-Channel Mode (LS0 = low; LS1 = high).
Powerdown Modes
The SN65LVDS301 Transmitter has two powerdown modes to facilitate efficient power management.
Shutdown Mode
The SN65LVDS301 enters Shutdown mode when the TXEN pin is asserted low. This turns off all transmitter
circuitry, including the CMOS input, PLL, serializer, and SubLVDS transmitter output stage. All outputs are
high-impedance. Current consumption in Shutdown mode is nearly zero.
Standby Mode
The SN65LVDS301 enters the Standby mode if TXEN is high and the PCLK input signal frequency is less than
500kHz. All circuitry except the PCLK input monitor is shut down, and all outputs enter high-impedance mode.
The current consumption in Standby mode is very low. When the PCLK input signal is completely stopped, the
IDD current consumption is less than 10 µA. The PCLK input must not be left floating.
NOTE:
A floating (left open) CMOS input allows leakage currents to flow from VDD to GND.
To prevent large leakage current, a CMOS gate must be kept at a valid logic level,
either VIH or VIL. This can be achieved by applying an external voltage of VIH or VIL to
all SN65LVDS301 inputs.
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Active Modes
When TXEN is high and the PCLK input clock signal is faster than 3 MHz, the SN65LVDS301 enters Active
mode. Current consumption in Active mode depends on operating frequency and the number of data transitions
in the data payload.
Acquire Mode (PLL approaches lock)
The PLL is enabled and attempts to lock to the input Clock. All outputs remain in high-impedance mode. When
the PLL monitor detects stable PLL operation, the device switches from Acquire to Transmit mode. For proper
device operation, the pixel clock frequency must fall within the valid fPCLK range specified under recommended
operating conditions. If the pixel clock frequency is larger than 3 MHz but smaller than fPCLK(min), the
SN65LVDS301 PLL is enabled. Under such conditions, it is possible for the PLL to lock temporarily to the pixel
clock, causing the PLL monitor to release the device into transmit mode. If this happens, the PLL may or may
not be properly locked to the pixel clock input, potentially causing data errors, frequency oscillation, and PLL
deadlock (loss of VCO oscillation).
Transmit Mode
After the PLL achieves lock, the device enters the normal transmit mode. The CLK pin outputs a copy of PCLK.
Based on the selected mode of operation, the D0, D1, and D2 outputs carry the serialized data. In 1-channel
mode, outputs D1 and D2 remain high-impedance. In the 2-channel mode, output D2 remains high-impedance.
Parity Bit Generation
The SN65LVDS301 transmitter calculates the parity of the transmit data word and sets the parity bit accordingly.
The parity bit covers the 27 bit data payload consisting of 24 bits of pixel data plus VS, HS and DE. The two
reserved bits are not included in the parity generation. ODD Parity bit signaling is used. The transmitter sets the
Parity bit if the sum of the 27 data bits result in an even number of ones. The Parity bit is cleared otherwise. This
allows the receiver to verify Parity and detect single bit errors.
Status Detect and Operating Modes Flow diagram
The SN65LVDS301 switches between the power saving and active modes in the following way:
Power Up
TXEN = 0
Power Up
TXEN = 1
CLK Inactive
TXEN Low
> 10 ms
Shutdown
Mode
TXEN High > 10 ms
TXEN Low
> 10 ms
TXEN Low
> 10 ms
Transmit
Mode
Standby
Mode
PCLK
Stops or Lost
PCLK
Stops or Lost
PCLK
Active
PLL Achieved Lock
Power Up
TXEN = 1
CLK Active
Acquire
Mode
Figure 6. Status Detect and Operating Modes Flow Diagram
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Table 3. Status Detect and Operating Modes Descriptions
Mode
Characteristics
consumption (1)
Conditions
Shutdown Mode
Least amount of power
off); All outputs are high-impedance
Standby Mode
Low power consumption (only clock activity circuit active; PLL TXEN is high; PCLK input signal is missing or
is disabled to conserve power); All outputs are
inactive (2)
high-impedance
Acquire Mode
PLL tries to achieve lock; All outputs are high-impedance
TXEN is high; PCLK input monitor detected input
activity
Transmit Mode
Data transfer (normal operation); Transmitter serializes data
and transmits data on serial output; unused outputs remain
high-impedance
TXEN is high and PLL is locked to incoming clock
(1)
(2)
(most circuitry turned
TXEN is
low (1) (2)
In Shutdown Mode, all SN65LVDS301 internal switching circuits (e.g., PLL, serializer, etc.) are turned off to minimize power
consumption. The input stage of any input pin remains active.
Leaving inputs unconnected can cause random noise to toggle the input stage and potentially harm the device. All inputs must be tied to
a valid logic level VIL or VIH during Shutdown or Standby Mode.
Operating Mode Transitions
MODE TRANSITION
Shutdown → Standby
USE CASE
TRANSITION SPECIFICS
Drive TXEN high to enable
transmitter
1. TXEN high > 10 µs
2. Transmitter enters standby mode
a. All outputs are high-impedance
b. Transmitter turns on clock input monitor
Standby → Acquire
Transmitter activity detected
1. PCLK input monitor detects clock input activity;
2. Outputs remain high-impedance;
3. PLL circuit is enabled
Acquire → Transmit
Link is ready to transfer data
1. PLL is active and approaches lock
2. PLL achieved lock within 2 ms
3. Parallel Data input latches into shift register
4. CLK output turns on
5. selected Data outputs turn on and send out first serial data bit
Transmit → Standby
Request Transmitter to enter
Standby mode by stopping
PCLK
1. PCLK Input monitor detects missing PCLK
2. Transmitter indicates standby, putting all outputs into high-impedance;
3. PLL shuts down;
4. PCLK activity input monitor remains active
Transmit/Standby →
Shutdown
Turn off Transmitter
1. TXEN pulled low for longer than 10us
2. Transmitter indicates standby, putting output CLK+ and CLK– into
high-impedance state;
3. Transmitter puts all other outputs into high-impedance state
4. Most IC circuitry is shut down for least power consumption
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SN65LVDS301
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ORDERING INFORMATION
PART NUMBER
PACKAGE
SN65LVDS301ZQE
SHIPPING METHOD
Tray
ZQE
SN65LVDS301ZQER
Reel
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
Supply voltage range, VDD (2), VDDPLLA, VDDPLLD, VDDLVDS
-0.3 to 2.175
V
Voltage range at any input When VDDx > 0 V
or output terminal
When VDDx≤ 0 V
-0.5 to 2.175
V
-0.5 to VDD + 2.175
V
±3
kV
±500
V
Human Body Model (3) (all Pins)
Electrostatic discharge
Charged-Device Mode (4)l (all Pins)
Machine
Model (5)
±200
(all pins)
Continuous power dissipation
(1)
(2)
(3)
(4)
(5)
See Dissipation Rating Table
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the GND terminals.
In accordance with JEDEC Standard 22, Test Method A114-A.
In accordance with JEDEC Standard 22, Test Method C101.
In accordance with JEDEC Standard 22, Test Method A115-A
DISSIPATION RATINGS
(1)
(2)
PACKAGE
CIRCUIT
BOARD MODEL
TA < 25°C
DERATING FACTOR (1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
ZQE
Low-K (2)
592 mW
7.407 mW/°C
148 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
In accordance with the Low-K thermal metric definitions of EIA/JESD51-2.
THERMAL CHARACTERISTICS
PARAMETER
PD
10
TEST CONDITIONS
Typical
VDDx = 1.8 V, TA = 25°C
Maximum
VDDx = 1.95 V, TA = –40°C
Device Power Dissipation
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VALUE
PCLK at 4 MHz
14.4
PCLK at 65 MHz
44.5
PCLK at 4 MHz
22.3
PCLK=65 MHz
71.8
UNIT
mW
mW
SN65LVDS301
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SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006
RECOMMENDED OPERATING CONDITIONS
VDD
VDDPLLA
VDDPLLD
VDDLVDS
(1)
Supply voltages
VDDn(PP)
MIN
NOM
MAX
UNIT
1.65
1.8
1.95
V
Test set-up see Figure 12
Supply voltage noise
magnitude 50 MHz (all
supplies)
f(PCLK) ≤ 50 MHz; f(noise) = 1 Hz to 2 GHz
100
f(PCLK) > 50 MHz; f(noise) = 1 Hz to 1 MHz
100
f(PCLK) > 50 MHz; f(noise) > 1 MHz
fPCLK
Pixel clock frequency
mV
40
1-Channel transmit mode, see Figure 3
4
15
2-Channel transmit mode, see Figure 4
8
30
3-Channel transmit mode, see Figure 5
20
65
Frequency threshold Standby mode to active
mode (2), see Figure 16
0.5
3
MHz
tH x fPCLK
PCLK input duty cycle
0.33
0.67
TA
Operating free-air
temperature
–40
85
°C
tjit(per)PCLK
PCLK RMS period jitter (3)
5
ps-rms
tjit(TJ)PCLK
PCLK total jitter
tjit(CC)PCLK
PCLK peak
cycle-to-cycle jitter (4)
Measured on PCLK input
0.05/fPCLK
s
0.02/fPCLK
s
VDD
V
PCLK, R[0:7], G[0:7], B[0:7], VS, HS, DE, PCLK, LS[1:0], CPOL, TXEN, SWAP
VIH
High-level input voltage
VIL
Low-level input voltage
tDS
Data set up time prior to
PCLK transition
tDH
Data hold time after PCLK
transition
(1)
(2)
(3)
(4)
0.7×VDD
0.3×VDD
f (PCLK) = 65 MHz; see Figure 8
V
2.0
ns
2.0
ns
Unused single-ended inputs must be held high or low to prevent them from floating.
PCLK input frequencies lower than 500 kHz force the SN65LVDS301into standby mode. Input frequencies between 500 kHz and 3 MHz
may or may not activate the SN65LVDS301. Input frequencies beyond 3 MHz activate the SN65LVDS301.
Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 100,000 cycles.
Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles; over a random sample of 1,000 adjacent cycle
pairs.
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DEVICE ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAM
ETER
TEST CONDITIONS
1ChM
2ChM
IDD
3ChM
TYP (1)
MAX
VDD =VDDPLLA=VDDPLLD=VDDLVDS,
RL(PCLK)=RL(D0)=100 Ω, VIH=VDD, VIL=0 V,
TXEN at VDD,
alternating 1010 serial bit pattern
fPCLK = 4 MHz
9.0
11.4
fPCLK = 6 MHz
10.6
12.6
fPCLK = 15 MHz
16
18.8
VDD =VDDPLLA=VDDPLLD=VDDLVDS,
RL(PCLK)=RL(D0)=100 Ω, VIH=VDD, VIL=0 V,
TXEN at VDD,
typical power test pattern (see Table 5)
fPCLK = 4 MHz
8.0
fPCLK = 6 MHz
8.9
fPCLK = 15 MHz
14.0
VDD =VDDPLLA=VDDPLLD=VDDLVDS,
RL(PCLK)=RL(D0)=100 Ω, VIH=VDD, VIL=0 V,
TXEN at VDD,
alternating 1010 serial bit pattern;
fPCLK = 8 MHz
13.7
15.9
fPCLK = 22 MHz
18.4
22.0
fPCLK = 30 MHz
21.4
25.8
VDD =VDDPLLA=VDDPLLD=VDDLVDS,
RL(PCLK)=RL(D0)=100 Ω, VIH=VDD, VIL=0 V,
TXEN at VDD,
typical power test pattern (see Table 6)
fPCLK = 8 MHz
11.5
fPCLK = 22 MHz
16.0
fPCLK = 30 MHz
19.1
VDD =VDDPLLA=VDDPLLD=VDDLVDS,
RL(PCLK)=RL(D0)=100 Ω, VIH=VDD, VIL=0 V,
TXEN at VDD,
alternating 1010 serial bit pattern
fPCLK = 20 MHz
20.0
22.5
29.1
36.8
VDD =VDDPLLA=VDDPLLD=VDDLVDS,
RL(PCLK)=RL(D0)=100 Ω, VIH=VDD, VIL=0 V,
TXEN at VDD,
typical power test pattern (see Table 7)
fPCLK = 20 MHz
Standby Mode
fPCLK = 65 MHz
fPCLK = 65 MHz
VDD = VDDPLLA = VDDPLLD
= VDDLVDS,
RL(PCLK)=RL(D0)=100 Ω,
VIH=VDD, VIL=0 V, all
inputs held static high or
static low
Shutdown Mode
(1)
MIN
UNIT
mA
mA
mA
mA
mA
15.9
mA
24.7
0.61
10
µA
0.55
10
µA
MAX
UNIT
All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
OUTPUT ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP (1)
subLVDS output (D0+, D0–, D1+, D1–, D2+, D1–, CLK+, and CLK–)
VOC(SS)M
Steady-state common-mode output voltage
VOCM(SS)
Change in steady-state common-mode output voltage
VOCM(PP)
Peak-to-peak common mode output voltage
|VOD|
Differential output voltage magnitude
|VDx+– VDx– |, |VCLK+– VCLK– |
∆|VOD|
Change in differential output voltage between logic states
ZOD(CLK)
Differential small-signal output impedance
TXEN at VDD
IOSD
Differential short-circuit output current
VOD = 0 V, fPCLK = 28 MHz
IOS
Short circuit output current (2)
VO = 0 V or VDD
IOZ
High-impedance state output current
VO = 0 V or VDD(max),
TXEN at GND
(1)
(2)
12
Output load see Figure 10
0.8
0.9
–10
100
150
–10
All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
All SN65LVDS301 outputs tolerate shorts to GND or VDD without permanent device damage.
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1.0
V
10
mV
75
mV
200
10
mV
Ω
210
10
5
–3
mV
3
mA
µA
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INPUT ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1) MAX
UNIT
PCLK, R[0:7], G[0:7], B[0:7], VS, HS, DE, PCLK, LS[1:0], CPOL, TXEN, SWAP
IIH
High-level input current
VIN = 0.7 × VDD
–200
200
IIL
Low-level input current
VIN = 0.3 × VDD
–200
200
CIN
Input capacitance
(1)
nA
1.5
pF
All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
tr
20%-to-80% differential
output signal rise time
See Figure 9 and Figure 10
250
500
tf
20%-to-80% differential
output signal fall time
See Figure 9 and Figure 10
250
500
PLL bandwidth (3dB cutoff
frequency)
Tested from PCLK input to
CLK output, See Figure 7 (2)
fPCLK = 22 MHz
0.082 × fPCLK
fPCLK = 65 MHz
0.07 × fPCLK
Propagation delay time,
input to serial output (data
latency Figure 11)
TXEN at VDD, VIH=VDD,
VIL=GND, RL=100 Ω
1-channel mode
0.8/fPCLK
1/fPCLK
1.2/fPCLK
2-channel mode
1.0/fPCLK
1.21/fPCLK
1.5/fPCLK
3-channel mode
1.1/fPCLK
1.31/fPCLK
1.6/fPCLK
1-channel and 3-channel
mode
0.45
0.50
0.55
2-channel mode
0.49
0.53
0.58
fBW
tpd(L)
tH× fCLK0
Output CLK duty cycle
tGS
TXEN Glitch suppression
pulse width (3)
VIH=VDD, VIL=GND, TXEN toggles between VIL and VIH,
see Figure 14 and Figure 15
tpwrup
Enable time from power
down (↑TXEN)
Time from TXEN pulled high to CLK and Dx outputs
enabled and transmit valid data; see Figure 15
tpwrdn
Disable time from active
mode (↓TXEN)
TXEN is pulled low during transmit mode; time
measurement until output is disabled and PLL is
Shutdown; see Figure 15
twakup
Enable time from Standby
(↕PCLK)
TXEN at VDD; device in standby; time measurement from
PCLK starts switching to CLK and Dx outputs enabled and
transmit valid data; see Figure 15
Disable time from Active
mode (PCLK stopping)
TXEN at VDD; device is transmitting; time measurement
from PCLK input signal stops until CLK + Dx outputs are
disabled and PLL is disabled; see Figure 15
tsleep
(1)
(2)
(3)
3.8
10
0.24
2
0.5
11
0.23
2
UNIT
ps
MHz
s
µs
ms
µs
ms
0.4
100
µs
All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
The Maximum Limit is based on statistical analysis of the device performance over process, voltage, and temp ranges. This parameter
is functionality tested only on Automatic Test Equipment (ATE).
The TXEN input incorporates glitch-suppression circuitry to disregard short input pulses. tGS is the duration of either a high-to-low or
low-to-high transition that is suppressed.
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12.0%
9.0
4 MHz: 8 MHz:
8.5%
8.5%
11.0%
20 MHz:
8.3%
RX PLL BW
10.0%
9%
9.0%
8.5%
8.0%
7.5%
7.0%
7%
6.0%
PLL BANDWIDTH - %
PLL BW [% of PCLK Frequency]
8.5
Spec Limit
1ChM
8.0
7.5
Spec
Limit
2ChM
30 MHz:
7.6%
15 MHz:
7.6%
Spec Limit 3ChM
7.0
65 MHz:
7.0%
TX PLL BW
6.5
5.0%
6.0
4.0%
0
100
200
300
400
500
600
700
0
10
PLL frequency − MHz
20
30
40
50
60
70
PCLK FREQUENCY - MHz
Figure 7. LVDS301 PLL Bandwidth (also showing the LVDS302 PLL bandwidth)
TIMING CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
1ChM: x=0..29, fPCLK=15 MHz; TXEN at
VDD, VIH=VDD, VIL=GND, RL=100 Ω, test
pattern as in Table 10 (3)
x
- 330 ps
30 × fPCLK
x
+ 330 ps
30 × fPCLK
x – 0.1845
30 × fPCLK
x + 0.1845
30 × fPCLK
x
- 330 ps
15 × fPCLK
x
+ 330 ps
15 × fPCLK
x – 0.1845
15 × fPCLK
x + 0.1845
15 × fPCLK
x
- 210 ps
10 × fPCLK
x
+ 210 ps
10 × fPCLK
x - 0.153
10 × fPCLK
x + 0.153
10 × fPCLK
1ChM: x=0..29,
fPCLK=4 MHz to 15 MHz
tPPOSX
Output Pulse Position,
serial data to ↑CLK; see
(1) (2)and Figure 13
(4)
2ChM: x = 0..14, fPCLK = 30 MHz
TXEN at VDD, VIH=VDD, VIL=GND,
RL=100 Ω, test pattern as in Table 11 (3)
2ChM: x=0..14,
fPCLK= 8 MHz to 30 MHz
(4)
3ChM: x=0..9, fPCLK=65 MHz,
TXEN at VDD, VIH=VDD, VIL=GND,
RL=100 Ω, test pattern as in Table 12 (3)
3ChM: x=0..9,
fPCLK=20 MHz to 65 MHz
(1)
(2)
(3)
(4)
14
(4)
TYP
MAX
UNIT
ps
This number also includes the high-frequency random and deterministic PLL clock jitter that is not traceable by the SN65LVDS302
receiver PLL; tPPosx represents the total timing uncertainty of the transmitter necessary to calculate the jitter budget when combined
with the SN65LVDS302 receiver;
The pulse position min/max variation is given with a bit error rate target of 10–12; The measurement estimates the random jitter
contribution to the total jitter contribution by multiplying the random RMS jitter by the factor 14; Measurements of the total jitter are taken
over a sample amount of > 10–12 samples.
The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temp ranges.
This parameter is functionality tested only on Automatic Test Equipment (ATE).
These Minimum and Maximum Limits are simulated only.
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PARAMETER MEASUREMENT INFORMATION
t DS
VIH
R[7:0], G[7:0], B[7:0];
VS, HS, DE, LS0, LS1,
TXEN, SWAP, CPOL
VIL
t DH
VIH
PCLK
(CPOL=low)
VIL
tR
Figure 8. Setup/Hold Time
VOD
tf
tr
150mV (nom)
80%
0V
20%
−150mV (nom)
Figure 9. Rise and Fall Time Definitions
R1 = 49.9
CLK+, Dx+
VDx+ or V CLK+
975mV (nom)
VDx− or V CLK−
825mV (nom)
VOD
CLK−, Dx−
R2 = 49.9
VOCM
VOCM
SN65LVDS301
C1 = 1 pF
C2 = 1 pF
VOCM (pp)
VOCM (ss)
NOTES:
A. 20 MHz output test pattern on all differental outputs (CLK, D0, D1, and D2):
this is achieved by: 1. Device is set to 3-channel-mode;
2. fPCLK = 20 MHz
3. Inputs R[7:3] = B[7:3] connected to VDD, all other data inputs set to GND.
B. C1, C2 and C3 includes instrumentation and fixture capacitance; tolerance± 20%; C, R1 and R2 tolerance± 1%.
C. The measurement of VOCM (pp) and VOC (ss) are taken with test equipment bandwidth >1 GHz.
Figure 10. Driver Output Voltage Test Circuit and Definitions
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PARAMETER MEASUREMENT INFORMATION (continued)
CMOS
Data In
pixel (n)
pixel (n+1)
R7(n−1)
R7(n)
R7(n+1)
R6(n−1)
R6(n)
R6(n+1)
VDD /2
PCLK
t PROP
CLK−
CLK+
D0+
CP R7 R6
CP R7 R6
pixel (n−1)
pixel (n−2)
R6(n−1)
R7(n−1)
R7(n)
Figure 11. tpd(L) Propagation Delay Input to Output (LS0 = LS1 = 0; CPOL = 0)
1
SN65LVDS301
VDDPLLD
V DDPLLA
2
1
Noise
Generator
100 mV
V DD
10 mF
VDDLVDS
GND
Note: The generator regulates the
noise amplitude at point
1 to the
target amplitude given under the table
Recommended Operating Conditions
1.6 H
1.8 V
supply
Figure 12. Power Supply Noise Test Set-Up
tCLK+
CLK−
CLK+
Next Cycle
Current Cycle
D[0:m]+
Bit 0
Bit1
Bit2
Bitx
Bit0
Bit1
tPPOS0
Note:
1−channel mode: x=0..29; m=0
2−channel mode: x=0..14; m=1
3−channel mode: x=0....9; m=2
tPPOS1
tPPOS2
tPPOSx
Figure 13. tSK(0) SubLVDS Output Pulse Position Measurement
16
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PARAMETER MEASUREMENT INFORMATION (continued)
VDD/2
TXEN
t GS
PCLK
PLL Approaches Lock
VCO Internal Signal
t pwrup
CLK
D0, D1, D2
Figure 14. Transmitter Behavior While Approaching Sync
Figure 15. Transmitter Enable Glitch Suppression Time
PCLK
twakeup
tsleep
CLK+
Transmitter Disabled
(OFF)
Transmitter Aquires Lock,
Outputs Still Disabled
Transmitter Enabled,
Output Data Valid
Transmitter
Enabled,
Output Data
Valid
Transmitter
Disabled
(OFF)
Figure 16. Standby Detection
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PARAMETER MEASUREMENT INFORMATION (continued)
Power Consumption Tests
Table 4 shows an example test pattern word.
Table 4. Example Test Pattern Word
7
Word
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x7C3E1E7
C
3
E
1
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
E
7
B6
B5
B4
B3
B2
B1
B0
0
0
0
1
1
1
1
0
0
0
VS HS DE
1
1
1
Typical IC Power Consumption Test Pattern
The typical power consumption test patterns consists of sixteen 30-bit transmit words in 1-channel mode, eight
30-bit transmit words in 2-channel mode and five 30-bit transmit words in 3-channel mode. The pattern repeats
itself throughout the entire measurement. It is assumed that every possible transmit code on RGB inputs has the
same probability to occur during typical device operation.
Table 5. Typical IC Power Consumption Test Pattern,
1-Channel Mode
Word
18
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x0000007
2
0xFFF0007
3
0x01FFF47
4
0xF0E07F7
5
0x7C3E1E7
6
0xE707C37
7
0xE1CE6C7
8
0xF1B9237
9
0x91BB347
10
0xD4CCC67
11
0xAD53377
12
0xACB2207
13
0xAAB2697
14
0x5556957
15
0xAAAAAB3
16
0xAAAAAA5
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Table 6. Typical IC Power Consumption Test Pattern,
2-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x0000001
2
0x03F03F1
3
0xBFFBFF1
4
0x1D71D71
5
0x4C74C71
6
0xC45C451
7
0xA3aA3A5
8
0x5555553
Table 7. Typical IC Power Consumption Test Pattern,
3-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0xFFFFFF1
2
0x0000001
3
0xF0F0F01
4
0xCCCCCC1
5
0xAAAAAA7
Maximum Power Consumption Test Pattern
The maximum (or worst-case) power consumption of the SN65LVDS301 is tested using the two different test
patterns shown in Table 8 and Table 9. The test patterns consist of sixteen 30-bit transmit words in 1-channel
mode, eight 30-bit transmit words in 2-channel mode and five 30-bit transmit words in 3-channel mode. The
pattern repeats itself throughout the entire measurement. It is assumed that every possible transmit code on
RGB inputs has the same probability to occur during typical device operation.
Table 8. Worst-Case Power Consumption Test Pattern
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0xAAAAAA5
2
0x5555555
Table 9. Worst-Case Power Consumption Test Pattern
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x0000000
2
0xFFFFFF7
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Output Skew Pulse Position & Jitter Performance
The following test patterns are used to measure the output-skew pulse position and the jitter performance of the
SN65LVDS301. The jitter test pattern stresses the interconnect, particularly to test for ISI. Very long run-lengths
of consecutive bits incorporate very high and low data rates, maximinges switching noise. Each pattern is
self-repeating for the duration of the test.
Table 10. Transmit Jitter Test Pattern, 1-Channel Mode
Word
20
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x0000001
2
0x0000031
3
0x00000F1
4
0x00003F1
5
0x0000FF1
6
0x0003FF1
7
0x000FFF1
8
0x0F0F0F1
9
0x0C30C31
10
0x0842111
11
0x1C71C71
12
0x18C6311
13
0x1111111
14
0x3333331
15
0x2452413
16
0x22A2A25
17
0x5555553
18
0xDB6DB65
19
0xCCCCCC1
20
0xEEEEEE1
21
0xE739CE1
22
0xE38E381
23
0xF7BDEE1
24
0xF3CF3C1
25
0xF0F0F01
26
0xFFF0001
27
0xFFFC001
28
0xFFFF001
29
0xFFFFC01
30
0xFFFFF01
31
0xFFFFFC1
32
0xFFFFFF1
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Table 11. Transmit Jitter Test Pattern, 2-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x0000001
2
0x000FFF3
3
0x8008001
4
0x0030037
5
0xE00E001
6
0x00FF001
7
0x007E001
8
0x003C001
9
0x0018001
10
0x1C7E381
11
0x3333331
12
0x555AAA5
13
0x6DBDB61
14
0x7777771
15
0x555AAA3
16
0xAAAAAA5
17
0x5555553
18
0xAAA5555
19
0x8888881
20
0x9242491
21
0xAAA5571
22
0xCCCCCC1
23
0xE3E1C71
24
0xFFE7FF1
25
0xFFC3FF1
26
0xFF81FF1
27
0xFE00FF1
28
0x1FF1FF1
29
0xFFCFFC3
30
0x7FF7FF1
31
0xFFF0007
32
0xFFFFFF1
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Table 12. Transmit Jitter Test Pattern, 3-Channel Mode
Word
22
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x0000001
2
0x0000001
3
0x0000003
4
0x0101013
5
0x0303033
6
0x0707073
7
0x1818183
8
0xE7E7E71
9
0x3535351
10
0x0202021
11
0x5454543
12
0xA5A5A51
13
0xADADAD1
14
0x5555551
15
0xA6A2AA3
16
0xA6A2AA5
17
0x5555553
18
0x5555555
19
0xAAAAAA1
20
0x5252521
21
0x5A5A5A1
22
0xABABAB1
23
0xFDFCFD1
24
0xCAAACA1
25
0x1818181
26
0xE7E7E71
27
0xF8F8F81
28
0xFCFCFC1
29
0xFEFEFE1
30
0xFFFFFF1
31
0xFFFFFF5
32
0xFFFFFF5
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TYPICAL CHARACTERISTICS
POWERDOWN, STANDBY SUPPLY CURRENT
vs TEMPERATURE
SUPPLY CURRENT IDD vs TEMPERATURE
20
1.0
2-Channel Mode, 22 MHz (VGA)
IDD - mA
IDDQ - mA
15
Standby Current
2-Channel Mode, 11 MHz (HVGA)
10
Power-Down Current
5
0.1
-50
-30
-10
10
30
50
Temperature - °C
70
0
-50
90
-30
-10
10
30
50
Temperature - °C
70
90
Figure 17.
Figure 18.
SUPPLY CURRENT vs PCLK FREQUENCY
DIFFERENTIAL OUTPUT SWING vs PCLK FREQUENCY
200
30
Differential Output Swing VOD - mV
85°C
3-Channel Mode
25
2-Channel Mode
15
10
1-Channel Mode
5
0
10
20
30
40
50
FREQUENCY - MHz
60
25°C
180
170
–40°C
160
150
140
130
120
110
100
0
70
10
20
30
40
50
FREQUENCY - MHz
60
Figure 19.
Figure 20.
PLL BANDWIDTH
CYCLE-TO-CYCLE OUTPUT JITTER
vs PCLK FREQUENCY
70
500
400
CC JITTER - ps
IDD - mA
20
190
300
200
100
3-Channel Mode
1-Channel Mode
0
0
Figure 21.
10
20
2-Channel Mode
30
40
50
FREQUENCY - MHz
60
70
Figure 22.
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SN65LVDS301
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SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
CYCLE-TO-CYCLE OUTPUT JITTER
vs TEMPERATURE
OUTPUT PULSE POSITION vs TEMPERATURE
200
2-Channel Mode,
f(PCLK) = 11 MHz
150
CC JITTER - ps
OUTPUT PULSE POSITION (tPPOS) - PS
120
100
2-Channel Mode,
f(PCLK) = 22 MHz
50
0
-50
-25
0
25
50
Temperature - °C
75
100
2-Channel Mode,
11 MHz (VGA)
100
80
60
2-Channel Mode,
22 MHz (HVGA)
40
20
0
-50
-25
Figure 24.
DATA EYE PATTERN, 2-CHANNEL MODE
DATA EYE PATTERN, 3-CHANNEL MODE
Figure 25.
Figure 26.
VGA 2-CHANNEL OUTPUT WAVEFORM
250
190
190
Output Voltage Amplitude - mV
Output Voltage Amplitude - mV
QVGA OUTPUT WAVEFORM
1-Channel Mode,
f(PCLK) = 5.5 MHz
–190
0
2-Channel Mode,
f(PCLK) = 22 MHz
–190
–251
24
75
Figure 23.
249
0
0
25
50
TEMPERATURE - °C
–250
1 ns/div
Response Over 80-inch of FR-4 + 1m Coax Cable
500 ps/div
Response Over 8-inch FR-4 + 1m Coax Cable
Figure 27.
Figure 28.
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100
SN65LVDS301
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SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
VGA3-CHANNEL OUTPUT WAVEFORM
249
190
190
Output Voltage Amplitude - mV
Output Voltage Amplitude - mV
VGA 2-CHANNEL OUTPUT WAVEFORM
249
2-Channel Mode,
f(PCLK) = 22 MHz
0
0
3-Channel Mode,
f(PCLK) = 22 MHz
–190
–190
–251
–251
500 ps/div
Response Over 80-inch FR-4 + 1m Coax Cable
1 ns/div
Response Over 80-inch FR-4 + 1m Coax Cable
Figure 29.
Figure 30.
XGA 3-CHANNEL OUTPUT WAVEFORM
XGA 3-CHANNEL OUTPUT WAVEFORM ON THE
SN65LVDS302 WHEN DRIVEN BY THE SN65LVDS301
249
Output Voltage Amplitude - mV
400 mV/div
Output Voltage Amplitude - mV
190
0
–190
3-Channel Mode,
f(PCLK) = 56 MHz
3-Channel Mode,
f(PCLK) = 56 MHz
–251
300 ps/div
Response Over 80-inch FR-4 + 1m Coax Cable
3.5 ns/div
Response With 10-pF Load
Figure 31.
Figure 32.
PLL PHASE NOISE
OUTPUT RETURN LOSS
-50
-60
-70
-80
-90
dBc/Hz
-100
f(PCLK) = 65 MHz
-110
-120
-130
-140
-150
-160
-170
-180
1
10
100
1k
10k
100k
1M
10M
FREQUENCY - Hz
Figure 33.
Figure 34.
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SN65LVDS301
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SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
OUTPUT COMMON MODE NOISE REJECTION
CROSSTALK
Figure 35.
Figure 36.
GTEM SAE J1752/3 EMI TEST(A)
Figure 37.
A.
26
Figure 37 shows a superimposed image of three EMI measurements with the device operating at f(PCLK) = 5 MHz,
f(PCLK) = 22 MHz, and f(PCLK) = 65 MHz. This excellent EMI performance meets the system requirements of
dense, mobile designs with a noise floor of ~2 dBµV (-105 dBm) and all spurs being smaller than 16 dBµV (-101
dBm). The test was performed in compliance with the SAE J1752/3 EMI test guidelines.
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SN65LVDS301
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SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006
APPLICATION INFORMATION
Preventing Increased Leakage Currents in Control Inputs
A floating (left open) CMOS input allows leakage currents to flow from VDD to GND. Do not leave any CMOS
Input unconnected or floating. Every input must be connected to a valid logic level VIH or VOL while power is
supplied to VDD. This also minimizes the power consumption of standby and power down mode.
Power Supply Design Recommendation
For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all
ground terminals directly to this plane.
Decoupling Recommendation
The SN65LVDS301 was designed to operate reliably in a constricted environment with other digital switching
ICs. In cell phone designs, the SN65LVDS301 often shares a power supply with the application processor. The
SN65LVDS301 can operate with power supply noise as specified in Recommend Device Operating Conditions.
To minimize the power supply noise floor, provide good decoupling near the SN65LVDS301 power pins. The
use of four ceramic capacitors (2×0.01 µF and 2×0.1 µF) provides good performance. At the very least, it is
recommended to install one 0.1 µF and one 0.01 µF capacitor near the SN65LVDS301. To avoid large current
loops and trace inductance, the trace length between decoupling capacitor and IC power inputs pins must be
minimized. Placing the capacitor underneath the SN65LVDS301 on the bottom of the pcb is often a good choice.
VGA Application
Figure 38 shows a possible implementation of a VGA display. The LVDS301 interfaces to the SN65LVDS302,
which is the corresponding receiver device to deserialize the data and drive the display driver. The pixel clock
rate of 22 MHz assumes ~10% blanking overhead and 60 Hz display refresh rate. The application assumes
24-bit color resolution. It is also shown, how the application processor provides a powerdown (reset) signal for
both serializer and the display driver. The signal count over the FPC could be further decreased by using the
standby option on the SN65LVDS302 and pulling RXEN high with a 30 kΩ resistor to VDD.
GND
GND
22MHz
27
PCLK
R[7:0]
G[7:0]
B[7:0]
HS,VS,DE
22MHz
D0+
D0D1+
D1-
330Mbps
330Mbps
CLK+
CLKD0+
D0D1+
D1-
22MHz
27
SN65LVDS302
LS0
TXEN
LS1
LS0
RESET
SPI
SN65LVDS301
PCLK
R[7:0]
G[7:0]
B[7:0]
HS,VS,DE
Video Mode Display
Driver
1.8V
RXEN
Pixel CLK
2x0.01uF
LCD with VGA
resolution
1.8V
SPI
1.8V
ENABLE
2.7V
CLK+
CLK-
2x0.1uF
GND
LS1
VDDx
Application
Processor
(e.g. OMAP)
D[7:0]
D[15:8]
D[23:16]
HS,VS,DE
GND
2x0.01uF
FPC
GND
GND
2.7V
VDDx
2x0.1uF
1.8V
If FPC wire count is critical , replace this
connection with a pull -up resistor at RXEN
Serial port interface
(3-wire IF)
3
Figure 38. Typical VGA Display Application
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SN65LVDS301
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SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006
APPLICATION INFORMATION (continued)
Dual LCD-Display Application
The example in Figure 39 shows a possible application setup driving two video mode displays from one
application processor. The data rate of 330 Mbps at a pixel clock rate of 5.5 MHz corresponds to QVGA
resolution at 60 Hz refresh rate and 10% blanking overhead.
18+3
GND
PCLK
5.5MHz
D0+
D0-
R[5:0]
G[5:0]
B[5:0]
HS,VS,DE
330Mbps
Display Driver1
21
CLK+
CLKD0+
D0-
PCLK
R[5:0]
G[5:0]
B[5:0]
HS,VS,DE
PCLK
EN
SIN
SOUT
SCLK
SN65LVDS302
LS0
TXEN
LS0
LS1
SN65LVDS301
SCLK
SIN
SOUT
SEL2
SEL1
GND
2x0.01uF
LCD with QVGA
resolution
1.8V
GND
2.7V
1.8V
Display Driver2
LCD with QVGA
resolution
D[5:0]
D[11:6]
D[17:12]
HS,VS,DE
5.5MHz
2.7V
CLK+
CLK-
2x0.1uF
GND
RXEN
VDDx
Application
Processor
(e.g. OMAP)
Pixel CLK
GND
2x0.01uF
FPC
VDDx
GND
LS1
2x0.1uF
PCLK
1.8V
EN
SIN
SOUT
SCLK
1.8V
Figure 39. Example Dual-QVGA Display Application
Typical Application Frequencies
The SN65LVDS301 supports pixel clock frequencies from 4 MHz to 65 MHz over 1, 2, or 3 data lanes. Table 13
provides a few typical display resolution examples and shows the number of data lanes necessary to connect
the LVDS301 with the display. The blanking overhead is assumed to be 20%. Often, blanking overhead is
smaller, resulting in a lower data rate. Furthermore, the examples in the table assumes a display frame refresh
rate of 60 Hz or 90 Hz. The actual refresh rate may differ depending on the application-processor clock
implementation.
Table 13. Typical Application Data Rates & Serial Lane Usage
Display Screen
Resolution
Visible
Pixel Count
Blanking
Overhead
Display
Refresh
Rate
Pixel Clock Frequency
[MHz]
176x220 (QCIF+)
38,720
20%
90 Hz
4.2 MHz
125 Mbps
240x320 (QVGA)
76,800
60 Hz
5.5 MHz
166 Mbps
640x200
128,000
9.2 MHz
276 Mbps
138 Mbps
352x416 (CIF+)
146,432
10.5 MHz
316 Mbps
158 Mbps
352x440
154,880
11.2 MHz
335 Mbps
167 Mbps
320x480 (HVGA)
153,600
11.1 MHz
332 Mbps
166 Mbps
800x250
200,000
14.4 MHz
432 Mbps
216 Mbps
640x320
204,800
14.7 MHz
442 Mbps
221 Mbps
640x480 (VGA)
307,200
22.1 MHz
332 Mbps
221 Mbps
1024x320
327,680
23.6 MHz
354 Mbps
236 Mbps
854x480 (WVGA)
409,920
29.5 MHz
443 Mbps
295 Mbps
800x600 (SVGA)
480,000
34.6 MHz
346 Mbps
1024x768 (XGA)
786,432
56.6 MHz
566 Mbps
28
Submit Documentation Feedback
Serial Data Rate Per Lane
1-ChM
2-ChM
3-ChM
SN65LVDS301
www.ti.com
SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006
Calculation Example: HVGA Display
Display Resolution:
480 x 320
Frame Refresh Rate:
58.4 Hz
Horizontal Visible Pixel:
480 columns
Horizontal Front Porch:
20 columns
Horizontal Sync:
5 columns
Horizontal Back Porch:
3 columns
Vertical Visible Pixel:
320 lines
Vertical Front Porch:
10 lines
Vertical Sync:
5 lines
Vertical Back Porch:
3 lines
Hsync = 5
HBP
This example calculation shows a typical Half-VGA display with these parameters:
Visible area = 480 column
HFP = 20
Vsync = 5
VBP = 3
Visible area
= 320 lines
Visible area
VFP = 10
Entire display
Figure 40. HVGA Display Parameters
Calculation of the total number of pixel and Blanking overhead:
Visible Area Pixel Count:
480 × 320 = 153600 pixel
Total Frame Pixel Count:
(480+20+5+3) × (320+10+5+3) = 171704 pixel
Blanking Overhead:
(171704-153600) ÷ 153600 = 11.8 %
The application requires following serial-link parameters:
Pixel Clk Frequency:
171704 × 58.4 Hz = 10.0 MHz
Serial Data Rate:
1-channel mode: 10.0 MHz × 30 bit/channel = 300 Mbps
2-channel mode: 10.0 MHz × 15 bit/channel = 150 Mbps
Submit Documentation Feedback
29
PACKAGE OPTION ADDENDUM
www.ti.com
12-Sep-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
SN65LVDS301ZQE
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQE
80
360
Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
SN65LVDS301ZQER
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQE
80
2500 Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN65LVDS301ZQER
Package Package Pins
Type Drawing
BGA MI
CROSTA
R JUNI
OR
ZQE
80
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
5.3
5.3
1.5
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65LVDS301ZQER
BGA MICROSTAR
JUNIOR
ZQE
80
2500
340.5
333.0
20.6
Pack Materials-Page 2
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