SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 PROGRAMMABLE 27-BIT DISPLAY SERIAL-INTERFACE TRANSMITTER FEATURES • • • • • • • • • • • • • • FlatLink™3G Serial-Interface Technology Compatible With FlatLink3G Receivers Such as SN65LVDS304 Input Supports 24-bit RGB Video Mode Interface 24-Bit RGB Data, 3 Control Bits, 1 Parity Bit and 2 Reserved Bits Transmitted over 1 or 2 Differential Lines SubLVDS Differential Voltage Levels Effective Data Throughput up to 810 Mbps Three Operating Modes to Conserve Power – Active-Mode QVGA 17.4 mW (typ) – Active-Mode VGA 28.8 mW (typ) – Shutdown Mode ≈ 0.5 µA (typ) – Standby Mode ≈ 0.5 µA (typ) Bus Swap for Increased PCB Layout Flexibility 1.8-V Supply Voltage ESD Rating > 2 kV (HBM) Typical Application: Host-Controller to Display-Module Interface Pixel Clock Range of 4 MHz–30 MHz Failsafe on All CMOS Inputs Packaging: 80-Terminal, 5-mm × 5-mm µBGA® FPC cabling typically interconnects the SN65LVDS303 with the display. Compared to parallel signaling, the SN65LVDS303 outputs significantly reduce the EMI of the interconnect by over 20 dB. The SN65LVDS303 supports three power modes (shutdown, standby and active) to conserve power. When transmitting, the PLL locks to the incoming pixel clock, PCLK, and generates an internal high-speed clock at the line rate of the data lines. The parallel data are latched on the rising or falling edge of PCLK, as selected by the external control signal CPOL. The serialized data is presented on the serial outputs D0 and D1, together with a recreated PCLK that is generated from the internal high-speed clock and output on CLK. If PCLK stops, the device enters a standby mode to conserve power. The parallel (CMOS) input bus offers a bus-swap feature. The SWAP terminal configures the input order of the pixel data to be either R[7:0], G[7:0], B[7:0], VS, HS, DE or B[0:7]. G[0:7], R[0:7], VS, HS, DE. This gives a PCB designer the flexibility to better match the bus to the host controller pinout or to put the transmitter device on the top side or the bottom side of the PCB. Flatlinkä3G DESCRIPTION The SN65LVDS303 serializer device converts 27 parallel data inputs to one or two sub-low-voltage differential signaling (SubLVDS) serial outputs. It loads a shift register with 24 pixel bits and 3 control bits from the parallel CMOS input interface. In addition to the 27 data bits, the device adds a parity bit and two reserved bits into a 30-bit data word. Each word is latched into the device by the pixel clock (PCLK). The parity bit (odd parity) allows a receiver to detect single bit errors. The serial shift register is uploaded at 30 or 15 times the pixel-clock data rate, depending on the number of serial links used. A copy of the pixel clock is output on a separate differential output. LCD Driver LVDS304 CLK DATA LVDS303 1 2 3 4 5 6 7 8 9 * 0 # Application Processor with RGB Video Interface Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FlatLink is a trademark of Texas Instruments. µBGA is a registered trademark of Tessera, Inc.. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2007, Texas Instruments Incorporated SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The link select line, LS, controls whether one or two serial links are used. The TXEN input may be used to put the SN65LVDS303 in a shutdown mode. The SN65LVDS303 enters an active standby mode if the input clock, PCLK, stops. This minimizes power consumption without the need for controlling an external terminal. The SN65LVDS303 is characterized for operation over ambient air temperatures of –40°C to 85°C. All CMOS inputs offer failsafe to protect the input from damage during power up and to avoid current flow into the device inputs during power up. An input voltage of up to 2.165 V can be applied to all CMOS inputs while VDD is between 0 V and 1.65 V. Functional Block Diagram Parity Calc D0+ SWAP SubLVDS D0– 1 Bit28 = 0 Bit27 = 0 0 8 [0..26] R[0:7] 8 G[0:7] 8 B[0:7] HS VS 2 ´ 15- or 1 ´ 30-Bit Parallel-to-Serial Conversion Bit29 D1+ SubLVDS D1– CLK+ SubLVDS DE CLK– PCLK 0 iPCLK ´15 or ´30 1 ´1 PLL Multiplier CPOL GND LS TXEN 2 Glitch Supression Control/Standby Monitor Submit Documentation Feedback SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 PINOUT – TOP VIEW 1 2 GND G2/G5 G0/G7 G1/G6 B6/R1 B7/R0 4 5 6 7 8 9 G4/G3 G6/G1 R0/B7 R2/B5 R4/B3 R6/B1 GND G3/G4 G5/G2 G7/G0 R1/B6 R3/B4 R5/B2 R7/B0 VDD GND VDD VDD GND LS 3 A B C D B4/R3 B5/R2 VDD GND GND GND GND GND NC B3/R4 GND VDD GND GND GND GND GNDPLLD NC B1/R6 B2/R5 VDD GND GND GND GND VDDPLLD D1+ PCLK B0/R7 VDD GND GND GND GNDLVDS D1- HS VS GND GND DE TXEN E F G GND H GNDLVDS VDDLVDS GNDPLLA VDDPLLA VDDLVDS CPOL J D0– D0+ CLK– CLK+ SWAP GNDLVDS RGB Input pin assignment based on SWAP pin setting : SWAP=0/SWAP=1 Submit Documentation Feedback 3 SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 PINOUT – TOP VIEW (continued) SWAP TERMINAL FUNCTIONALITY The SWAP terminal allows the PCB designer to reverse the RGB bus, thus minimize potential signal crossovers due to signal routing. Figure 1 and Figure 2 show the RGB signal terminal assignment based on the SWAP terminal setting. 1 2 3 4 5 6 7 8 G6 R0 R2 R4 R6 9 A 1 2 3 4 5 6 7 8 9 A G2 G4 B G5 G3 G1 B7 B5 B3 B1 G7 G6 G4 G2 G0 B6 B4 B2 R1 R0 B G0 G1 G3 G5 G7 R1 R3 R5 R7 C B0 C B6 B7 SN65LVDS303 D B4 D B5 R3 Top View E B3 R2 E Top View R4 F SN65LVDS303 F B1 B2 PCLK B0 G R6 R5 PCLK R7 HS VS G H H HS VS J J DE SWAP DE 1.8V SWAP=0 Figure 1. SWAP TERMINAL = 0 4 Submit Documentation Feedback SWAP=1 SWAP Figure 2. SWAP Terminal = 1 SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 Table 1. NUMERIC TERMINAL LIST . TERMINAL A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 SWAP SIGNAL TERMINAL SWAP SIGNAL — GND 0 G2 B1 1 G5 R6 0 0 G4 B2 1 R5 1 G3 C3 UNPOPULATED 0 G6 C4 — VDD F3 — VDD F4 — 1 G1 C5 — GND GND F5 — GND 0 R0 C6 1 B7 C7 — VDD F6 — GND — VDD F7 — 0 R2 GND C8 — GND F8 — VDDPLLD 1 B5 0 R4 C9 — LS F9 — D1+ 0 B4 G1 — 1 B3 PCLK 1 R3 0 0 R6 B0 0 B5 1 R7 1 B1 — GND D3 1 R2 G3 — VDD — VDD G4 — 0 G0 GND D4 — GND G5 — GND 1 0 G7 D5 — GND G6 — GND G1 D6 — GND G7 — GND 1 G6 D7 — GND G8 — GNDLVDS 0 G3 D8 — GND G9 — D1– 1 G4 D9 — NC H1 — HS 0 G5 0 B3 H2 — VS 1 G2 1 R4 H3 — GND 0 G7 E2 — GND H4 — GNDLVDS 1 G0 E3 — VDD H5 — VDDLVDS 0 R1 E4 — GND H6 — GNDPLLA 1 B6 E5 — GND H7 — VDDPLLA 0 R3 E6 — GND H8 — VDDLVDS 1 B4 E7 — GND H9 — CPOL 0 R5 E8 — GNDPLLD J1 — GND 1 B2 E9 — NC J2 — DE 0 R7 J3 — TXEN 1 B0 J4 — D0– J5 — D0+ J6 — CLK– J7 — CLK+ J8 — SWAP J9 — GNDLVDS D1 D2 E1 R1 0 B7 1 R0 SIGNAL 1 C2 B6 1 SWAP 0 C1 0 TERMINAL Submit Documentation Feedback F1 F2 G2 5 SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 Table 2. TERMINAL FUNCTIONS NAME I/O D0+, D0– D1+, D1– DESCRIPTION SubLVDS data link (active during normal operation) SubLVDS out SubLVDS data link (active during normal operation when LS = high; high impedance if LS = low) CLK+, CLK– SubLVDS output clock; clock polarity is fixed. R0–R7 Red pixel data (8); terminal assignment depends on SWAP terminal setting. G0–G7 Green pixel data (8); terminal assignment depends on SWAP terminal setting. B0–B7 Blue pixel data (8); terminal assignment depends on SWAP terminal setting. HS Horizontal sync VS Vertical sync DE Data enable PCLK Input pixel clock; rising or falling clock polarity is selected by control input CPOL. CMOS in LS Link select (determines active SubLVDS data links and PLL range); see Table 3. Disables the CMOS drivers and turns off the PLL, putting device in shutdown mode 1 – Transmitter enabled 0 – Transmitter disabled (shutdown) Note: The TXEN input incorporates glitch-suppression logic to avoid device malfunction on short input spikes. It is necessary to pull TXEN high for longer than 10 µs to enable the transmitter. It is necessary to pull the TXEN input low for longer than 10 µs to disable the transmitter. At power up, the transmitter is enabled immediately if TXEN = 1 and disabled if TXEN = 0 TXEN Input clock polarity selection CPOL SWAP CMOS in 0 – rising edge clocking 1 – falling edge clocking Bus swap. Swaps the bus terminals to allow device placement on top or bottom of PCB. See pinout drawing for terminal assignments. 0 – data input from B0...R7 1 – data input from R7...B0 VDD Supply voltage GND Supply ground VDDLVDS SubLVDS I/O supply voltage GNDLVDS VDDPLLA Power supply (1) SubLVDS ground PLL analog supply voltage GNDPLLA PLL analog GND VDDPLLD PLL digital supply voltage GNDPLLD PLL digital GND (1) 6 CMOS in For a multilayer PCB, it is recommended to keep one common GND layer underneath the device and connect all ground terminals directly to this plane. Submit Documentation Feedback SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 FUNCTIONAL DESCRIPTION Serialization Modes The SN65LVDS303 transmitter has two modes of operation controlled by link-select terminal LS. Table 3 shows the serializer modes of operation. Table 3. Logic Table: Link Select Operating Modes LS Mode of Operation Data Links Status 0 1-channel mode, 1ChM (30-bit serialization rate) D0 active; D1 high-impedance 1 2-channel mode, 2ChM (15-bit serialization rate) D0, D1 active 1-Channel Mode While LS is held low, the SN65LVDS303 transmits payload data over a single SubLVDS data pair, D0. The PLL locks to PCLK and internally multiplies the clock by a factor of 30. The internal high-speed clock is used to serialize (shift out) the data payload on D0. Two reserved bits and the parity bit are added to the data frame. Figure 3 illustrates the timing and the mapping of the data payload into the 30-bit frame. The internal high-speed clock is divided by a factor of 30 to recreate the pixel clock, and presented on the SubLVDS CLK output. While in this mode, the PLL can lock to a clock that is in the range of 4 MHz through 15 MHz. This mode is intended for smaller video display formats (e.g. QVGA to HVGA) that do not require the full bandwidth capabilities of the SN65LVDS303. CLK– CLK+ D0 +/– CHANNEL 0 0 CP R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 VS HS DE 0 0 CP R7 R6 Figure 3. Data and Clock Output in 1-Channel Mode (LS = Low). 2-Channel Mode While LS is held high, the SN65LVDS303 transmits payload data over two SubLVDS data pairs, D0 and D1. The PLL locks to PCLK and internally multiplies it by a factor of 15. The internal high-speed clock is used to serialize the data payload on D0 and D1. Two reserved bits and the parity bit are added to the data frame. Figure 4 illustrates the timing and the mapping of the data payload into the 30-bit frame and how the frame becomes split into the two output channels. The internal high-speed clock is divided by 15 to recreate the pixel clock and presented on SubLVDS CLK. The PLL can lock to a clock that is in the range of 8 MHz through 30 MHz in this mode. Typical applications for using the 2-channel mode are HVGA and VGA displays. CLK– CLK + D0 +/– Channel CP R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 VS 0 CP R7 R6 D1 +/– Channel 0 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 HS DE 0 G3 G2 Figure 4. Data and Clock Output in 2-Channel Mode (LS = High). Power-Down Modes The SN65LVDS303 transmitter has two power-down modes to facilitate efficient power management. Shutdown Mode The SN65LVDS303 enters shutdown mode when the TXEN terminal is asserted low. This turns off all transmitter circuitry, including the CMOS input, PLL, serializer, and SubLVDS transmitter output stage. All outputs are high-impedance. Current consumption in shutdown mode is nearly zero. Submit Documentation Feedback 7 SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 Standby Mode The SN65LVDS303 enters the standby mode if TXEN is high and the PCLK input signal frequency is less than 500 kHz. All circuitry except the PCLK input monitor is shut down, and all outputs enter the high-impedance state. The current consumption instandby mode is very low. When the PCLK input signal is completely stopped, the IDD current consumption is less than 10 µA. The PCLK input must not be left floating. NOTE: A floating (left open) CMOS input allows leakage currents to flow from VDD to GND. To prevent large leakage current, a CMOS gate must be kept at a valid logic level, either VIH or VIL. This can be achieved by applying an external voltage of VIH or VIL to all SN65LVDS303 inputs. Active Modes When TXEN is high and the PCLK input clock signal is faster than 3 MHz, the SN65LVDS303 enters the active mode. Current consumption in the active mode depends on operating frequency and the number of data transitions in the data payload. Acquire Mode (PLL Approaches Lock) The PLL is enabled and attempts to lock to the input clock. All outputs remain in the high-impedance state. When the PLL monitor detects stable PLL operation, the device switches from the acquire mode to the transmit mode. For proper device operation, the pixel clock frequency must fall within the valid fPCLK range specified under recommended operating conditions. If the pixel clock frequency is higher than 3 MHz but lower than fPCLK(min), the SN65LVDS303 PLL is enabled. Under such conditions, it is possible for the PLL to lock temporarily to the pixel clock, causing the PLL monitor to release the device into transmit mode. If this happens, the PLL may or may not be properly locked to the pixel clock input, potentially causing data errors, frequency oscillation, and PLL deadlock (loss of VCO oscillation). Transmit Mode After the PLL achieves lock, the device enters the normal transmit mode. The CLK terminal outputs a copy of PCLK. Based on the selected mode of operation, the D0 and D1 outputs carry the serialized data. In 1-channel mode, the D1 outputs remain in the high-impedance state. Parity Bit Generation The SN65LVDS303 transmitter calculates the parity of the transmit data word and sets the parity bit accordingly. The parity bit covers the 27-bit data payload consisting of 24 bits of pixel data plus VS, HS and DE. The two reserved bits are not included in the parity generation. Odd-parity bit signaling is used. The transmitter sets the parity bit if the sum of the 27 data bits results in an even number of ones. The parity bit is cleared otherwise. This allows the receiver to verify parity and detect single bit errors. 8 Submit Documentation Feedback SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 Status Detect and Operating Modes Flow diagram The SN65LVDS303 switches between the power saving and active modes in the following way: Power Up TXEN = 0 Power Up TXEN = 1 CLK Inactive TXEN Low > 10 ms Shutdown Mode TXEN High > 10 ms PCLK Stops or Lost TXEN Low > 10 ms TXEN Low > 10 ms Standby Mode Transmit Mode PCLK Stops or Lost PCLK Active PLL Achieved Lock Power Up TXEN = 1 CLK Active Acquire Mode Figure 5. Status Detect and Operating Modes Flow Diagram Table 4. Status Detect and Operating Modes Descriptions Mode Characteristics consumption (1) Conditions Shutdown mode Least amount of power off); all outputs are high-impedance. Standby mode Low power consumption (only clock activity circuit active; PLL TXEN is high; PCLK input signal is missing or is disabled to conserve power); all outputs are inactive. (2) high-impedance. Acquire mode PLL tries to achieve lock; all outputs are high-impedance. TXEN is high; PCLK input monitor detected input activity. Transmit mode Data transfer (normal operation); transmitter serializes data and transmits data on serial output; unused outputs remain high-impedance. TXEN is high and PLL is locked to incoming clock. (1) (2) (most circuitry turned TXEN is low. (1) (2) In shutdown mode, all SN65LVDS303 internal switching circuits (e.g., PLL, serializer, etc.) are turned off to minimize power consumption. The input stage of any input terminal remains active. Leaving inputs unconnected can cause random noise to toggle the input stage and potentially harm the device. All inputs must be tied to a valid logic level VIL or VIH during shutdown or standby mode. Submit Documentation Feedback 9 SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 Table 5. Operating Mode Transitions MODE TRANSITION Shutdown → standby USE CASE TRANSITION SPECIFICS Drive TXEN high to enable transmitter 1. TXEN high > 10 µs 2. Transmitter enters standby mode. a. All outputs are high-impedance. b. Transmitter turns on clock input monitor. Standby → acquire Transmitter activity detected 1. PCLK input monitor detects clock input activity. 2. Outputs remain high-impedance. 3. PLL circuit is enabled. Acquire → transmit Link is ready to transfer data 1. PLL is active and approaches lock. 2. PLL achieved lock within 2 ms. 3. Parallel data input latches into shift register. 4. CLK output turns on. 5. Selected data outputs turn on and send out first serial data bit. Transmit → standby Request transmitter to enter standby mode by stopping PCLK 1. PCLK Input monitor detects missing PCLK. 2. Transmitter indicates standby, putting all outputs into high-impedance. 3. PLL shuts down. 4. PCLK activity input monitor remains active. Transmit/standby → shutdown 1. TXEN pulled low for longer than 10 µs Turn off transmitter 2. Transmitter indicates standby, putting output CLK+ and CLK– into high-impedance state. 3. Transmitter puts all other outputs into high-impedance state. 4. Most IC circuitry is shut down for least power consumption. ORDERING INFORMATION PART NUMBER Package SHIPPING METHOD SN65LVDS303ZQER ZQE Reel ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) Supply voltage range, VDD (2), VDDPLLA, VDDPLLD, VDDLVDS Voltage range at any input When VDDx > 0 V or output terminal When VDDx ≤ 0 V Human-body model (3) (all terminals) Electrostatic discharge Charged-device model (4) (all terminals) Machine model (5) (all terminals) Continuous power dissipation (1) (2) (3) (4) (5) 10 VALUE UNIT –0.3 to 2.175 V –0.5 to 2.175 V –0.5 to VDD + 2.175 V ±3 kV ±500 ±200 V See Dissipation Ratings table Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the GND terminals. In accordance with JEDEC Standard 22, Test Method A114-A. In accordance with JEDEC Standard 22, Test Method C101. In accordance with JEDEC Standard 22, Test Method A115-A Submit Documentation Feedback SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 DISSIPATION RATINGS (1) (2) PACKAGE CIRCUIT BOARD MODEL TA < 25°C DERATING FACTOR (1) ABOVE TA = 25°C TA = 85°C POWER RATING ZQE Low-K (2) 592 mW 7.407 mW/°C 148 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. In accordance with the low-K thermal metric definitions of EIA/JESD51-2. THERMAL CHARACTERISTICS PARAMETER PD TEST CONDITIONS Typical VDDx = 1.8 V, TA = 25°C, 2-channel mode Maximum VDDx = 1.95 V, TA = –40°C Device power dissipation VALUE PCLK at 4 MHz 14.4 PCLK at 30 MHz 38.2 PCLK at 4 MHz 22.3 PCLK = 30 MHz 50.2 UNIT mW mW RECOMMENDED OPERATING CONDITIONS (1) VDD VDDPLLA VDDPLLD VDDLVDS VDDn(PP) fPCLK Supply voltages Supply voltage noise magnitude 50 MHz (all supplies) Pixel clock frequency MIN NOM MAX UNIT 1.65 1.8 1.95 V 100 mV Test setup see Figure 11 f(noise) = 1Hz to 2 GHz 1-channel transmit mode, see Figure 3 4 15 2-channel transmit mode, see Figure 4 8 30 0.5 3 Frequency threshold, standby mode to active mode (2), see Figure 15 MHz tH× fPCLK PCLK input duty cycle 0.33 0.67 TA Operating free-air temperature –40 85 °C 5 ps-rms jitter (3) tjit(per)PCLK PCLK RMS period tjit(TJ)PCLK PCLK total jitter tjit(CC)PCLK PCLK peak cycle-to-cycle jitter (4) 0.05/fPCLK Measured on PCLK input 0.02/fPCLK s s PCLK, R[0:7], G[0:7], B[0:7], VS, HS, DE, PCLK, LS, CPOL, TXEN, SWAP VIH High-level input voltage VIL Low-level input voltage tDS Data set up time prior to PCLK transition tDH (1) (2) (3) (4) Data hold time after PCLK transition 0.7 VDD VDD V 0.3 VDD V 2 ns 2 ns f (PCLK) = 30 MHz; see Figure 7 Unused single-ended inputs must be held high or low to prevent them from floating. PCLK input frequencies lower than 500 kHz force the SN65LVDS303 into standby mode. Input frequencies between 500 kHz and 3 MHz may or may not activate the SN65LVDS303. Input frequencies beyond 3 MHz activate the SN65LVDS303. Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 100,000 cycles. Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles; over a random sample of 1,000 adjacent cycle pairs. Submit Documentation Feedback 11 SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 DEVICE ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS 1ChM IDD 2ChM MIN MAX VDD = VDDPLLA = VDDPLLD = VDDLVDS, RL(PCLK) = RL(Dx) = 100 Ω, VIH = VDD, VIL = 0 V, TXEN at VDD, alternating 1010 serial bit pattern fPCLK = 4 MHz 9 11.4 fPCLK = 6 MHz 10.6 12.6 fPCLK = 15 MHz 16 18.8 VDD = VDDPLLA = VDDPLLD= VDDLVDS, RL(PCLK) = RL(Dx) = 100 Ω, VIH = VDD, VIL = 0 V, TXEN at VDD, typical power test pattern (see Table 7) fPCLK = 4 MHz 8 fPCLK = 6 MHz 8.9 fPCLK = 15 MHz 14 VDD = VDDPLLA = VDDPLLD= VDDLVDS, RL(PCLK) = RL(Dx) = 100 Ω, VIH = VDD, VIL = 0 V, TXEN at VDD, alternating 1010 serial bit pattern fPCLK = 8 MHz 13.7 fPCLK = 22 MHz 18.4 22 fPCLK = 30 MHz 21.4 25.8 VDD = VDDPLLA = VDDPLLD= VDDLVDS, RL(PCLK) = RL(Dx) = 100 Ω, VIH = VDD, VIL = 0 V, TXEN at VDD, typical power test pattern (see Table 8) fPCLK = 8 MHz 11.5 Standby mode Shutdown mode (1) TYP (1) UNIT mA mA 15.9 mA fPCLK = 22 MHz 16 fPCLK = 30 MHz 19.1 VDD = VDDPLLA = VDDPLLD = VDDLVDS, RL(PCLK) = RL(Dx) = 100 Ω, VIH = VDD, VIL = 0 V, all inputs held static high or static low 0.61 10 µA 0.55 10 µA mA All typical values are at 25°C and with 1.8 V supply unless otherwise noted. OUTPUT ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT SubLVDS Output (D0+, D0–, D1+, D1–, CLK+, and CLK–) VOC(SS)M Steady-state common-mode output voltage VOCM(SS) Change in steady-state common-mode output voltage VOCM(PP) Peak-to-peak common mode output voltage |VOD| Differential output voltage magnitude |VDx+ – VDx– |, |VCLK+ – VCLK– | ∆|VOD| Change in differential output voltage between logic states ZOD(CLK) Differential small-signal output impedance TXEN at VDD IOSD Differential short-circuit output current VOD = 0 V, fPCLK = 28 MHz IOS Short circuit output current (2) VO = 0 V or VDD IOZ High-impedance state output current VO = 0 V or VDD(max), TXEN at GND (1) (2) Output load see Figure 9 0.8 0.9 –10 100 150 –10 1.0 V 10 mV 75 mV 200 mV 10 mV Ω 210 10 5 –3 3 MIN TYP (1) MAX mA µA All typical values are at 25°C and with 1.8-V supply, unless otherwise noted. All SN65LVDS303 outputs tolerate shorts to GND or VDD without device damage. INPUT ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT PCLK, R[0:7], G[0:7], B[0:7], VS, HS, DE, PCLK, LS, CPOL, TXEN, SWAP IIH High-level input current VIN = 0.7 × VDD –200 200 IIL Low-level input current VIN = 0.3 × VDD –200 200 CIN Input capacitance (1) 12 1.5 All typical values are at 25°C and with 1.8-V supply, unless otherwise noted. Submit Documentation Feedback nA pF SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS TYP (1) MIN MAX tr 20%-to-80% differential output signal rise time See Figure 8 and Figure 9 250 500 tf 20%-to-80% differential output signal fall time See Figure 8 and Figure 9 250 500 fBW PLL bandwidth (3dB cutoff frequency) Tested from PCLK input to CLK output, See Figure 6 (2) tpd(L) Propagation delay time, input to serial output (data latency Figure 10) TXEN at VDD, VIH=VDD, VIL=GND, RL=100 Ω tH × fCLK0 Output CLK duty cycle tGS TXEN Glitch suppression pulse duration (3) VIH = VDD, VIL = GND, TXEN toggles between VIL and VIH, see Figure 13 and Figure 14. tpwrup Enable time from power down (↑TXEN) Time from TXEN pulled high to CLK and Dx outputs enabled and transmit valid data; see Figure 14 tpwrdn Disable time from active mode (↓TXEN) TXEN is pulled low during transmit mode; time measurement until output is disabled and PLL is Shutdown; see Figure 14 twakup Enable time from standby (↕PCLK) TXEN at VDD; device in standby; time measurement from PCLK starts switching to CLK and Dx outputs enabled and transmit valid data; see Figure 14 tsleep Disable time from active mode (PCLK stopping) TXEN at VDD; device is transmitting; time measurement from PCLK input signal stops until CLK + Dx outputs are disabled and PLL is disabled; see Figure 14 (3) fPCLK = 22 MHz 0.082 fPCLK fPCLK = 30 MHz 0.078 fPCLK 1-channel mode 0.8/fPCLK 1/fPCLK 1.2/fPCLK 2-channel mode 1/fPCLK 1.21/fPCLK 1.5/fPCLK 1-channel mode 0.45 0.50 0.55 2-channel mode 0.49 0.53 0.58 MHz s 10 µs 0.24 2 ms 0.5 11 µs 0.23 2 ms 0.4 100 µs 3.8 All typical values are at 25°C and with 1.8-V supply unless otherwise noted. The Maximum Limit is based on statistical analysis of the device performance over process, voltage, and temp ranges. This parameter is functionality tested only on Automatic Test Equipment (ATE). The TXEN input incorporates glitch-suppression circuitry to disregard short input pulses. tGS is the duration of either a high-to-low or low-to-high transition that is suppressed. 12 PLL BW (% of PCLK Frequency) − % ps 11 ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ 9.0 4 MHz: 8.5% 9% 9 8.5 % 8 8.1 % 7.6 % 7 6 4 0 100 200 300 400 f − PLL Frequency − MHz 500 Spec Limit 2 ChM Spec Limit 1 ChM 8.0 7.5 15 MHz: 7.6% 7.0 30 MHz: 7.6% 6.5 TX PLL BW 5 8 MHz: 8.5% 8.5 RX PLL BW 10 PLL Bandwidth − % (1) (2) UNIT 6.0 600 0 G001 5 10 15 20 25 30 f − PCLK Frequency − MHz 35 40 G002 Figure 6. SN65LVDS303 PLL Bandwidth (Also Showing the SN65LVDS304 PLL Bandwidth) Submit Documentation Feedback 13 SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 TIMING CHARACTERISTICS PARAMETER tPPOSX Output pulse position, serial data to ↑CLK; see (1) (2)and Figure 12 TEST CONDITIONS MIN 1ChM: x = 0..29, fPCLK = 15 MHz; TXEN at VDD, VIH = VDD, VIL = GND, RL = 100 Ω, test pattern as in Table 11 (3) x - 330 ps 30 × fPCLK x + 330 ps 30 × fPCLK x – 0.1845 30 × fPCLK x + 0.1845 30 × fPCLK x - 330 ps 15 × fPCLK x + 330 ps 15 × fPCLK x – 0.1845 15 × fPCLK x + 0.1845 15 × fPCLK 1ChM: x = 0..29, fPCLK = 4 MHz to 15 MHz 2ChM: x = 0..14, fPCLK = 30 MHz TXEN at VDD, VIH = VDD, VIL = GND, RL = 100 Ω, test pattern as in Table 12 (3) 2ChM: x = 0..14, fPCLK = 8 MHz to 30 MHz (1) (2) (3) (4) (4) (4) TYP MAX ps This number also includes the high-frequency random and deterministic PLL clock jitter that is not traceable by the SN65LVDS304 receiver PLL; tPPosx represents the total timing uncertainty of the transmitter necessary to calculate the jitter budget when combined with the SN65LVDS304 receiver. The pulse position min/max variation is given with a bit error rate target of 10–12; the measurement estimates the random jitter contribution to the total jitter by multiplying the random RMS jitter by the factor 14; measurements of the total jitter are taken with > 10–12 samples. The minimum and maximum limits are based on statistical analysis of the device performance over process, voltage, and temp ranges. This parameter is functionality tested only on automatic test equipment (ATE). These minimum and maximum limits are simulated only. PARAMETER MEASUREMENT INFORMATION t DS VIH R[7:0], G[7:0], B[7:0]; VS, HS, DE, LS, TXEN, SWAP, CPOL VIL t DH VIH PCLK (CPOL = Low) VIL tR Figure 7. Setup/Hold Time VOD tf tr 150mV (nom) 80% 0V 20% −150mV (nom) Figure 8. Rise and Fall Time Definitions 14 UNIT Submit Documentation Feedback SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 PARAMETER MEASUREMENT INFORMATION (continued) R1 = 49.9 W CLK+, Dx+ VDx+ or VCLK+ 975 mV (Nom) VDx– or VCLK– 825 mV (Nom) VOD VOCM CLK–, Dx– VOCM R2 = 49.9 W SN65LVDS303 C3 = 1 pF C1 = 1 pF VOCM (pp) VOCM (ss) C2 = 1 pF NOTES: A. 20-MHz output test pattern on all differential outputs (CLK, D0, and D1): this is achieved by: 1. Device is set to 2-channel mode. 2. fPCLK = 20 MHz 3. Inputs R[7:3] = B[7:3] connected to VDD, all other data inputs set to GND. B. C1, C2, and C3 include instrumentation and fixture capacitance, tolerance ±20%; C, R1, and R2 tolerance ±1% C. The measurement of VOCM (pp) and VOC(ss) are taken with test equipment bandwidth >1 GHz. Figure 9. Driver Output Voltage Test Circuit and Definitions CMOS Data In pixel (n) pixel (n+1) R7(n−1) R7(n) R7(n+1) R6(n−1) R6(n) R6(n+1) VDD /2 PCLK t PROP CLK− CLK+ D0+ CP R7 R6 CP R7 R6 pixel (n−1) pixel (n−2) R6(n−1) R7(n−1) R7(n) R6(n) Figure 10. tpd(L) Propagation Delay Input to Output (LS = 0; CPOL = 0) 1 Noise Generator 100 mV SN65LVDS303 V DDPLLD V DDPLLA 2 1 VDD 10 mF V DDLVDS GND Note: The generator regulates the noise amplitude at point 1 to the target amplitude given under the table Recommended Operating Conditions 1.8-V Supply Figure 11. Power Supply Noise Test Setup Submit Documentation Feedback 15 SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 PARAMETER MEASUREMENT INFORMATION (continued) tCLK+ CLK– CLK+ Current Cycle D[0:m]± Bit 0 Bit1 Next Cycle Bitx Bit2 Bit0 Bit1 tPPOS0 tPPOS1 Note: 1-Channel Mode: x = 0...29; m = 0 2-Channel Mode: x = 0...14; m = 1 tPPOS2 tPPOSx Figure 12. tSK(0) SubLVDS Output Pulse Position Measurement VDD/2 TXEN t GS PCLK VCO Internal Signal PLL Approaches Lock t pwrup CLK D0, D1 Figure 13. Transmitter Behavior While Approaching Sync 16 Submit Documentation Feedback SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 PARAMETER MEASUREMENT INFORMATION (continued) Figure 14. Transmitter Enable Glitch Suppression Time PCLK twakeup tsleep CLK+ Transmitter Disabled (OFF) Transmitter Aquires Lock, Outputs Still Disabled Transmitter Enabled, Output Data Valid Transmitter Enabled, Output Data Valid Transmitter Disabled (OFF) Figure 15. Standby Detection Power Consumption Tests Table 6 shows an example test pattern word. Table 6. Example Test Pattern Word 7 Word R[7:4], R[3:0], G[7:4], G[3:0], B[7:4], B[3:0], 0, VS, HS, DE 1 0x7C3E1E7 C 3 E 1 R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 E 7 B6 B5 B4 B3 B2 B1 B0 0 0 0 1 1 1 1 0 0 0 VS HS DE 1 1 1 Typical IC Power-Consumption Test Pattern The typical power-consumption test patterns consists of 16 30-bit transmit words in 1-channel mode, eight 30-bit transmit words in 2-channel mode. The pattern repeats itself throughout the entire measurement. It is assumed that every possible transmit code on RGB inputs has the same probability to occur during typical device operation. Submit Documentation Feedback 17 SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 Table 7. Typical IC Power-Consumption Test Pattern, 1-Channel Mode Word Test Pattern: R[7:4], R[3:0], G[7:4], G[3:0], B[7:4], B[3:0], 0, VS, HS, DE 1 0x0000007 2 0xFFF0007 3 0x01FFF47 4 0xF0E07F7 5 0x7C3E1E7 6 0xE707C37 7 0xE1CE6C7 8 0xF1B9237 9 0x91BB347 10 0xD4CCC67 11 0xAD53377 12 0xACB2207 13 0xAAB2697 14 0x5556957 15 0xAAAAAB3 16 0xAAAAAA5 Table 8. Typical IC Power Consumption Test Pattern, 2-Channel Mode Word Test Pattern: R[7:4], R[3:0], G[7:4], G[3:0], B[7:4], B[3:0], 0, VS, HS, DE 1 0x0000001 2 0x03F03F1 3 0xBFFBFF1 4 0x1D71D71 5 0x4C74C71 6 0xC45C451 7 0xA3AA3A5 8 0x5555553 Maximum Power Consumption Test Pattern The maximum (or worst-case) power consumption of the SN65LVDS303 is tested using the two different test pattern shown in table. test patterns consists of sixteen 30-bit transmit words in 1-channel mode, eight 30-bit transmit words in 2-channel mode. The pattern repeats itself throughout the entire measurement. It is assumed that every possible transmit code on RGB inputs has the same probability to occur during typical device operation. Table 9. Worst-Case Power Consumption Test Pattern Word 18 Test Pattern: R[7:4], R[3:0], G[7:4], G[3:0], B[7:4], B[3:0], 0, VS, HS, DE 1 0xAAAAAA5 2 0x5555555 Submit Documentation Feedback SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 Table 10. Worst-Case Power Consumption Test Pattern Word Test Pattern: R[7:4], R[3:0], G[7:4], G[3:0], B[7:4], B[3:0], 0, VS, HS, DE 1 0x0000000 2 0xFFFFFF7 Output Skew Pulse Position and Jitter Performance The following test patterns are used to measure the output skew pulse position and the jitter performance of the SN65LVDS303. The jitter test patterns stress the interconnect for worst-case ISI. Each pattern is self-repeating for the duration of the test. Table 11. Transmit Jitter Test Pattern, 1-Channel Mode Word Test Pattern: R[7:4], R[3:0], G[7:4], G[3:0], B[7:4], B[3:0], 0, VS, HS, DE 1 0x0000001 2 0x0000031 3 0x00000F1 4 0x00003F1 5 0x0000FF1 6 0x0003FF1 7 0x000FFF1 8 0x0F0F0F1 9 0x0C30C31 10 0x0842111 11 0x1C71C71 12 0x18C6311 13 0x1111111 14 0x3333331 15 0x2452413 16 0x22A2A25 17 0x5555553 18 0xDB6DB65 19 0xCCCCCC1 20 0xEEEEEE1 21 0xE739CE1 22 0xE38E381 23 0xF7BDEE1 24 0xF3CF3C1 25 0xF0F0F01 26 0xFFF0001 27 0xFFFC001 28 0xFFFF001 29 0xFFFFC01 30 0xFFFFF01 31 0xFFFFFC1 32 0xFFFFFF1 Submit Documentation Feedback 19 SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 Table 12. Transmit Jitter Test Pattern, 2-Channel Mode Word 20 Test Pattern: R[7:4], R[3:0], G[7:4], G[3:0], B[7:4], B[3:0], 0, VS, HS, DE 1 0x0000001 2 0x000FFF3 3 0x8008001 4 0x0030037 5 0xE00E001 6 0x00FF001 7 0x007E001 8 0x003C001 9 0x0018001 10 0x1C7E381 11 0x3333331 12 0x555AAA5 13 0x6DBDB61 14 0x7777771 15 0x555AAA3 16 0xAAAAAA5 17 0x5555553 18 0xAAA5555 19 0x8888881 20 0x9242491 21 0xAAA5571 22 0xCCCCCC1 23 0xE3E1C71 24 0xFFE7FF1 25 0xFFC3FF1 26 0xFF81FF1 27 0xFE00FF1 28 0x1FF1FF1 29 0xFFCFFC3 30 0x7FF7FF1 31 0xFFF0007 32 0xFFFFFF1 Submit Documentation Feedback SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 TYPICAL CHARACTERISTICS POWERDOWN, STANDBY SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT IDD vs TEMPERATURE 1 20 IDD − Supply Current − mA IDDQ − Supply Current − µA 2-Channel Mode, 22 MHz (VGA) Standby Current Power−Down Current 0.1 −50 −30 −10 10 30 50 T − Temperature − °C 70 15 2-Channel Mode, 11 MHz (HVGA) 10 5 0 −50 90 −30 G003 Figure 16. 10 30 50 T − Temperature − °C 70 90 G004 Figure 17. SUPPLY CURRENT vs PCLK FREQUENCY DIFFERENTIAL OUTPUT SWING vs PCLK FREQUENCY 200 VOD − Differential Output Swing − mV 30 IDD − Supply Current − mA −10 25 20 2-Channel Mode 15 10 1-Channel Mode 5 190 85°C 180 170 –40°C 160 25°C 150 140 130 120 110 100 0 5 10 15 20 f − PCLK Frequency − MHz 25 30 0 5 G005 10 15 20 f − PCLK Frequency − MHz 25 G006 Figure 18. Figure 19. PLL BANDWIDTH CYCLE-TO-CYCLE OUTPUT JITTER vs PCLK FREQUENCY 10.0 30 500 9.5 Spec Limit 1 ChM 4 MHz: 8.5% Spec Limit 2 ChM 8 MHz: 8.5% 8.5 400 CC Output Jitter − ps PLL Bandwidth − % 9.0 8.0 7.5 Spec Limit 1 ChM 15 MHz: 7.6% 7.0 Spec Limit 2 ChM 30 MHz: 7.6% 6.5 6.0 300 200 100 2-ChM 5.5 1-Channel Mode 5.0 2-Channel Mode 0 0 5 10 15 20 25 30 f − PCLK Frequency − MHz 35 40 0 G007 Figure 20. 5 10 15 20 f − PCLK Frequency − MHz 25 30 G008 Figure 21. Submit Documentation Feedback 21 SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 TYPICAL CHARACTERISTICS (continued) CYCLE-TO-CYCLE OUTPUT JITTER vs TEMPERATURE OUTPUT PULSE POSITION vs TEMPERATURE 120 tPPOS − Output Pulse Position − ps CC Output Jitter − ps 200 2-Channel Mode, f(PCLK) = 11 MHz 150 100 1-Channel Mode, f(PCLK) = 22 MHz 50 0 −50 −25 0 25 50 T − Temperature − °C 75 2-Channel Mode, 11 MHz (VGA) 100 80 60 2-Channel Mode, 22 MHz (HVGA) 40 20 0 −50 100 −25 0 25 50 T − Temperature − °C G009 Figure 22. OUTPUT RETURN LOSS Output Common-Mode Noise Rejection − dB Output Return Loss − dB D0 −10 D1 −15 500 1000 f − Frequency − MHz 1500 0 −5 D0 CLK −10 D1 −15 −20 2000 0 500 G011 1000 f − Frequency − MHz Figure 24. Figure 25. CROSSTALK 0 Isolation − dB −20 −40 D0 to D1 −60 −80 −100 0 500 1000 f − Frequency − MHz 1500 Figure 26. 22 G010 OUTPUT COMMON MODE NOISE REJECTION −5 0 100 Figure 23. 0 CLK 75 Submit Documentation Feedback 2000 G013 1500 2000 G012 SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 APPLICATION INFORMATION Preventing Increased Leakage Currents in Control Inputs A floating (left open) CMOS input allows leakage currents to flow from VDD to GND. Do not leave any CMOS input unconnected or floating. Every input must be connected to a valid logic level, VIH or VIL, while power is supplied to VDD. This also minimizes the power consumption of standby and power-down modes. Power Supply Design Recommendation For a multilayer PCB, it is recommended to keep one common GND layer underneath the device and connect all ground terminals directly to this plane. Decoupling Recommendation The SN65LVDS303 was designed to operate reliably in a constricted environment with other digital switching ICs. In cell phone designs, the SN65LVDS303 often shares a power supply with the application processor. The SN65LVDS303 can operate with power supply noise as specified in Recommend Device Operating Conditions. To minimize the power-supply noise floor, provide good decoupling near the SN65LVDS303 power terminals. The use of four ceramic capacitors (2 × 0.01 µF and 2 × 0.1 µF) provides good performance. At the very least, it is recommended to install one 0.1 µF and one 0.01 µF capacitor near the SN65LVDS303. To avoid large current loops and trace inductance, the trace length between decoupling capacitor and IC power inputs terminals must be minimized. Placing the capacitor underneath the SN65LVDS303 on the bottom of the PCB is often a good choice. VGA Application Figure 27 shows a possible implementation of a VGA display. The SN65LVDS303 interfaces to the SN65LVDS304, which is the corresponding receiver device to deserialize the data and drive the display driver. The pixel clock rate of 22 MHz assumes ~10% blanking overhead and 60-Hz display refresh rate. The application assumes 24-bit color resolution. It is also shown how the application processor provides a power-down (reset) signal for both serializer and the display driver. The signal count over the FPC could be further decreased by using the standby option on the SN65LVDS304 and pulling RXEN high with a 30-kΩ resistor to VDD. 2 ´ 0.01 mF 1.8 V GND GND D1+ D1– 330 Mbps LS 1.8 V Serial Port Interface (3-Wire IF) R[7:0] G[7:0] B[7:0] HS, VS, DE SN65LVDS304 TXEN LS SPI RESET SN65LVDS303 D1+ D1– 22 MHz PCLK 27 LCD With VGA Resolution 330 Mbps CLK+ CLK– D0+ D0– ENABLE R[7:0] G[7:0] B[7:0] HS, VS, DE 22 MHz Video Mode Display Driver SPI PCLK 27 2.7 V 1.8 V RXEN D[7:0] D[15:8] D[23:16] HS, VS, DE 2.7 V CLK+ CLK– D0+ D0– 22 MHz Pixel CLK 2 ´ 0.1 mF GND 2 ´ 0.01 mF VDDx Application Processor (e.g. OMAP) GND FPC VDDx GND GND 2 ´ 0.1 mF 1.8 V If FPC wire count is critica, replace this connection with a pull-up resistor at RXEN 3 Figure 27. Typical VGA Display Application Submit Documentation Feedback 23 SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 APPLICATION INFORMATION (continued) Typical Application Frequencies The SN65LVDS303 supports pixel clock frequencies from 4 MHz to 30 MHz over one or two data pairs. Table 13 provides a few typical display resolution examples and shows the number of data pairs necessary to connect the LVDS303 with the display. The blanking overhead is assumed to be 20%. Often, blanking overhead is smaller, resulting in a lower data rate. Futhermore, the examples in the table assume a display frame refresh rate of 60-HZ or 90-Hz. The actual refresh rate may differ depending on the application-processor clock implementation. Table 13. Typical Application Data Rates and Serial Pair Usage Display Screen Resolution 176 × 220 (QCIF+) Visible Pixel Count Blanking Overhead Display Refresh Rate Pixel Clock Frequency [MHz] Serial Data Rate Per Pair 38,720 20% 90 Hz 4.2 MHz 125 Mbps 60 Hz 1-ChM 2-ChM 240 × 320 (QVGA) 76,800 5.5 MHz 166 Mbps 640 × 200 128,000 9.2 MHz 276 Mbps 138 Mbps 352 × 416 (CIF+) 146,432 10.5 MHz 316 Mbps 158 Mbps 352 × 440 154,880 11.2 MHz 335 Mbps 167 Mbps 320 × 480 (HVGA) 153,600 11.1 MHz 332 Mbps 166 Mbps 800 × 250 200,000 14.4 MHz 432 Mbps 216 Mbps 640 × 320 204,800 14.7 MHz 442 Mbps 221 Mbps 640 × 480 (VGA) 307,200 22.1 MHz 332 Mbps 1024 × 320 327,680 23.6 MHz 354 Mbps 854 × 480 (WVGA) 409,920 29.5 MHz 443 Mbps 24 Submit Documentation Feedback SN65LVDS303 www.ti.com SLLS743A – JULY 2006 – REVISED JANUARY 2007 Calculation Example: HVGA Display Display resolution: 480 × 320 Frame refresh rate: 58.4 Hz Vertical visible pixels: 320 lines Vertical front porch: 10 lines Vertical sync: 5 lines Vertical back porch: 3 lines Horizontal visible pixels: 480 columns Horizontal front porch: 20 columns Horizontal sync: 5 columns Horizontal back porch: 3 columns Hsync = 5 HBP This example calculation shows a typical half-VGA display with these parameters: Visible area = 480 column HFP = 20 Vsync = 5 VBP = 3 Visible area = 320 lines Visible area VFP = 10 Entire display Figure 28. HVGA Display Parameters Calculation of the total number of pixels and blanking overhead: Visible area pixel count: 480 × 320 = 153,600 pixels Total frame pixel count: (480 + 20 + 5 + 3) × (320 + 10 + 5 + 3) = 171,704 pixels Blanking overhead: (171,704 – 153,600) ÷ 153,600 ≈ 11.8% The application requires following serial-link parameters: Pixel clock frequency: 171,704 × 58.4 Hz = 10 MHz Serial data rate: 1-channel mode: 10 MHz × 30 bits/channel = 300 Mbps 2-channel mode: 10 MHz × 15 bits/channel = 150 Mbps Submit Documentation Feedback 25 PACKAGE OPTION ADDENDUM www.ti.com 5-Jan-2007 PACKAGING INFORMATION Orderable Device Status (1) SN65LVDS303ZQER ACTIVE Package Type BGA MI CROSTA R JUNI OR Package Drawing ZQE Pins Package Eco Plan (2) Qty 80 2500 Green (RoHS & no Sb/Br) Lead/Ball Finish SNAGCU MSL Peak Temp (3) Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 7-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device SN65LVDS303ZQER 7-May-2007 Package Pins ZQE 80 Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) TAI 330 12 5.3 5.3 1.5 8 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN65LVDS303ZQER ZQE 80 TAI 342.9 336.6 20.64 Pack Materials-Page 2 W Pin1 (mm) Quadrant 12 NONE IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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