SN65LVDS308 www.ti.com SLLS835 – MAY 2007 PROGRAMMABLE 27-BIT PARALLEL-TO-SERIAL RECEIVER FEATURES • • • • • • • • • • • FlatLink 3G Serial Interface Technology Compatible With FlatLink™ 3G Transmitters Such as SN65LVDS307 Supports Video Interfaces up to 24-Bit RGB Data and 3 Control Bits Received Over Two Differential Data Lines SubLVDS Differential Voltage Levels Up to 810-Mbps Data Throughput Three Operating Modes to Conserve Power – Active mode VGA 60 fps: 17 mW – Typical Shutdown: 0.7 µW – Typical Standby Mode: 67 µW Typical ESD Rating > 4 kV (HBM) Pixel-Clock Range of 8 MHz–30 MHz Failsafe on all CMOS Inputs 4-mm × 4-mm MicroStar Junior™µBGA® Package With 0,5-mm Ball Pitch Very Low EMI When receiving, the PLL locks to the incoming clock, CLK, and generates an internal high-speed clock at the line rate of the data lines. The data is serially loaded into a shift register using the internal high-speed clock. The deserialized data is presented on the parallel output bus with a recreation of the pixel clock, PCLK, generated from the internal high-speed clock. If no input CLK signal is present, the output bus is held static with PCLK and DE held low, while all other parallel outputs are pulled high. The F/S control input selects between a slow CMOS bus output rise time for best EMI and power consumption and a fast CMOS output for increased speed or higher-load designs. Flatlinkä3G LCD Driver LVDS308 CLK APPLICATIONS • • • Small Low-Emission Interface Between Graphics Controller and LCD Display Mobile Phones and Smart Phones Portable Multimedia Players DESCRIPTION The SN65LVDS308 receiver deserializes FlatLink 3G-compliant serial input data to 27 parallel data outputs. The SN65LVDS308 receiver contains one shift register to load 30 bits from two serial inputs and latches the 24 pixel bits and 3 control bits out to the parallel CMOS outputs after checking the parity bit. If a parity error is detected, the data output bus disregards the newly received pixel. Instead, the last data word is held on the output bus for another clock cycle. DATA LVDS307 1 2 3 4 5 6 7 8 9 * 0 # Application Processor with RGB Video Interface M0056-03 The serial data and clock are received via sub-low-voltage differential signalling (SubLVDS) lines. The SN65LVDS308 supports three operating power modes (shutdown, standby, and active) to conserve power. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FlatLink, MicroStar Junior are trademarks of Texas Instruments. µBGA is a registered trademark of Tessera, Inc. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated SN65LVDS308 www.ti.com SLLS835 – MAY 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The RXEN input can be used to put the SN65LVDS308 in a shutdown mode. The SN65LVDS308 enters an active standby mode if the common-mode voltage of the CLK input becomes shifted to VDDLVDS (e.g., the transmitter releases the CLK output into high-impedance). This minimizes power consumption without the need of switching an external control pin. The SN65LVDS308 is characterized for operation over ambient air temperatures of –40°C to 85°C. All CMOS and SubLVDS signals are 2-V tolerant with VDD = 0 V. This feature allows powering up I/Os before VDD is stabilized. FUNCTIONAL BLOCK DIAGRAM VDDLVDS RBBDC iPCLK D0+ 50 Parity Check SubLVDS 50 F/S AND D0– 8 50 SubLVDS D1– 27-Bit Parallel Register D1+ 50 R[0:7] 8 G[0:7] 0 Output Buffer VDDLVDS Serial-to-Parallel Conversion RBBDC 1 RGB = 1 HS = VS = 1 DE = 0 VDDLVDS 8 B[0:7] HS VS Standby or Pwr Down DE RBBDC CLK+ ´15 50 50 PLL Multiplier SubLVDS CLK– ´1 0 PCLK 1 Standby Vthstby RXEN Glitch Suppression Control B0177-03 2 Submit Documentation Feedback SN65LVDS308 www.ti.com SLLS835 – MAY 2007 PINOUT – TOP VIEW ZQC PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 B4 B6 B7 G1 G3 G5 GND B2 B3 B5 G2 G4 G7 R0 B0 GND G0 G6 R1 VDD GNDPLLD VDD VDDPLLD B1 R3 R5 R2 D1+ D1– VDDPLLA RXEN PCLK R7 R4 TST CLK– D0+ VS HS R6 GNDPLLA D0– DE VDD F/S A B C D E F GNDLVDS (Tie to GND) G VDDLVDS CLK+ P0063-02 Submit Documentation Feedback 3 SN65LVDS308 www.ti.com SLLS835 – MAY 2007 PINOUT – TOP VIEW (continued) Table 1. Numeric Terminal List TERMINAL 4 SIGNAL TERMINAL SIGNAL TERMINAL SIGNAL TERMINAL SIGNAL A1 B4 B7 R0 D6 R5 F5 VS A2 B6 C1 B0 D7 R2 F6 HS A3 B7 C2 GND E1 D1+ F7 R6 A4 G1 C3 – E2 D1– G1 VDDLVDS A5 G3 C4 G0 E3 VDDPLLA G2 CLK+ A6 G5 C5 G6 E4 RXEN G3 GNDPLLA A7 GND C6 R1 E5 PCLK G4 D0– B1 B2 C7 VDD E6 R7 G5 DE B2 B3 D1 GNDPLLD E7 R4 G6 VDD B3 B5 D2 VDD F1 GNDLVDS G7 F/S B4 G2 D3 VDDPLLD F2 TST B5 G4 D4 B1 F3 CLK– B6 G7 D5 R3 F4 D0+ Submit Documentation Feedback SN65LVDS308 www.ti.com SLLS835 – MAY 2007 Table 2. TERMINAL FUNCTIONS NAME I/O D0+, D0– D1+, D1– DESCRIPTION SubLVDS data link SubLVDS in SubLVDS data link CLK+, CLK– SubLVDS input pixel clock; polarity is fixed. R0–R7 Red-pixel data (8) G0–G7 Green-pixel data (8) B0–B7 HS Blue-pixel data (8) CMOS out Horizontal sync VS Vertical sync DE Data enable PCLK Output pixel clock (rising clock polarity) Disables the CMOS Drivers and Turns Off the PLL, putting device in shutdown mode 1 – Receiver enabled 0 – Receiver disabled (shutdown) RXEN CMOS in Note: The RXEN input incorporates glitch suppression logic to avoid unwanted switching. The input must be pulled low for longer than 10 µs continuously to force the receiver to enter shutdown. The input must be pulled high for at least 10 µs continuously to activate the receiver. An input pulse shorter than 5 µs is interpreted as a glitch and becomes ignored. At power up, the receiver is enabled immediately if RXEN = H and disabled if RXEN = L. CMOS bus rise time select F/S 1 – fast-output rise time 0 – slow-output rise time TST Test – this input is used for TI internal test purposes only and must be tied permanently to VSS. VDD Supply voltage GND Supply ground VDDLVDS SubLVDS I/O supply voltage GNDLVDS VDDPLLA Power supply SubLVDS ground PLL analog supply voltage GNDPLLA PLL analog GND VDDPLLD PLL digital supply voltage GNDPLLD PLL digital GND Submit Documentation Feedback 5 SN65LVDS308 www.ti.com SLLS835 – MAY 2007 FUNCTIONAL DESCRIPTION The SN65LVDS308 receives payload data over two SubLVDS data pairs, D0 and D1. The PLL locks to the SubLVDS clock input and internally multiplies the clock by a factor of 15. The internal high-speed clock is used to shift in the data payload on D0 and D1 and to deserialize 15 bits of data from each pair. Figure 1 illustrates the timing and the mapping of the data payload into the 30-bit frame. The internal high-speed clock is divided by a factor of 15 to recreate the pixel clock, and the data payload with pixel clock is presented on the output bus. The reserved bits and parity bit are not output. CLK– CLK + D0+/– Channel CP R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 VS res CP R7 R6 D1+/– Channel res G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 HS DE res G3 G2 T0162-01 Figure 1. Data and Clock Input POWER-DOWN MODES The SN65LVDS308 receiver has two power-down modes to facilitate efficient power management. Shutdown Mode A low input signal on the RXEN pin puts the SN65LVDS308 into shutdown mode. This turns off most of the receiver circuitry, including the SubLVDS receivers, PLL, and deserializers. The SubLVDS differential-input resistance remains 100 Ω, and any input signal is ignored. All outputs hold a static output pattern: R[0:7] = G[0:7] = B[0:7] = VS = HS = high; DE = PCLK = low. The current draw in shutdown mode is nearly zero if the SubLVDS inputs are left open or pulled high. Standby Mode The SN65LVDS308 enters the standby mode when the SN65LVDS308 is not in shutdown mode but the clock-input common-mode voltage on the SubLVDS clock input is above 0.9 × VDDLVDS. The CLK input incorporates pullup circuitry. This circuit shifts the SubLVDS clock-input common-mode voltage to VDDLVDS in the absence of an input signal. All circuitry except the SubLVDS clock-input standby monitor is shut down. The SN65LVDS308 also enters the standby mode when the input clock frequency on the CLK input is less than 500 kHz. The SubLVDS input resistance remains 100 Ω, and any input signal on data inputs D0 and D1 is ignored. All outputs hold a static output pattern: R[0:7] = G[0:7] = B[0:7] = VS = HS = high; DE = PCLK = low. The current draw in standby mode is very low. ACTIVE MODES A high input signal on RXEN combined with a CLK input signal switching faster than 3 MHz and VICM smaller than 0.9 VDD forces the SN65LVDS308 into the active mode. Current consumption in the active mode depends on operating frequency and the number of data transitions in the data payload. CLK-input frequencies between 3 MHz and 8 MHz activate the device, but proper PLL functionality is not assured. Acquire Mode (PLL Approaches Lock) When the SN65LVDS308 is enabled and a SubLVDS clock input is present, the PLL pursues lock to the input clock. While the PLL pursues lock, the output data bus holds a static output pattern: R[0:7] = G[0:7] = B[0:7] = VS = HS = high; DE = PCLK = low. 6 Submit Documentation Feedback SN65LVDS308 www.ti.com SLLS835 – MAY 2007 FUNCTIONAL DESCRIPTION (continued) For proper device operation, the pixel clock frequency must fall within the valid fPCLK range specified under recommended operating conditions. If the pixel clock frequency is larger than 3 MHz but smaller than fPCLK(min), the SN65LVDS308 PLL is enabled. Under such conditions, it is possible for the PLL to lock temporarily to the pixel clock, causing the PLL monitor to release the device into active receive mode. If this happens, the PLL may or may not be properly locked to the pixel clock input, potentially causing data errors, frequency oscillation, and PLL deadlock (loss of VCO oscillation). Receive Mode After the PLL achieves lock the device enters the normal receive mode. The output data bus presents the deserialized data. The PCLK output pin outputs the recovered pixel clock. PARITY ERROR DETECTION AND HANDLING The SN65LVDS308 receiver performs error checking on the basis of a parity bit that is transmitted across the SubLVDS interface from the transmitting device. Once the SN65LVDS308 detects the presence of the clock and the PLL has locked onto PCLK, then the parity is checked. Parity-error detection ensures detection of all single-bit errors in one pixel and 50% of all multibit errors. The parity bit covers the 27-bit data payload consisting of 24 bits of pixel data plus VS, HS, and DE. Odd-parity bit signalling is used. If the sum of the 27 data bits and the parity bit is an odd number, the receive data are assumed to be valid. If the sum equals an even number, parity error is declared. If a parity error is detected, then the data on that PCLK cycle is not output. Instead, the last valid data from a previous PCLK cycle is repeated on the output bus. This is to prevent any bit error that occurs on the LVDS link from causing perturbations in VS, HS, or DE that might be visually disruptive to a display. The reserved bits are not covered in the parity calculations. R[0:7], G[0:7], B[0:7], HS, VS, DE PCLK When a parity error is detected, the receiver outputs the previous pixel on the bus. Hence, no data transitions occur. T0163-02 Figure 2. Output Response When Parity Error Is Detected Submit Documentation Feedback 7 SN65LVDS308 www.ti.com SLLS835 – MAY 2007 FUNCTIONAL DESCRIPTION (continued) STATUS-DETECT AND OPERATING-MODES FLOW DIAGRAM The SN65LVDS308 switches between the power saving and active modes in the following way: Power Up RXEN = 1 CLK Input Inactive RXEN Low for > 10 ms Power Up RXEN = 0 Shutdown Mode Standby Mode RXEN High for > 10 ms VICM(CLK) > 0.9 VDDLVDS RXEN Low for > 10 ms VICM(CLK) > 0.9 VDDLVDS or fCLK < 500 kHz CLK Input Active Power Up RXEN = 1 CLK Active RXEN Low for > 10 ms Receive Mode PLL Achieved Lock Acquire Mode F0017-01 Figure 3. Operating Modes Flow Diagram Table 3. Status Detect and Operating Modes Descriptions MODE CONDITIONS Least amount of power consumption (most circuitry turned off); all outputs held static: R[0:7] = G[0:7] = B[0:7] = VS = HS = high; DE = PCLK = low RXEN is set low for longer than 10 µs. Standby mode Low power consumption (standby monitor circuit active; PLL is shut down to conserve power); All outputs held static: R[0:7] = G[0:7] = B[0:7] = VS = HS = high; DE = PCLK = low RXEN is high for longer than 10 µs and both CLK inputs are common-mode, VICM(CLK) is above 0.9 × VDDLVDS, or CLK inputs are floating (2) Acquire mode PLL pursues lock; all outputs held static: R[0:7] = G[0:7] = B[0:7] = VS = HS = high; DE = PCLK = low RXEN is high; CLK input monitor detected clock input common mode and woke up receiver from standby mode. Receive mode Data transfer (normal operation); receiver deserializes data and provides data on parallel output RXEN is high and PLL is locked to incoming clock. (1) (2) 8 CHARACTERISTICS Shutdown mode (1) (2) In shutdown mode, all SN65LVDS308 internal switching circuits (e.g., PLL, serializer, etc.) are turned off to minimize power consumption. The input stage of any input pin remains active. Leaving inputs unconnected can cause random noise to toggle the input stage and potentially harm the device. All CMOS inputs must be tied to a valid logic level, VIL or VIH, during shutdown or standby mode. Exceptions are the SubLVDS inputs CLK and Dx, which can be left unconnected while not in use. Submit Documentation Feedback SN65LVDS308 www.ti.com SLLS835 – MAY 2007 Table 4. Operating Mode Transitions MODE TRANSITION USE CASE Shutdown → standby Drive RXEN high to enable receiver. TRANSITION SPECIFICS 1. RXEN high > 10 µs 2. Receiver enters standby mode. a. R[0:7] = G[0:7] = B[0:7] = VS = HS remain high and DE = PCLK low b. Receiver activates clock input monitor. Standby → acquire Transmitter activity detected 1. CLK input monitor detects clock input activity. 2. Outputs remain static. 3. PLL circuit is enabled. Acquire → receive Link is ready to receive data. 1. PLL is active and approaches lock. 2. PLL achieves lock within twakeup. 3. First data word is recovered. 4. Parallel output bus turns on switching from a static output pattern to output the first valid data word. Receive → standby Transmitter requested to enter standby mode by input common-mode voltage VICM > 0.9 VDDLVDS (e.g., transmitter output clock enters high-impedance state) 1. Receiver disables outputs within tsleep. 2. RX input monitor detects VICM > 0.9 VDDLVDS. 3. R[0:7] = G[0:7] = B[0:7] = VS = HS transition to high and DE = PCLK to low on next falling PLL clock edge. 4. PLL shuts down. 5. Clock activity input monitor remains active. Receive/standby → shutdown Turn off receiver. 1. RXEN pulled low for > tpwrdn. 2. Receiver switches all outputs to high-impedance state. 3. Most IC circuitry is shut down for least power consumption. Submit Documentation Feedback 9 SN65LVDS308 www.ti.com SLLS835 – MAY 2007 ABSOLUTE MAXIMUM RATINGS (1) Supply voltage range, VDD (2), VDDPLLA, VDDPLLD, VDDLVDS Voltage range at any input When VDDx > 0 V or output terminal When VDDx ≤ 0 V V ±4 Charged-device model (4) (all pins) ±1500 Machine model (5) (all pins) ±200 V kV V See Dissipation Ratings Table ±5 Ouput current, IO (2) (3) (4) (5) –0.3 to 2.175 –0.5 to VDD + 2.175 Continuous power dissipation (1) UNIT –0.5 to 2.175 Human body model (3) (all pins) Electrostatic discharge VALUE mA Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the GND terminals. In accordance with JEDEC Standard 22, Test Method A114-B In accordance with JEDEC Standard 22, Test Method C101 In accordance with JEDEC Standard 22, Test Method A115-A DISSIPATION RATINGS (1) (2) PACKAGE CIRCUIT BOARD MODEL TA < 25°C DERATING FACTOR (1) ABOVE TA = 25°C TA = 85°C POWER RATING ZQC Low-K (2) 496 mW 6.21 mW/°C 124 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. In accordance with the low-K thermal metric definitions of EIA/JESD51-2. DEVICE POWER DISSIPATION PARAMETER PD 10 Device power dissipation TEST CONDITIONS VDDx = 1.8 V, TA = 25°C, all outputs terminated with 10 pF, fCLK at 8 MHz VDDx = 1.95 V, TA = –40°C, all outputs terminated with 10 pF, fCLK at 30 MHz Submit Documentation Feedback TYP MAX 11.5 72.2 UNIT mW SN65LVDS308 www.ti.com SLLS835 – MAY 2007 RECOMMENDED OPERATING CONDITIONS VDD VDDPLLA VDDPLLD VDDLVDS (1) Supply voltages VDDn(PP) Supply voltage noise magnitude TA Operating free-air temperature MIN TYP MAX UNIT 1.65 1.8 1.95 V Test setup shown in Figure 5; f(noise) = 1Hz to 2 GHz 100 f(noise) = 1Hz to 1MHz 100 f(noise) > 1MHz mV 40 –40 85 °C CLK+ and CLK– fCLK± Input pixel clock frequency tDUTCLK CLK input duty cycle See Figure 1 8 30 MHz 500 kHz 35 65 % |VD0+ – VD0-|, |VD1+– VD1-|, |VCLK+ – VCLK-| during normal operation 70 200 mV Receive or acquire mode 0.6 1.2 Standby mode (2), see Figure 14 D0+, D0–, D1+, D1–, CLK+, and CLK– |VID| Magnitude of differential input voltage VICM Input voltage common mode range ∆VICM Input voltage common mode variation VICM(n) – VICM(m) with n = D0, D1, or CLK among all SubLVDS inputs and m = D0, D1, or CLK ∆VID Differential input voltage amplitude variation among all SubLVDS inputs VID(n) – VID(m) with n = D0, D1, or CLK and m = D0, D1, or CLK tr/f Input rise and fall times RXEN at VDD; see Figure 8 ∆tr/f Input rise or fall time mismatch among all SubLVDS inputs tr(n) – tr(m) and tf(n) – tf(m) with n = D0, D1, or CLK and m = D0, D1, or CLK Standby mode V 0.9 VDDLVDS –100 100 mV –10 10 % 800 ps –100 100 ps 0.7 VDD VDD V 0 0.3 VDD RXEN, F/S VICMOSH High-level input voltage VICMOSL Low-level input voltage tinRXEN RXEN input pulse duration V µs 10 R[7:0], G[7:0], B[7:0], VS, HS, PCLK CL (1) (2) Output load capacitance 10 pF Unused single-ended inputs must be held high or low to prevent them from floating. PCLK input frequencies lower than 500 kHz force the SN65LVDS308 into standby mode. Input frequencies between 500 kHz and 3 MHz may or may not activate the SN65LVDS308. Input frequencies beyond 3 MHz activate the SN65LVDS308. Input frequencies between 500 kHz and 4 MHz are not recommended, and can cause PLL malfunction. DEVICE ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER Alternating 1010 test pattern (seeTable 8***); all CMOS outputs terminated with 10 pF; F/S and RXEN at VDD; VIH = VDD, VIL = 0 V; VDD = VDDPLLA = VDDPLLD = VDDLVDS ID D RMS supply current Typical power test pattern (see Table 6); VID = 70 mV, all CMOS outputs terminated with 10 pF; F/S at GND and RXEN at VDD; VIH = VDD, VIL = 0 V; VDD = VDDPLLA = VDDPLLD = VDDLVDS CLK and Dx inputs are left open; all control inputs held static high or low; All CMOS outputs terminated with 10 pF; VIH = VDD, VIL = 0 V; VDD = VDDPLLA = VDDPLLD = VDDLVDS (1) TYP (1) MAX 14.3 19.4 fPCLK = 22 MHz 25 33 fPCLK = 30 MHz 26.8 37 fPCLK = 8 MHz 6.4 fPCLK = 22 MHz 13.7 fPCLK = 30 MHz 18.3 Standby mode; RXEN = VIH 15 100 Shutdown mode; RXEN = VIL 0.4 10 TEST CONDITIONS MIN fPCLK = 8 MHz UNIT mA mA µA All typical values are at 25°C and with 1.8-V supply, unless otherwise noted. Submit Documentation Feedback 11 SN65LVDS308 www.ti.com SLLS835 – MAY 2007 INPUT ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT D0+, D0–, D1+, D1–, CLK+, and CLK– Vthstby Input voltage common mode threshold to switch between receive/acquire mode and RXEN at VDD standby mode 1.3 VTHL Low-level differential input voltage threshold –40 VTHH High-level differential input voltage threshold II+, II– Input leakage current VDD = 1.95 V; VI+ = VI–; VI = 0.4 V or VI = 1.5 V IIOFF Power-off input current VDD = GND; VI = 1.5 V RID Differential input termination resistor value CIN Input capacitance ∆CIN Input capacitance variation VD0+– VD0–, VD1+– VD1–, VCLK+– VCLK– 78 0.9 VDDLVDS mV 100 Measured between input terminal and GND 40 mV 75 µA –75 µA 122 Ω 1 pF Within one signal pair 0.2 Between all signals RBBDC Pullup resistor for standby detection V 1 21 30 39 pF kΩ RXEN, F/S VIK Input clamp voltage IICMOS Input current (2) II = –18 mA, VDD = VDD(min) –1.2 V 0 V ≤ VDD ≤ 1.95 V; VI = GND or VI = 1.95 V 100 nA CIN Input capacitance IIH High-level input current VIN = 0.7 VDD –200 200 IIL Low-level input current VIN = 0.3 VDD –200 200 VIH High-level input voltage 0.7 VDD VDD VIL Low-level input voltage 0 0.3 VDD (1) (2) 2 pF nA V All typical values are at 25°C and with 1.8-V supply unless otherwise noted. Do not leave any CMOS input unconnected or floating to minimize leakage currents. Every input must be connected to a valid logic level, VIH or VOL, while power is supplied to VDD. OUTPUT ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.8 VDD VDD V 0 0.2 VDD V R[0:7], G[0:7], B[0:7], VS, HS, PCLK VOH High-level output current VOL Low-level output current IOH High-level output current IOL Low-level output current 12 F/S = L, IOH = –500 µA F/S = H, IOH = –2 mA F/S = L, IOL = 500 µA F/S = H, IOL = 2 mA F/S = L –500 F/S = H –2000 µA F/S = L 500 F/S = H 2000 Submit Documentation Feedback µA SN65LVDS308 www.ti.com SLLS835 – MAY 2007 SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT 800 ps –100 100 ps F/S = L 4 8 F/S = H 1 2 D0+, D0–, D1+, D1–, CLK+, and CLK– tr/f Input rise and fall times RXEN at VDD; see Figure 8 ∆tr/f Input rise or fall time mismatch between all SubLVDS inputs tr(n) – tr(m) and tf(n) – tf(m) with n = D0, D1, or CLK and m = D0, D1, or CLK R[7:0], G[7:0], B[7:0], VS, HS, PCLK CL = 10 pF (3); see Figure 7 tr/f Rise and fall time 20%–80% of VDD tOUTP PCLK output duty cycle 48% tOSK Output skew between PCLK and R[0:7], G[0:7], B[0:7], HS, See Figure 7. VS, and DE –500 (2) 53% ns 59% 500 ps 2.5/fPCLK s 3.8 µs INPUT-TO-OUTPUT RESPONSE TIME tPD(L) Propagation delay time from CLK+ input to PCLK output RXEN at VDD, VIH = VDD, VIL = GND, CL = 10 pF, see Figure 12 tGS RXEN glitch suppression pulse width (4) VIH = VDD, VIL = GND, RXEN toggles between VIL and VIH; see Figure 13 and Figure 14. tpwrup Enable time from power down (↑RXEN) Time from RXEN pulled high to data outputs enabled and transmit valid data; see Figure 14. 2 ms tpwrdn Disable time from active mode (↓RXEN) RXEN is pulled low during receive mode; time measurement until all outputs held static: R[0:7] = G[0:7] = B[0:7] = VS = HS = high, DE = PCLK = low and PLL is shut down; see Figure 14. 11 µs twakeup Enable time from standby (↑↓CLK) RXEN at VDD; device is in standby; time measurement from CLK input start of switching until PCLK and data outputs enabled and transmitting valid data; see Figure 15. 2 ms tsleep Disable time from active mode (CLK transitions to high-impedance) RXEN at VDD; device is receiving data; time measurement from CLK input signal stops (input open or input common mode VICM exceeds threshold voltage Vthstby) until all outputs held static: R[0:7] = G[0:7] = B[0:7] = VS = HS = high; DE = PCLK = low and PLL is shut down; see Figure 15. 3 µs fBW PLL bandwidth (5) Tested from CLK input to PCLK output; fPCLK = 22 MHz (1) (2) (3) (4) (5) 1.4/fPCLK 0.087 fPCLK 1.9/fPCLK MHz All typical values are at 25°C and with 1.8-V supply, unless otherwise noted. tr/f depends on the F/S setting and the capacitive load connected to each output. Some application information of how to calculate tr/f based on the output load and how to estimate the timing budget to interconnect to an LCD driver are provided in the application section near the end of this data sheet. The output rise and fall times are optimized for an output load of 10 pF. The rise and fall times can be adjusted by changing the output load capacitance. The RXEN input incorporates glitch-suppression logic to disregard short input pulses. tGS is the duration of either a high-to-low or low-to-high transition that is suppressed. When using the SN65LVDS308 receiver in conjunction with the SN65LVDS307 transmitter in one link, the PLL bandwidth of the SN65LVDS308 receiver always exceeds the bandwidth of the SN65LVDS307 transmit PLL. This ensures stable PLL tracking under all operating conditions and maximizes the receiver skew margin. Submit Documentation Feedback 13 SN65LVDS308 www.ti.com SLLS835 – MAY 2007 12 10.0 11 10 9 8 MHz 9% PLL – Bandwidth – % PLL BW [% of PCLK Frequency] 9.5 RX PLL BW 9% 8.5% 8.2% 8 7.7% 7 6 9.0 Spec Limit 8.5 8.0 30 MHz 8.1 % TX PLL BW 7.5 5 7.0 4 0 100 200 300 0 400 5 10 PLL Frequency − MHz 15 20 25 30 35 40 PCLK – Frequency – MHz G001 Figure 4. SN65LVDS308 PLL Bandwidth (Also Showing the SN65LVDS307 PLL Bandwidth) TIMING CHARACTERISTICS PARAMETER tRSKMx (1) (2) (1) (2) (3) (4) (5) Receiver input skew margin; See (3) and Figure 30 TEST CONDITIONS MIN fCLK = 30 MHz (4) x = 0..14, fPCLK =30 MHz RXEN at VDD, VIH = VDD, VIL = GND, RL = 100 Ω, test setup as in Figure 6, test pattern as in Table 9 MAX fCLK = 8 MHz to 30 MHz (5) 1 - 480 ps 2 · 15 · fCLK ps Receiver input skew margin (tRSKM) is the timing margin available for transmitter output pulse position (tPPOS), interconnect skew, and interconnect inter-symbol interference. tRSKM represents the remainder of the serial bit time not taken up by the receiver strobe uncertainty. tRSKM assumes a bit error rate better than 10–12. tRSKM is inversely proportional to the internal setup and hold time uncertainty, ISI and duty cycle distortion from the front end receiver, the skew missmatch between CLK and data D0 and D1, as well as the PLL cycle-to-cycle jitter. This includes the receiver internal setup and hold time uncertainty, all PLL-related high-frequency random and deterministic jitter components that impact the jitter budget, ISI and duty cycle distortion from the front-end receiver, and the skew between CLK and data D0 and D1; the pulse position minimum/maximum variation is given with a bit error rate target of 10–12; measurements of the total jitter are taken over >1012 samples. The minimum and maximum limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. These minimum and maximum limits are simulated only. PARAMETER MEASUREMENT INFORMATION 1 Noise Generator 100 mV VDDPLLA 2 1 SN65LVDS308 VDDPLLD VDD 10 mF VDDLVDS GND Note: The generator regulates the noise amplitude at point 1 to the target amplitude given under the table Recommended Operating Conditions 1.8-V Supply S0216-04 Figure 5. Power-Supply Noise Test Setup 14 UNIT 630 Submit Documentation Feedback SN65LVDS308 www.ti.com SLLS835 – MAY 2007 PARAMETER MEASUREMENT INFORMATION (continued) To measure tRSKM CLK is advanced or delayed with respect to data until errors are observed at the receiver outputs. The advance or delay is then reduced until there are no data errors observed over 10 tRSKM Programmable Delay –12 serial bit times. The magnitude of the advance or delay CLK CLK and Data Pattern Generator D1 DUT: SN65LVDS308 D2 Bit Error Detector D3 Ideal Receiver Strobe Position tPG_ERROR tRSKM(p) tRSKM(n) C tbit tRSKM – is the smaller of the two measured values tRSKM(p) and tRSKM(n) tPG_ERROR – Test equipment (pattern generator) intrinsic output pulse position timing uncertainty tbit – serial bit time C – LVDS308 set-up and hold-time uncertainty Note: C can be derived by subtracting the receiver skew margin tRSKM(p) + tRSKM(p) from one serial bit time T0164-03 Figure 6. Receiver Jitter-Budget Test Setup tf t setup 80% (VOH -V OL ) R[7:0], G[7:0], B[7:0], HS, VS, DE 20% (VOH -V OL ) t hold t OSK tr VOH 80% (VOH -V OL ) PCLK 50% (VOH - –VOL) 20% (VOH -VOL ) VOL tf tr Note: The Set-up and Hold-time of CMOS outputs R[7:0], G[7:0], B[7:0], HS, VS, and DE in relation to PCLK can be calulated by: 1 tS&H = 2 -rPCLK -tREF - tOSK - DtDUTP T0256-01 Figure 7. Output Rise/Fall, Setup/Hold Time Submit Documentation Feedback 15 SN65LVDS308 www.ti.com SLLS835 – MAY 2007 PARAMETER MEASUREMENT INFORMATION (continued) VD+ – VD– , VCLK+ – VCLK– tf 80%(VID) 100%(VIC) tr 0V 20%(VID) 0%(VID) T0167-01 Figure 8. SubLVDS Differential Input Rise and Fall Time Defintion CLK+, Dx+ VDDLVDS RID/2 RBBDC Gain Stage RID/2 CLK–, Dx– Standby Detection Line End Termination ESD S0224-02 Figure 9. Equivalent Input Circuit Design 16 Submit Documentation Feedback SN65LVDS308 www.ti.com SLLS835 – MAY 2007 PARAMETER MEASUREMENT INFORMATION (continued) IICMOS RXEN, F/S CMOS Input (VI+ + VI–)/2 II+ VICMOS CLK+, Dx+ VID RGB, VS, HS, PCLK IO II– CLK–, Dx– VICM VI+ VO VI– SubLVDS Input CMOS Output S0217-03 Figure 10. I/O Voltage and Current Definition RGB, VS, HS, PCLK VO SN65LVDS308 CL=10 pF S0218-03 Figure 11. CMOS Output Test Circuit, Signal, and Timing Definition Submit Documentation Feedback 17 SN65LVDS308 www.ti.com SLLS835 – MAY 2007 PARAMETER MEASUREMENT INFORMATION (continued) Pixel(n–1) R7(n–1) R7(n–2) D0+ R7 R6 R5 R4 Pixel(n) Pixel(n+1) R7(n) R7(n+1) CP R7 CP R7 CLK– CLK+ tPD(L) VDD/2 PCLK Pixel(n–1) CMOS Data Out R7 R7(n–3) R7(n–1) R6 R6(n–3) R6(n–1) T0168-02 Figure 12. Propagation Delay, Input to Output VDD/2 RXEN tGS CLK tPLL VCO Internal Signal PLL Approaches Lock tpwrup PCLK R[7:0], G[7:0], B[7:0], VS, HS DE T0257-01 Figure 13. Receiver Phase-Locked Loop Set TIme and Receiver Enable Time 18 Submit Documentation Feedback SN65LVDS308 www.ti.com SLLS835 – MAY 2007 PARAMETER MEASUREMENT INFORMATION (continued) 3 ms <20 ns Glitch Shorter Than tGS Will Be Ignored 2 ms Less Than 20 ns Spike Will be Rejected Glitch Shorter Than tGS Will Be Ignored RXEN tpwrup tpwrdn CLK+ tGS ICC tGS PCLK Receiver Disabled (OFF) Receiver Aquires Lock Receiver Enabled (ON) Receiver Turns OFF Receiver Disabled (OFF) T0254-01 Figure 14. Receiver Enable/Disable Glitch Suppression Time CLK twakeup tsleep PCLK R[7:0], G[7:0], B[7:0], VS, HS, Receiver Disabled (OFF) Receiver Aquires Lock, Outputs Still Disabled RX Enabled Output Data Valid RX Enabled; Output Data Invalid RX Disabled (OFF) T0255-01 Figure 15. Standby Detection Submit Documentation Feedback 19 SN65LVDS308 www.ti.com SLLS835 – MAY 2007 PARAMETER MEASUREMENT INFORMATION (continued) POWER CONSUMPTION TESTS Table 5 shows an example test pattern word. Table 5. Example Test Pattern Word WORD R[7:4], R[3:0], G[7:4], G[3:0], B[7:4], B[3:0], 0, VS, HS, DE 1 7 0x7C3E1E7 C 3 E 1 R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 E 7 B6 B5 B4 B3 B2 B1 B0 0 0 0 1 1 1 1 0 0 0 VS HS DE 1 1 1 TYPICAL IC POWER-CONSUMPTION TEST PATTERN Typical power-consumption test patterns consist of eight 30-bit transmit words. The pattern repeats itself throughout the entire measurement. It is assumed that every possible transmit code on RGB inputs has the same probability to occur during typical device operation. Table 6. Typical IC Power-Consumption Test Pattern WORD 20 TEST PATTERN: R[7:4], R[3:0], G[7:4], G[3:0], B[7:4], B[3:0], 0, VS, HS, DE 1 0x0000001 2 0x03F03F1 3 0xBFFBFF1 4 0x1D71D71 5 0x4C74C71 6 0xC45C451 7 0xA3aA3A5 8 0x5555553 Submit Documentation Feedback SN65LVDS308 www.ti.com SLLS835 – MAY 2007 MAXIMUM POWER-CONSUMPTION TEST PATTERN The maximum (or worst-case) power consumption of the SN65LVDS308 is tested using the two different test patterns shown in Table 7. Test patterns consist of eight 30-bit transmit words. The pattern repeats itself throughout the entire measurement. It is assumed that every possible transmit code on the RGB inputs has the same probability to occur during typical device operation. Table 7. Worst-Case Power-Consumption Test Pattern 1 WORD TEST PATTERN: R[7:4], R[3:0], G[7:4], G[3:0], B[7:4], B[3:0], 0, VS, HS, DE 1 0x0000000 2 0xFFFFFF7 Table 8. Worst-Case Power-Consumption Test Pattern 2 WORD TEST PATTERN: R[7:4], R[3:0], G[7:4], G[3:0], B[7:4], B[3:0], 0, VS, HS, DE 1 0x0000000 2 0xFFFFFF7 OUTPUT SKEW PULSE POSITION and JITTER PERFORMANCE The following test pattern is used to measure the output skew pulse position and the jitter performance of the SN65LVDS308. The jitter test pattern stresses the interconnect, particularly to test for ISI, using very long run-lengths of consecutive bits, and incorporating very high and low data rates, maximizing switching noise. The pattern is self-repeating for the duration of the test. Submit Documentation Feedback 21 SN65LVDS308 www.ti.com SLLS835 – MAY 2007 Table 9. Transmit Jitter Test Pattern WORD 22 TEST PATTERN: R[7:4], R[3:0], G[7:4], G[3:0], B[7:4], B[3:0], 0, VS, HS, DE 1 0x0000001 2 0x000FFF3 3 0x8008001 4 0x0030037 5 0xE00E001 6 0x00FF001 7 0x007E001 8 0x003C001 9 0x0018001 10 0x1C7E381 11 0x3333331 12 0x555AAA5 13 0x6DBDB61 14 0x7777771 15 0x555AAA3 16 0xAAAAAA5 17 0x5555553 18 0xAAA5555 19 0x8888881 20 0x9242491 21 0xAAA5571 22 0xCCCCCC1 23 0xE3E1C71 24 0xFFE7FF1 25 0xFFC3FF1 26 0xFF81FF1 27 0xFE00FF1 28 0x1FF1FF1 29 0xFFCFFC3 30 0x7FF7FF1 31 0xFFF0007 32 0xFFFFFF1 Submit Documentation Feedback SN65LVDS308 www.ti.com SLLS835 – MAY 2007 TYPICAL CHARACTERISTIC CURVES Some of the plots in this section show more than one curve representing various device pin relationships. Taken together, they represent a working range for the tested parameter. SUPPLY CURRENT vs TEMPERATURE QUIESCENT SUPPLY CURRENT vs TEMPERATURE 100.0 30 22 MHz (VGA), F/S = 1 25 STANDBY 11 MHz (HVGA), F/S = 1 10.0 IDDQ - mA IDD - mA 20 22 MHz (VGA), F/S = 0 15 11 MHz (HVGA), F/S = 0 10 1.0 POWERDOWN 5 0.1 -50 0 -50 -30 -10 10 30 Temperature - °C 50 70 90 -30 -10 10 30 50 Temperature - °C Figure 16. 90 Figure 17. SUPPLY CURRENT vs FREQUENCY RECEIVER STROBE POSITION vs TEMPERATURE 450 40 Limit With RSKM = 130 ps 400 35 F/S = 1, typ pwr 350 30 F/S = 1, jitter test FL3G Limit 300 t(RSPOS) 25 IDD - mA 70 20 15 22 MHz (VVGA) 250 200 150 10 100 F/S = 0, jitter test 5 50 F/S = 0, typ pwr 0 0 5 10 15 20 f - Frequency - MHz 25 30 0 -40 Figure 18. -20 0 20 40 Temperature - °C 60 80 Figure 19. Submit Documentation Feedback 23 SN65LVDS308 www.ti.com SLLS835 – MAY 2007 TYPICAL CHARACTERISTIC CURVES (continued) PLL BANDWIDTH PCLK CYCLE-TO-CYCLE OUTPUT JITTER 12 900 800 Spec Limit 8 Mhz: 9% 700 8 600 Spec Limits CC Jitter - ps PLL Bandwidth - % 10 6 4 500 400 300 200 2 100 0 0 0 10 20 Frequency - MHz 30 40 0 Figure 20. RSKM vs BIT RATE Output Voltage Amplitude - mV 225 ps 0 225 ps Trskm - Tppos -1000 190 Bit width Trskm Time - ps 40 VGA OUTPUT WAVEFORM Trskm - Tppos 1000 Trskm 0 f(PCLK) = 22 MHz –190 Bit width -1500 -2000 120 30 250 1500 -500 20 Frequency - MHz Figure 21. 2000 500 10 –250 170 220 270 320 dR - Mbps 370 500 ps/div Response Over 8-inch FR-4 + 1m Coax Cable 420 Figure 22. Figure 23. VGA OUTPUT WAVEFORM INPUT COMMON-MODE NOISE REJECTION vs FREQUENCY 0.0 249 -2.0 -4.0 -6.0 0 CMNR - dB Output Voltage Amplitude - mV 190 f(PCLK) = 22 MHz -8.0 -10.0 -12.0 -14.0 -16.0 –190 -18.0 –251 500 ps/div Response Over 80-inch FR-4 + 1m Coax Cable -20.0 0 Figure 24. 24 200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency - MHz Figure 25. Submit Documentation Feedback SN65LVDS308 www.ti.com SLLS835 – MAY 2007 TYPICAL CHARACTERISTIC CURVES (continued) INPUT RETURN LOSS INPUT DIFFERENTIAL CROSSTALK vs FREQUENCY 0.0 0.0 -10.0 Differential Xtalk - dB Differential S11 - dB -10.0 -20.0 -30.0 -40.0 -20.0 -30.0 -40.0 -50.0 -60.0 -50.0 -70.0 -60.0 -80.0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency - MHz 0 Figure 26. 200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency - MHz Figure 27. Submit Documentation Feedback 25 SN65LVDS308 www.ti.com SLLS835 – MAY 2007 APPLICATION INFORMATION PREVENTING INCREASED LEAKAGE CURRENTS IN CONTROL INPUTS A floating (left open) CMOS input allows leakage currents to flow from VDD to GND. Do not leave any CMOS input unconnected or floating. Every input must be connected to a valid logic level, VIH or VIL, while power is supplied to VDD. This also minimizes the power consumption of standby and power-down modes. POWER-SUPPLY DESIGN RECOMMENDATION For a multilayer PCB, it is recommended to keep one common GND layer underneath the device and connect all ground terminals directly to this plane. SN65LVDS308 DECOUPLING RECOMMENDATION The SN65LVDS308 was designed to operate reliably in a constricted environment with other digital switching ICs. In cell phone designs, the SN65LVDS308 often shares a power supply with various other ICs. The SN65LVDS308 can operate with power-supply noise as specified in the Recommended Operating Conditions. To minimize the power-supply noise floor, provide good decoupling near the SN65LVDS308 power pins. The use of four ceramic capacitors (two 0.01-µF and two 0.1-µF) provides good performance. At the very least, it is recommended to install one 0.1-µF and one 0.01-µF capacitor near the SN65LVDS308. To avoid large current loops and trace inductance, the trace length between the decoupling capacitors and IC power input pins must be minimized. Placing the capacitor underneath the SN65LVDS308 on the bottom of the PCB is often a good choice. VGA APPLICATION Figure 28 shows a possible implementation of a standard 640 × 480 VGA display. The SN65LVDS307 interfaces to the SN65LVDS308, which is the corresponding receiver device, to deserialize the data and drive the display driver. The pixel clock rate of 22 MHz assumes ~10% blanking overhead and 60-Hz display refresh rate. The application assumes 24-bit color resolution. Also shown is how the application processor provides a power-down (reset) signal for both the serializer and the display driver. The signal count over the flexible printed circuit board (FPC) could be further decreased by using the standby detection feature of the SN65LVDS307 and SN65LVDS308 and pulling RXEN high. 2 ´ 0.01 mF 1.8 V GND GND D1+ D1– 330 Mbps LS If no RESET signal is available, TXEN and RXEN can also be pulled high permanently with 1.8 V a pull-up resistor to VDD Serial Port Interface (3-Wire IF) R[7:0] G[7:0] B[7:0] HS, VS, DE SN65LVDS308 TXEN LS SPI RESET SN65LVDS307 D1+ D1– 22 MHz PCLK 27 LCD With VGA Resolution 330 Mbps CLK+ CLK– D0+ D0– ENABLE R[7:0] G[7:0] B[7:0] HS, VS, DE 22 MHz Video Mode Display Driver SPI 27 2.7 V 1.8 V RXEN PCLK D[23:0] HS, VS, DE 2.7 V CLK+ CLK– D0+ D0– 22 MHz Pixel CLK 2 ´ 0.1 mF GND 2 ´ 0.01 mF VDDx Application Processor (e.g. OMAP) GND FPC VDDx GND GND 2 ´ 0.1 mF 1.8 V If FPC wire count is critical, replace this connection with a pull-up resistor at RXEN 3 B0178-03 Figure 28. Typical VGA Display Application 26 Submit Documentation Feedback SN65LVDS308 www.ti.com SLLS835 – MAY 2007 APPLICATION INFORMATION (continued) TYPICAL APPLICATION FREQUENCIES The SN65LVDS308 supports pixel clock frequencies from 8 MHz to 30 MHz over two data pairs. Table 10 provides a few typical display resolution examples and shows the number of data pairs necessary to connect the SN65LVDS308 with the display. The blanking overhead is assumed to be 20%. Often, blanking overhead is smaller, resulting in a lower data rate. Furthermore, the examples in the table assumes a display frame refresh rate of 60 Hz. The actual refresh rate may differ, depending on the application-processor clock implementation. Table 10. Typical Application Data Rates and Serial Pair Usage Display Screen Resolution Visible Pixel Count Blanking Overhead Display Refresh Rate [Hz] Pixel Clock Frequency [MHz] Data Rate on D0 and D1 [Mbps] 90 8.3 124 240 × 320 (QVGA) 76,800 640 × 200 128,000 9.2 138 352 × 416 (CIF+) 146,432 10.5 158 352 × 440 154,880 11.2 167 320 × 480 (HVGA) 153,600 11.1 166 800 × 250 200,000 14.4 216 640 x 320 204,800 14.7 221 640 × 480 (VGA) 307,200 11.1 166 640 × 480 (VGA) 307,200 22.1 332 1024 × 320 327,680 23.6 354 854 × 480 (WVGA) 409,920 29.5 443 800 × 600 (SVGA) 480,000 17.3 259 1024 × 768 (XGA) 786,432 28.3 425 60 20% 30 60 30 Submit Documentation Feedback 27 SN65LVDS308 www.ti.com SLLS835 – MAY 2007 CALCULATION EXAMPLE: HVGA DISPLAY Display resolution: 480 × 320 Frame refresh rate: 58.4 Hz Vertical visible pixels: 320 lines Vertical front porch: 10 lines Vertical sync: 5 lines Vertical back porch: 3 lines Horizontal visible pixels: 480 columns Horizontal front porch: 20 columns Horizontal sync: 5 columns Horizontal back porch: 3 columns Hsync = 5 HBP The following calculation shows an example for a half-VGA display with the following parameters: Visible Area = 480 Column Vsync = 5 VBP = 3 Visible Area = 320 Lines VFP = 10 Visible Area Entire Display M0086-01 Figure 29. HVGA Display Calculation of the total number of pixels and blanking overhead: Visible area pixel count: 480 × 320 = 153,600 pixels Total frame pixel count: (320 + 10 + 5 + 3) × (480 + 20 + 5 + 3) = 171,704 pixels Blanking overhead: (171,704 – 153,600) ÷ 153,600 ≈ 11.8% The application requires the following serial-link parameters: Pixel clock frequency: 171,704 × 58.4 Hz = 10 MHz Serial data rate: 10 MHz × 15 bits/channel = 150 Mbps 28 HFP = 20 Submit Documentation Feedback SN65LVDS308 www.ti.com SLLS835 – MAY 2007 HOW TO DETERMINE INTERCONNECT SKEW AND JITTER BUDGET Designing a reliable data link requires examining the interconnect skew and jitter budget. The sum of all transmitter, PCB, connector, FPC, and receiver uncertainties must be smaller than the available serial bit time. The highest pixel clock frequency defines the available serial bit time. The transmitter timing uncertainty is defined by tPPOS in the transmitter data sheet. For a bit-error-rate target of ≤ 10–12, the measurement duration for tPPOS is ≥ 1012. The SN65LVDS308 receiver can tolerate a maximum timing uncertainty defined by tRSKM. The interconnect budget is calculated by: tinterconnect = tRSKM– tPPOS Example: fPCLK(max) = 23 MHz (VGA display resolution, 60 Hz) Transmission mode: 2-ChM; tPPOS(SN65LVDS307) = 330 ps Target bit error rate: 10–12 tRSKM(SN65LVDS308) = 1/(2 × 15 × fPCLK) – 480 ps = 969 ps The interconnect budget for cable skew and ISI must be smaller than: tinterconnect = tRSKM– tPPOS = 639 ps Ideal TPPosn data transition Serial bit width (1/dR) D0, D1 TPPosn(min) TPPosn(max) Ideal receiver strobe position tinterconnect tinterconnect RX internal sampling clock tRSPosn(min) tRSPosn(max) Tppos: Transmitter output pulse position (min and max) RSKM: Receiver Skew Margin RSPosn: Receiver input strobe position (min and max) TPPosx(max) -TPPosx(min) = TJ TXPLL(non-trackable) + tTXskew + tTXDJ RSKM = SKEW PCB + XTALK PCB + ISIPCB RSPosn(max) - RSPosn(min) = SkewRX + S&HRX + TJ (RXPLL(non-trackable) TJTXPLL(non-trackable): : non-trackable TX PLL jitter; this is mainly cycle-to-cycle PLL jitter, which can not be compensated for at the R PLL tTXskew: : transmitter output skew (skew between CLK and data) tTXIDJ Transmitter Deterministic Jitter of TX output stage (includes TX Intersymbol Interference ISI) SKEWPCB: : PCB induced Skew (trace + connector); XTALKPCB: : PCB induced cross-talk; SkewRX: Receiver input skew (skew between CLK and Dx input) S&HRX: Receiver input latch Sample & Hold uncertainty TJ(RXPLL(non-trackable): : Intrinsic RX PLL jitter above RX PLL bandwidth; PLLTJ > f(BWRX); TJ=RJ[ps-rms]*14 + DJ[ps] ISIPCB: : Inter-symbol interference of PCB; is dependent on interconnect frequency loss; may be zero for short interconnects. T0165-03 Figure 30. Jitter Budget Submit Documentation Feedback 29 SN65LVDS308 www.ti.com SLLS835 – MAY 2007 F/S-PIN SETTING AND CONNECTING THE SN65LVDS308 TO AN LCD DRIVER NOTE: Receiver PLL tracking: To maximize the design margin for the interconnect, good RX PLL tracking of the TX PLL is important. FlatLink3G requires the RX PLL to have a bandwidth higher than the bandwidth of the TX PLL. The SN65LVDS308 PLL design is optimized to track the SN65LVDS307 PLL particularly well, thus providing a very large receiver skew margin. A FlatLink3G-compliant link must provide at least ±225 ppm of receiver skew margin for the interconnect. It is important to understand the tradeoff between power consumption, EMI, and maximum speed when selecting the F/S signal. It is beneficial to choose the slowest rise time possible to minimize EMI and power consumption. Unfortunately, a slower rise time also reduces the timing margin left for the LCD driver. Hence, it is necessary to calculate the timing margin to select the correct F/S pin setting. The output rise time depends on the output driver strength and the output load. An LCD driver typical capacitive load is assumed with ~10 pF. The higher the capacitive load, the slower is the rise time. Rise time of the SN65LVDS308 is measured as the time duration it takes the output voltage to rise from 20% of VDD to 80% of VDD, and fall time is defined as the time for the output voltage to transition from 80% of VDD down to 20% of VDD. The rise time of the output stage is fixed and does not adjust to the pixel frequency. Only setting F/S changes the output rise time. Due to the short bit time at very fast pixel clock speeds and the real capacitive load of the display driver, the output amplitude might not reach VDD and GND saturation fully. To ensure sufficient signal swing and verify the design margin, it becomes necessary to determine that the output amplitude under any circumstance reaches the display driver’s input stage logic threshold (usually 30% and 70% of VDD). Figure 31 shows a worst-case rise time simulation assuming an LCD driver load of 16 pF at VGA display resolution. PCLK is the fastest-switching output. With F/S set to GND (Figure 31-b), the PCLK output voltage amplitude is significantly reduced. The voltage amplitude of the output data RGB[7:0], VS, HS, and DE shows less amplitude attenuation because these outputs carry random data patterns and toggle at half of the PCLK frequency or less. It is necessary to determine the timing margin between the SN65LVDS308 output and LCD driver input. RX rise/fall time Application: VGA (2-channel mode); F/S set to GND; Display driver load ~16 pF RX rise/fall time 2.0V 1.8V 1.8V 1.6V 1.6V 1.4V 1.4V 1.2V 1.2V VOD VOD Application: VGA (2-channel mode); F/S set to VDD; Display driver load ~16 pF 2.0V ( 1.0V 0.8V 0.6V 0.6V 0.4V 0.4V 0.2V 0.2V 0.0V 100ns 150ns 200ns 250ns 300ns 350ns clk 22 MHz, F/S=1, CL=16 pF 400ns 450ns 500ns 550ns 600ns The data signal has a slower maximum switching frequency, and therefore drives a larger amplitude than the clock signal 1.0V 0.8V 0.0V 100ns 150ns 200ns 250ns 300ns 350ns clk 22 MHz, F/S=0, CL=16 pF data 22 Mbps, F/S=1, CL=16 pF 400ns 450ns 500ns data 22 Mbps, F/S=0, CL=16 pF (b) (a) Figure 31. Output Amplitude as a Function of Output Toggling Frequency, Capacitive Load, and F/S Setting 30 Submit Documentation Feedback 550ns 600ns SN65LVDS308 www.ti.com SLLS835 – MAY 2007 HOW TO DETERMINE THE LCD DRIVER TIMING MARGIN To determine the timing margin, it is necessary to specify the frequency of operation, identify the setup and hold times of the LCD driver, and specify the output load of the SN65LVDS308 as a combination of the LCD driver input parasitics plus any capacitance caused by the connecting PCB trace. Furthermore, the setting of pin F/S and the SN65LVDS308 output skew impact the margin. The total remaining design margin calculates as follows: t rise(max) C LOAD 1 t DM + * t DUTP(max_error) * * Ťt OSKŤ 2 ƒ PCLK 10 pF (3) where: tDM – Design margin fPCLK – Pixel clock frequency tDUTP(max_error) – maximum duty cycle error trise(max) – maximum rise or fall time; see tr/f under switching characteristics CLOAD – parasitic capacitance (sum of LCD driver input parasitics + connecting PCB trace) tskew – clock to data output skew of the SN65LVDS308 Example: At a pixel clock frequency of 11 MHz (HVGA), and an assumed LCD driver load of 15 pF, the remaining timing margin is: Ť Ť t (max) * 50 t DUTP(max_error) + DUTP 100% t DM + 2 1 * 4.5ns * 11 MHz t PCLK + 5% 100% 16ns (FńS+GND) 10 pF 1 + 4.5 ns 11 MHz 15pF * 500 ps + 16 ns As long as the setup and hold times of the LCD driver are each less than 16 ns, the timing budget is met sufficiently. Submit Documentation Feedback 31 PACKAGE OPTION ADDENDUM www.ti.com 18-May-2007 PACKAGING INFORMATION Orderable Device Status (1) SN65LVDS308ZQCR ACTIVE BGA MI CROSTA R JUNI OR ZQC 48 2500 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR SN65LVDS308ZQCT ACTIVE BGA MI CROSTA R JUNI OR ZQC 48 250 SNAGCU Level-3-260C-168 HR Package Type Package Drawing Pins Package Eco Plan (2) Qty Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 17-May-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LVDS308ZQCR ZQC 48 TAI 330 12 4.3 4.3 1.5 12 12 PKGORN T1TR-MS P SN65LVDS308ZQCT ZQC 48 TAI 330 12 4.3 4.3 1.5 12 12 PKGORN T1TR-MS P TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN65LVDS308ZQCR ZQC 48 TAI 342.9 336.6 20.64 SN65LVDS308ZQCT ZQC 48 TAI 342.9 336.6 20.64 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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