MSP430F21x2 MIXED SIGNAL MICROCONTROLLER SLAS578 -- NOVEMBER 2007 D D D D D D D -- Active Mode: 200 μA at 1 MHz, 2.2 V -- Standby Mode: 0.7 μA -- Off Mode (RAM Retention): 0.1 μA Ultra-Fast Wake-Up From Standby Mode in Less Than 1 μs 16-Bit RISC Architecture, 62.5-ns Instruction Cycle Time Basic Clock Module Configurations: -- Internal Frequencies up to 16 MHz With Four Calibrated Frequencies to ±1% -- Internal Very Low Power LF Oscillator -- 32-kHz Crystal -- High-Frequency Crystal up to 16 MHz -- Resonator -- External Digital Clock Source -- External Resistor 16-Bit Timer0_A3 With Three Capture/Compare Registers 16-Bit Timer1_A2 With Two Capture/Compare Registers On-Chip Comparator for Analog Signal Compare Function or Slope Analog-to-Digital (A/D) Conversion 10-Bit 200-ksps A/D Converter With Internal Reference, Sample-and-Hold, Autoscan, and Data Transfer Controller D Universal Serial Communication Interface D D D D D D D -- Enhanced UART Supporting Auto Baudrate Detection (LIN) -- IrDA Encoder and Decoder -- Synchronous SPI -- I2C™ Brownout Detector Serial Onboard Programming, No External Programming Voltage Needed, Programmable Code Protection by Security Fuse Bootstrap Loader in Flash Devices On-Chip Emulation Module Family Members Include: MSP430F2132 8KB + 256B Flash Memory 512B RAM MSP430F2122 4KB + 256B Flash Memory 512B RAM MSP430F2112 2kB + 256B Flash Memory 256B RAM Available in 28-Pin TSSOP and 32-Pin QFN Packages (See Available Options) For Complete Module Descriptions, See the MSP430x2xx Family User’s Guide (Literature Number SLAU144) description The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 μs. The MSP430F21x2 series is an ultra-low-power microcontroller with two built-in 16-bit timers, a fast 10-bit A/D converter with integrated reference and a data transfer controller (DTC), a comparator, built-in communication capability using the universal serial communication interface, and up to 24 I/O pins. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I2C is a trademark of NXP Semiconductors. Copyright © 2007, Texas Instruments Incorporated PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 PRODUCT PREVIEW D Low Supply-Voltage Range, 1.8 V to 3.6 V D Ultra-Low Power Consumption: MSP430F21x2 MIXED SIGNAL MICROCONTROLLER SLAS578 -- NOVEMBER 2007 AVAILABLE OPTIONS TA --40°C 40 C to 85 85°C C PLASTIC 32-PIN QFN (RHB) MSP430F2112IPW MSP430F2112IRHB MSP430F2122IPW MSP430F2122IRHB MSP430F2132IPW MSP430F2132IRHB MSP430F2112TPW MSP430F2112TRHB MSP430F2122TPW MSP430F2122TRHB MSP430F2132TPW MSP430F2132TRHB PRODUCT PREVIEW --40°C 40 C to 105 105°C C PACKAGED DEVICES PLASTIC 28-PIN TSSOP (PW) 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430F21x2 MIXED SIGNAL MICROCONTROLLER SLAS578 -- NOVEMBER 2007 pin designation, PW package TEST/SBWTCK DVCC P2.5/ROSC/CA5 1 28 P1.7/TA2_0/TDO/TDI 2 3 27 26 P1.6/TA1_0/TDI/TCLK P1.5/TA0_0/TMS DVSS 4 25 P1.4/SMCLK/TCK XOUT/P2.7/CA7 5 XIN/P2.6/CA6 6 24 23 P1.2/TA1_0 RST/NMI/SBWTDIO P2.0/ACLK/A0/CA2 P2.1/TAINCLK/SMCLK/A1/CA3 7 22 P1.1/TA0_0/TA0_1 8 9 21 20 P1.0/TACLK/ADC10CLK/CAOUT P2.4/TA2_0/A4/VREF+/VeREF+/CA1 P1.3/TA2_0 P2.2/TA0_0/A2/CA4/CAOUT 10 19 P2.3/TA1_0/A3/VREF-/VeREF-/CA0 P3.0/UCB0STE/UCA0CLK/A5 11 18 P3.7/TA1_1/A7 P3.1/UCB0SIMO/UCB0SDA 12 17 P3.6/TA0_1/A6 P3.2/UCB0SOMI/UCB0SCL 13 16 P3.5/UCA0RXD/UCA0SOMI P3.3/UCB0CLK/UCA0STE 14 15 P3.4/UCA0TXD/UCA0SIMO P2.5/ROSC/CA5 NC DVCC TEST/SBWTCK P1.7/TA2_0/TDO/TDI P1.6/TA1_0/TDI/TCLK P1.5/TA0_0/TMS P1.4/SMCLK/TCK PRODUCT PREVIEW pin designation, RHB package 32 31 30 29 28 27 26 25 1 24 P1.3/TA2_0 XOUT/P2.7/CA7 XIN/P2.6/CA6 2 3 23 22 P1.2/TA1_0 P1.1/TA0_0/TA0_1 NC RST/NMI/SBWTDIO 4 5 21 20 P1.0/TACLK/ADC10CLK/CAOUT NC P2.0/ACLK/A0/CA2 P2.1/TAINCLK/SMCLK/A1/CA3 6 7 19 18 P2.4/TA2_0/A4/VREF+/VeREF+/CA1 P2.3/TA1_0/A3/VREF-/VeREF-/CA0 P2.2/TA0_0/A2/CA4/CAOUT 17 8 9 10 11 12 13 14 15 16 NC P3.0/UCB0STE/UCA0CLK/A5 P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE P3.4/UCA0TXD/UCA0SIMO P3.5/UCA0RXD/UCA0SOMI P3.6/TA0_1/A6 P3.7/TA1_1/A7 DVSS POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 MSP430F21x2 MIXED SIGNAL MICROCONTROLLER SLAS578 -- NOVEMBER 2007 functional block diagram XIN XOUT DVCC D/AVSS AVCC P1.x P3.x P2.x 8 8 8 ADC10 Port P1 Port P2 Port P3 10-bit 8 Channels Autoscan DTC 8 I/O Interrupt capability pull-up/down resistors 8 I/O Interrupt capability pull-up/down resistors 8 I/O Watchdog WDT+ Timer0_A3 Timer1_A2 3 CC Registers 2 CC Registers ACLK Basic Clock System+ SMCLK Flash RAM 8kB 4kB 2kB 512B 512B 256B MCLK 16MHz CPU incl. 16 Registers MAB MDB PRODUCT PREVIEW Emulation 2BP JTAG Interface Brownout Protection Comp_A+ 15-Bit Spy-Bi Wire RST/NMI 4 pull-up pull-down resistors POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 USCI A0 UART/ LIN, IrDA, SPI USCI B0 SPI, I2C MSP430F21x2 MIXED SIGNAL MICROCONTROLLER SLAS578 -- NOVEMBER 2007 Terminal Functions TERMINAL 28-PIN PW 32-PIN RHB I/O P1.0/ TACLK/ DESCRIPTION 21 21 I/O General-purpose digital I/O Timer0_A3, clock signal TACLK input Timer1_A2, clock signal TACLK input ADC10, conversion clock Comparator_A+ output P1.1/ TA0_0/ TA0_1 22 22 I/O General-purpose digital I/O Timer0_A3, capture: CCI0A input, compare: Out0_0 output Timer1_A2, capture: CCI0A input P1.2/ TA1_0 23 23 I/O General-purpose digital I/O Timer0_A3, capture: CCI1A input, compare: Out1_0 output P1.3/ TA2_0 24 24 I/O General-purpose digital I/O Timer0_A3, capture: CCI2A input, compare: Out2_0 output P1.4/ SMCLK/ TCK 25 25 I/O General-purpose digital I/O SMCLK signal output Test Clock input for device programming and test P1.5/ TA0_0 /TMS 26 26 I/O General-purpose digital I/O Timer0_A3, compare: Out0_0 output JTAG test mode select, input terminal for device programming and test P1.6/ TA1_0/ TDI/TCLK 27 27 I/O General-purpose digital I/O Timer0_A3, compare: Out1_0 output JTAG test data input or test clock input in programming and test P1.7/ TA2_0/ TDO/TDI 28 28 I/O General-purpose digital I/O Timer0_A3, compare: Out2_0 output JTAG test data output terminal or test data input in programming and test P2.0/ ACLK/ A0/ CA2 8 6 I/O General-purpose digital I/O ACLK signal output ADC10 analog input A0 Comparator_A+ input I/O General-purpose digital I/O SMCLK signal output Timer0_A3, clock signal TACLK input Timer1_A2, clock signal TACLK input ADC10 analog input A1 Comparator_A+ input I/O General-purpose digital I/O Timer0_A3, capture: CCI0B input, compare: Out0_0 output ADC10 analog input A2 Comparator_A+ input Comparator_A+ output I/O General-purpose digital I/O Timer0_A3, compare: Out1_0 output ADC10 analog input A3 Negative reference Comparator_A+ input I/O General-purpose digital I/O Timer0_A3, compare: Out2_0 output ADC10 analog input A4 Positive reference Comparator_A+ input ADC10CLK/ CAOUT P2.1/ TAINCLK/ SMCLK/ A1/ CA3 P2.2/ TA0_0/ A2/ CA4/ CAOUT P2.3/ TA1_0/ A3/ VREF-- /VeREF-- / CA0 P2.4/ TA2_0/ A4/ VREF+/VeREF+/ CA1 9 10 19 20 7 8 18 19 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRODUCT PREVIEW NAME 5 MSP430F21x2 MIXED SIGNAL MICROCONTROLLER SLAS578 -- NOVEMBER 2007 Terminal Functions (continued) TERMINAL 28-PIN PW 32-PIN RHB I/O XIN/ P2.6/ CA6 6 3 I/O Input terminal of crystal oscillator General-purpose digital I/O Comparator_A+ input XOUT/ P2.7/ CA7 5 2 I/O Output terminal of crystal oscillator General-purpose digital I/O Comparator_A+ input P3.0/ UCB0STE/ UCA0CLK/A5 11 9 I/O General-purpose digital I/O USCI_B0 slave transmit enable/USCI_A0 clock input/output ADC10 analog input A5 P3.1/ UCB0SIMO/UCB0SDA 12 10 I/O General-purpose digital I/O USCI_B0 slave in/master out in SPI mode, SDA I2C data in I2C mode P3.2/ UCB0SOMI/UCB0SCL 13 11 I/O General-purpose digital I/O USCI_B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode P3.3/ UCB0CLK/UCA0STE 14 12 I/O General-purpose digital I/O USCI_B0 clock input/output, USCI_A0 slave transmit enable P3.4/ UCA0TXD/UCA0SIMO 15 13 I/O General-purpose digital I/O USCI_A0 transmit data output in UART mode, slave data in/master out in SPI mode P3.5/ UCA0RXD/UCA0SOMI 16 14 I/O General-purpose digital I/O USCI_A0 receive data input in UART mode, slave data out/master in in SPI mode P3.6/ TA0_1/ A6 17 15 I/O General-purpose digital I/O Timer1_A2, capture: CCI0B input, compare: Out0_1 output ADC10 analog input A6 P3.7/ TA1_1/ A7 18 16 I/O General-purpose digital I/O Timer1_A2, capture: CCI1A input, compare: Out1_1 output ADC10 analog input A7 RST/NMI/ SBWTDIO 7 5 I Reset or nonmaskable interrupt input Spy-Bi-Wire test data input/output during programming and test 1 29 I Selects test mode for JTAG pins on Port1. The device protection fuse is connected to TEST. P2.5/ ROSC/ CA5 3 32 I/O DVCC 2 30 Digital supply voltage DVSS 4 1 Digital supply voltage NA 4, 17, 20, 31 PRODUCT PREVIEW NAME TEST/SBWTCK NC 6 DESCRIPTION General-purpose digital I/O Input for external resistor defining the DCO nominal frequency Comparator_A+ input Not connected internally. Recommended connection to VSS. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430F21x2 MIXED SIGNAL MICROCONTROLLER SLAS578 -- NOVEMBER 2007 short-form description CPU Program Counter PC/R0 Stack Pointer SP/R1 SR/CG1/R2 Status Register Constant Generator The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. instruction set The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; the address modes are listed in Table 2. CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 General-Purpose Register R11 General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 PRODUCT PREVIEW The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. Table 1. Instruction Word Formats Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 ------> R5 Single operands, destination only e.g., CALL PC ---->(TOS), R8----> PC Relative jump, un/conditional e.g., JNE R8 Jump-on-equal bit = 0 Table 2. Address Mode Descriptions ADDRESS MODE S D SYNTAX EXAMPLE Register F F MOV Rs,Rd MOV R10,R11 Indexed F F MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) Symbolic (PC relative) F F MOV EDE,TONI Absolute F F MOV &MEM,&TCDAT OPERATION R10 ----> R11 M(2+R5)----> M(6+R6) M(EDE) ----> M(TONI) M(MEM) ----> M(TCDAT) Indirect F MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) ----> M(Tab+R6) Indirect autoincrement F MOV @Rn+,Rm MOV @R10+,R11 M(R10) ----> R11 R10 + 2----> R10 Immediate F MOV #X,TONI MOV #45,TONI #45 ----> M(TONI) NOTE: S = source, D = destination POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 MSP430F21x2 MIXED SIGNAL MICROCONTROLLER SLAS578 -- NOVEMBER 2007 operating modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: D Active mode (AM) -- All clocks are active D Low-power mode 0 (LPM0) -- CPU is disabled ACLK and SMCLK remain active, MCLK is disabled D Low-power mode 1 (LPM1) -- CPU is disabled ACLK and SMCLK remain active, MCLK is disabled DCO’s dc generator is disabled if DCO not used in active mode PRODUCT PREVIEW D Low-power mode 2 (LPM2) -- CPU is disabled MCLK and SMCLK are disabled DCO’s dc generator remains enabled ACLK remains active D Low-power mode 3 (LPM3) -- CPU is disabled MCLK and SMCLK are disabled DCO’s dc generator is disabled ACLK remains active D Low-power mode 4 (LPM4) -- 8 CPU is disabled ACLK is disabled MCLK and SMCLK are disabled DCO’s dc generator is disabled Crystal oscillator is stopped POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430F21x2 MIXED SIGNAL MICROCONTROLLER SLAS578 -- NOVEMBER 2007 interrupt vector addresses INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-up External reset Watchdog Flash key violation PC out of range (see Note 1) PORIFG RSTIFG WDTIFG KEYV (see Note 2) reset 0xFFFE 31, highest NMI Oscillator fault Flash memory access violation NMIIFG OFIFG ACCVIFG (see Notes 2 and 6) (non)maskable (non)maskable (non)maskable 0xFFFC 30 Timer1_A2 TA1CCR0 CCIFG (see Note 3) maskable 0xFFFA 29 Timer1_A2 TA1CCR1 CCIFG, TA1CTL TAIFG (see Notes 2 and 3) maskable 0xFFF8 28 Comparator_A+ CAIFG maskable 0xFFF6 27 Watchdog timer WDTIFG maskable 0xFFF4 26 Timer0_A3 TA0CCR0 CCIFG (see Note 3) maskable 0xFFF2 25 Timer0_A3 TA0CCR1 CCIFG, TA0CCR2 CCIFG, TA0CTL TAIFG (see Notes 2 and 3) maskable 0xFFF0 24 USCI_A0/USCI_B0 receive USCI_B0 I2C status UCA0RXIFG, UCB0RXIFG (see Note 2 and 4) Maskable 0xFFEE 23 USCI_A0/USCI_B0 transmit USCI_B0 I2C receive / transmit UCA0TXIFG, UCB0TXIFG (see Note 2 and 5) Maskable 0xFFEC 22 ADC10 ADC10IFG (see Note 3) maskable 0xFFEA 21 0xFFE8 20 I/O port P2 (eight flags) P2IFG.0 to P2IFG.7 (see Notes 2 and 3) maskable 0xFFE6 19 I/O port P1 (eight flags) P1IFG.0 to P1IFG.7 (see Notes 2 and 3) maskable 0xFFE4 18 0xFFE2 17 0xFFE0 16 See Note 7 0xFFDE 15 See Note 8 0xFFDC to 0xFFC0 14 to 0, lowest PRODUCT PREVIEW The interrupt vectors and the power-up starting address are located in the address range 0xFFFF to 0xFFC0. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. If the reset vector (0xFFFE) contains 0xFFFF (e.g., flash is not programmed), the CPU enters LPM4 after power--up. NOTES: 1. 2. 3. 4. 5. 6. 7. A reset is executed if the CPU tries to fetch instructions from within the module register memory address range (0x0000 to 0x01FF). Multiple source flags. Interrupt flags are located in the module. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, and UCSTPIFG. In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, and UCB0TXIFG. Non--maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot. This location is used as bootstrap loader security key (BSLSKEY). A 0xAA55 at this location disables the BSL completely. A zero (0h) disables the erasure of the flash if an invalid password is supplied. 8. The interrupt vectors at addresses 0xFFDC to 0xFFC0 are not used in this device and can be used for regular program code if necessary. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 MSP430F21x2 MIXED SIGNAL MICROCONTROLLER SLAS578 -- NOVEMBER 2007 special function registers Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access. interrupt enable 1 and 2 Address 7 6 00h 4 ACCVIE rw--0 1 0 NMIIE OFIE WDTIE rw--0 rw--0 rw--0 2 Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode. OFIE Oscillator fault enable NMIIE (Non)maskable interrupt enable ACCVIE Flash access violation interrupt enable 7 6 5 01h 10 3 WDTIE Address PRODUCT PREVIEW 5 UCA0RXIE USCI_A0 receive-interrupt enable UCA0TXIE USCI_A0 transmit-interrupt enable UCB0RXIE USCI_B0 receive-interrupt enable UCB0TXIE USCI_B0 transmit-interrupt enable POST OFFICE BOX 655303 4 3 2 1 0 UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE rw--0 rw--0 rw--0 rw--0 • DALLAS, TEXAS 75265 MSP430F21x2 MIXED SIGNAL MICROCONTROLLER SLAS578 -- NOVEMBER 2007 interrupt flag register 1 and 2 Address 7 6 5 02h 4 3 2 1 0 NMIIFG RSTIFG PORIFG OFIFG WDTIFG rw--0 rw--(0) rw--(1) rw--1 rw--(0) Set on Watchdog Timer overflow or security key violation. Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode. OFIFG Flag set on oscillator fault PORIFG Power-on interrupt flag. Set on VCC power up. RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up. NMIIFG Set via RST/NMI pin Address 7 6 5 4 03h 3 2 1 0 UCB0TX IFG UCB0RX IFG UCA0TX IFG UCA0RX IFG rw--1 rw--0 rw--1 rw--0 PRODUCT PREVIEW WDTIFG UCA0RXIFG USCI_A0 receive-interrupt flag UCA0TXIFG USCI_A0 transmit-interrupt flag UCB0RXIFG USCI_B0 receive-interrupt flag UCB0TXIFG USCI_B0 transmit-interrupt flag Legend rw: rw-0,1: rw-(0,1): Bit can be read and written. Bit can be read and written. It is Reset or Set by PUC. Bit can be read and written. It is Reset or Set by POR. SFR bit is not present in device POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 MSP430F21x2 MIXED SIGNAL MICROCONTROLLER SLAS578 -- NOVEMBER 2007 memory organization MSP430F2122 MSP430F2122 MSP430F2132 Memory Main: interrupt vector Main: code memory Size Flash Flash 2KB 0xFFFF to 0xFFC0 0xFFFF to 0xF800 4KB 0xFFFF to 0xFFC0 0xFFFF to 0xF000 8KB 0xFFFF to 0xFFC0 0xFFFF to 0xE000 Information memory Size Flash 256 Byte 0x10FFh to 0x1000 256 Byte 0x10FFh to 0x1000 256 Byte 0x10FFh to 0x1000 Boot memory Size ROM 1KB 0x0FFF to 0x0C00 1KB 0x0FFF to 0x0C00 1KB 0x0FFF to 0x0C00 Size 256B 0x02FF to 0x0200 512B 0x03FF to 0x0200 512B 0x03FF to 0x0200 16-bit 8-bit 8-bit SFR 0x01FF to 0x0100 0x00FF to 0x0010 0x000F to 0x0000 0x01FF to 0x0100 0x00FF to 0x0010 0x000F to 0x0000 0x01FF to 0x0100 0x00FF to 0x0010 0x000F to 0x0000 RAM Peripherals PRODUCT PREVIEW bootstrap loader (BSL) The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by a user-defined password. For complete description of the features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap Loader (literature number SLAA089). BSL FUNCTION 28-PIN PW PACKAGE PINS 32-PIN RHB PACKAGE PINS Data rransmit 22 -- P1.1 22 -- P1.1 Data receive 10 -- P2.2 8 -- P2.2 flash memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: D Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size. D Segments 0 to n may be erased in one step, or each segment may be individually erased. D Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also called information memory. D Segment A contains calibration data. After reset segment A is protected against programming or erasing. It can be unlocked but care should be taken not to erase this segment if the calibration data is required. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430F21x2 MIXED SIGNAL MICROCONTROLLER SLAS578 -- NOVEMBER 2007 peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User’s Guide (SLAU144). oscillator and system clock The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power low-frequency oscillator, an internal digitally-controlled oscillator (DCO), and a high-frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 μs. The basic clock module provides the following clock signals: D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal or the internal D D very-low-power LF oscillator Main clock (MCLK), the system clock used by the CPU Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules PRODUCT PREVIEW The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 MSP430F21x2 MIXED SIGNAL MICROCONTROLLER SLAS578 -- NOVEMBER 2007 calibration data stored in information memory segment A Calibration data is stored for both the DCO and for ADC10 organized in a tag-length-value structure. TAGS USED BY THE ADC CALIBRATION TAGS NAME ADDRESS VALUE TAG_DCO_30 0x10F6 0x01 DCO frequency calibration at VCC = 3.0 V and TA = 30°C at calibration TAG_ADC10_1 0x10DA 0x10 ADC10_1 calibration tag -- 0xFE Identifier for empty memory areas TAG_EMPTY DESCRIPTION LABELS USED BY THE ADC CALIBRATION TAGS PRODUCT PREVIEW LABEL CONDITION AT CALIBRATION / DESCRIPTION SIZE ADDRESS OFFSET CAL_ADC_25T85 INCHx = 0x1010, REF2_5 = 1, TA = 85°C Word 0x000E CAL_ADC_25T30 INCHx = 0x1010, REF2_5 = 1, TA = 30°C Word 0x000C CAL_ADC_25VREF_FACTOR REF2_5 = 1, TA = 30°C, IVREF+ = 1.0 mA Word 0x000A CAL_ADC_15T85 INCHx = 0x1010, REF2_5 = 0, TA = 85°C Word 0x0008 CAL_ADC_15T30 INCHx = 0x1010, REF2_5 = 0, TA = 30°C Word 0x0006 CAL_ADC_15VREF_FACTOR REF2_5 = 0, TA = 30°C, IVREF+ = 0.5 mA Word 0x0004 CAL_ADC_OFFSET External Vref = 1.5 V, fADC12CLK = 5 MHz Word 0x0002 CAL_ADC_GAIN_FACTOR External Vref = 1.5 V, fADC12CLK = 5 MHz Word 0x0000 CAL_BC1_1MHz -- Byte 0x0007 CAL_DCO_1MHz -- Byte 0x0006 CAL_BC1_8MHz -- Byte 0x0005 CAL_DCO_8MHz -- Byte 0x0004 CAL_BC1_12MHz -- Byte 0x0003 CAL_DCO_12MHz -- Byte 0x0002 CAL_BC1_16MHz -- Byte 0x0001 CAL_DCO_16MHz -- Byte 0x0000 brownout The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. digital I/O There are three 8-bit I/O ports implemented—ports P1 through P3. D D D D D All individual I/O bits are independently programmable. Any combination of input, output, and interrupt conditions is possible. Edge-selectable interrupt input capability for all eight bits of ports P1 and P2. Read/write access to port-control registers is supported by all instructions. Each I/O has an individually programmable pullup/pulldown resistor. The MSP430F21x2 devices provides up to 24 total port I/O pins available externally. See the device pinout for more information. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430F21x2 MIXED SIGNAL MICROCONTROLLER SLAS578 -- NOVEMBER 2007 watchdog timer + (WDT+) The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. ADC10 The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator, and data transfer controller, or DTC, for automatic conversion result handling allowing ADC samples to be converted and stored without any CPU intervention. comparator_A+ The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals. Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer0_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer0_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer0_A3 SIGNAL CONNECTIONS INPUT PIN NUMBER 28-PIN PW 32-PIN RHB DEVICE INPUT SIGNAL 21 -- P1.0 21 -- P1.0 TACLK MODULE INPUT NAME TACLK ACLK ACLK SMCLK SMCLK 9 -- P2.1 7 -- P2.1 TAINCLK INCLK 22 -- P1.1 22 -- P1.1 TA0 CCI0A 10 -- P2.2 8 -- P2.2 TA0 CCI0B DVSS GND 23 -- P1.2 24 -- P1.3 23 -- P1.2 24 -- P1.3 MODULE BLOCK MODULE OUTPUT SIGNAL Timer NA CCR0 TA0 OUTPUT PIN NUMBER 28-PIN PW 32-PIN RHB 22 -- P1.1 22 -- P1.1 26 -- P1.5 26 -- P1.5 10 -- P2.2 8 -- P2.2 ADC10 (internal) DVCC VCC ADC10 (internal) TA1 CCI1A 23 -- P1.2 23 -- P1.2 CAOUT (internal) CCI1B 27 -- P1.6 27 -- P1.6 DVSS GND 19 - P2.3 18 -- P2.3 ADC10 (internal) CCR1 TA1 DVCC VCC ADC10 (internal) 24 -- P1.3 24 -- P1.3 28 -- P1.7 28 -- P1.7 20 - P2.4 19 -- P2.4 ADC10 (internal) ADC10 (internal) TA2 CCI2A ACLK (internal) CCI2B DVSS GND DVCC VCC POST OFFICE BOX 655303 CCR2 • DALLAS, TEXAS 75265 TA2 15 PRODUCT PREVIEW timer0_A3 MSP430F21x2 MIXED SIGNAL MICROCONTROLLER SLAS578 -- NOVEMBER 2007 timer1_A2 Timer1_A2 is a 16-bit timer/counter with two capture/compare registers. Timer1_A2 can support multiple capture/compares, PWM outputs, and interval timing. Timer1_A2 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer1_A2 Signal Connections PRODUCT PREVIEW INPUT PIN NUMBER 28-PIN PW 32-PIN RHB DEVICE INPUT SIGNAL 21 -- P1.0 21 -- P1.0 TACLK MODULE INPUT NAME TACLK ACLK ACLK SMCLK SMCLK 9 -- P2.1 7 -- P2.1 TAINCLK INCLK 22 -- P1.1 22 -- P1.1 TA0 CCI0A 17 -- P3.6 15 -- P3.6 18 -- P3.7 16 -- P3.7 TA0 CCI0B DVSS GND DVCC VCC TA1 CCI1A CAOUT (internal) CCI1B DVSS GND DVCC VCC MODULE BLOCK MODULE OUTPUT SIGNAL Timer NA CCR0 CCR1 OUTPUT PIN NUMBER 28-PIN PW 32-PIN RHB 17 -- P3.6 15 -- P3.6 18 -- P3.7 16 -- P3.7 TA0 TA1 universal serial communication interface (USCI) The USCI module is used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3 pin or 4 pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection (LIN), and IrDA. Not all packages support the USCI functionality. USCI_A0 provides support for SPI (3 pin or 4 pin), UART, enhanced UART, and IrDA. USCI_B0 provides support for SPI (3 pin or 4 pin) and I2C. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430F21x2 MIXED SIGNAL MICROCONTROLLER SLAS578 -- NOVEMBER 2007 peripheral file map ADC data transfer start address ADC memory ADC control register 1 ADC control register 0 ADC analog enable 0 ADC analog enable 1 ADC data transfer control register 1 ADC data transfer control register 0 ADC10SA ADC10MEM ADC10CTL1 ADC10CTL0 ADC10AE0 ADC10AE1 ADC10DTC1 ADC10DTC0 0x01BC 0x01B4 0x01B2 0x01B0 0x004A 0x004B 0x0049 0x0048 Timer0_A3 Capture/compare register Capture/compare register Capture/compare register Timer0_A3 register Capture/compare control Capture/compare control Capture/compare control Timer0_A3 control Timer0_A3 interrupt vector TA0CCR2 TA0CCR1 TA0CCR0 TA0R TA0CCTL2 TA0CCTL1 TA0CCTL0 TA0CTL TA0IV 0x0176 0x0174 0x0172 0x0170 0x0166 0x0164 0x0162 0x0160 0x012E Timer1_A2 Capture/compare register Capture/compare register Timer1_A2 register Capture/compare control Capture/compare control Timer1_A2 control Timer1_A2 interrupt vector TA1CCR1 TA1CCR0 TA1R TA1CCTL1 TA1CCTL0 TA1CTL TA1IV 0x0194 0x0192 0x0190 0x0184 0x0182 0x0180 0x011E Flash Memory Flash control 3 Flash control 2 Flash control 1 FCTL3 FCTL2 FCTL1 0x012C 0x012A 0x0128 Watchdog Timer+ Watchdog/timer control WDTCTL 0x0120 PRODUCT PREVIEW PERIPHERALS WITH WORD ACCESS ADC10 PERIPHERALS WITH BYTE ACCESS USCI_B0 USCI_B0 transmit buffer USCI_B0 receive buffer USCI_B0 status USCI B0 I2C Interrupt enable USCI_B0 bit rate control 1 USCI_B0 bit rate control 0 USCI_B0 control 1 USCI_B0 control 0 USCI_B0 I2C slave address USCI_B0 I2C own address UCB0TXBUF UCB0RXBUF UCB0STAT UCB0CIE UCB0BR1 UCB0BR0 UCB0CTL1 UCB0CTL0 UCB0SA UCB0OA 0x06F 0x06E 0x06D 0x06C 0x06B 0x06A 0x069 0x068 0x011A 0x0118 USCI_A0 USCI_A0 transmit buffer USCI_A0 receive buffer USCI_A0 status USCI_A0 modulation control USCI_A0 baud rate control 1 USCI_A0 baud rate control 0 USCI_A0 control 1 USCI_A0 control 0 USCI_A0 IrDA receive control USCI_A0 IrDA transmit control USCI_A0 auto baud rate control UCA0TXBUF UCA0RXBUF UCA0STAT UCA0MCTL UCA0BR1 UCA0BR0 UCA0CTL1 UCA0CTL0 UCA0IRRCTL UCA0IRTCTL UCA0ABCTL 0x0067 0x0066 0x0065 0x0064 0x0063 0x0062 0x0061 0x0060 0x005F 0x005E 0x005D POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 MSP430F21x2 MIXED SIGNAL MICROCONTROLLER SLAS578 -- NOVEMBER 2007 peripheral file map (continued) PRODUCT PREVIEW PERIPHERALS WITH BYTE ACCESS (CONTINUED) 18 Comparator_A+ Comparator_A port disable Comparator_A control2 Comparator_A control1 CAPD CACTL2 CACTL1 0x005B 0x005A 0x0059 Basic Clock System+ Basic clock system control 3 Basic clock system control 2 Basic clock system control 1 DCO clock frequency control BCSCTL3 BCSCTL2 BCSCTL1 DCOCTL 0x0053 0x0058 0x0057 0x0056 Port P3 Port P3 resistor enable Port P3 selection Port P3 direction Port P3 output Port P3 input P3REN P3SEL P3DIR P3OUT P3IN 0x0010 0x001B 0x001A 0x0019 0x0018 Port P2 Port P2 selection 2 Port P2 resistor enable Port P2 selection Port P2 interrupt enable Port P2 interrupt edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input P2SEL2 P2REN P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN 0x0042 0x002F 0x002E 0x002D 0x002C 0x002B 0x002A 0x0029 0x0028 Port P1 Port P1 selection 2 register Port P1 resistor enable Port P1 selection Port P1 interrupt enable Port P1 interrupt edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input P1SEL2 P1REN P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN 0x0041 0x0027 0x0026 0x0025 0x0024 0x0023 0x0022 0x0021 0x0020 Special Function SFR interrupt flag 2 SFR interrupt flag 1 SFR interrupt enable 2 SFR interrupt enable 1 IFG2 IFG1 IE2 IE1 0x0003 0x0002 0x0001 0x0000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 2-Nov-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) MSP430F2112IPW PREVIEW TSSOP PW 28 2000 TBD Call TI Call TI MSP430F2112IRHB PREVIEW QFN RHB 32 250 TBD Call TI Call TI MSP430F2112TPW PREVIEW TSSOP PW 28 2000 TBD Call TI Call TI MSP430F2112TRHB PREVIEW QFN RHB 32 250 TBD Call TI Call TI MSP430F2122IPW PREVIEW TSSOP PW 28 2000 TBD Call TI Call TI MSP430F2122IRHB PREVIEW QFN RHB 32 250 TBD Call TI Call TI MSP430F2122TPW PREVIEW TSSOP PW 28 2000 TBD Call TI Call TI MSP430F2122TRHB PREVIEW QFN RHB 32 250 TBD Call TI Call TI MSP430F2132IPW PREVIEW TSSOP PW 28 50 TBD Call TI Call TI MSP430F2132IRHB PREVIEW QFN RHB 32 250 TBD Call TI Call TI MSP430F2132TPW PREVIEW TSSOP PW 28 50 TBD Call TI Call TI MSP430F2132TRHB PREVIEW QFN RHB 32 250 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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