AMIS-30422 Micro-Stepping Stepper Motor Bridge Controller Introduction The AMIS−30422 is a micro-stepping stepper motor bridge controller for large current range bipolar applications. The chip interfaces via a SPI interface with an external controller in order to control two external power NMOS H−bridges. It has an on-chip voltage regulator, current sensing, self adapting PWM controller and pre-driver with smart slope control switching allowing the part to be EMC compliant with industrial and automotive applications. It uses a proprietary PWM algorithm for reliable current control. The AMIS−30422 contains a current translation table and takes the next micro-step depending on the clock signal on the “NXT” input pin and the status of the “DIR” (direction) register or input pin. The chip provides a so-called “Speed and Load Angle” output. This allows the creation of stall detection algorithms and control loops based on load angle to adjust torque and speed. The AMIS−30422 is implemented in a mature technology, enabling fast high voltage analog circuitry and multiple digital functionalities on the same chip. The chip is fully compatible with automotive voltage requirements. The AMIS−30422 is easy to use and ideally suited for large current stepper motor applications in the automotive, industrial, medical and marine environment. With the on−chip voltage regulator it further reduces the BOM for mechatronic stepper applications. Key Features • • • • • • • • • • • • • • • • Dual H−Bridge Pre−Drivers for 2−Phase Stepper Motors Programmable Current via SPI On−chip Current Translator SPI Interface Speed and Load Angle Output 9 Step Modes from Full Step up to 128 Micro−Steps Current−Sense via Two External Sense Resistors PWM Current Control with Automatic Selection of Fast and Slow Decay Low EMC PWM with Selectable Voltage Slopes Full Output Protection and Diagnosis Thermal Warning and Shutdown Compatible with 3.3 V Microcontrollers Integrated 3.3 V Regulator to Supply External Microcontroller Integrated Reset Function to Reset External Microcontroller Integrated Watchdog Function These Devices are Pb−Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2013 March, 2013 − Rev. 0 1 http://onsemi.com 1 48 QFN48 CASE 485AJ MARKING DIAGRAM 1 AMIS30422 0C422−001 AWLYYWW A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 44 of this data sheet. Publication Order Number: AMIS−30422/D AMIS−30422 OSC VBB VCP CPP CPN VDD VREGH BLOCK DIAGRAM MOTXP Chargepump MOTXN POR CLK GXTL EMC OTP DI GXTR P W M CS GXBL I−sense NXT Load Angle DIR Logic & Registers + − RSENSXN GYTL EMC GYTR P W M SLA Band− gap WD RSENSXP COMP Temp. Sense CLR GXBR TRANSLATOR DO GYBL I−sense ERR GYBR + − HOLDCUR RSENSYP COMP RSENSYN MOTYP MOTYN REF TEST AMIS−30422 GND Figure 1. Block Diagram AMIS−30422 GXBL NC NC GND VCP CPP CPN VBB GND NC NC NC 48 47 46 45 44 43 42 41 40 39 38 37 PIN OUT NC 1 36 GYBL MOTXP 2 35 MOTYP GXTL 3 34 GYTL GXBR 4 33 GYBR MOTXN 5 32 MOTYN 31 GYTR AMIS−30422 22 23 24 DI DO TEST CS GND 21 NXT 25 CLK 26 12 20 11 NC VDD 19 DIR NC 27 18 10 HOLDCUR NC NC 17 REF 16 RSENSYN 28 WD 29 9 CLR 8 15 RSENSXN ERR RSENSYP SLA 30 14 7 13 RSENSXP VREGH GXTR 6 Figure 2. Pin Out AMIS−30422 http://onsemi.com 2 AMIS−30422 Table 1. PIN LIST AND DESCRIPTION Name Pin Description Type MOTXP 2 Positive end of phase X−coil GXTL 3 Gate of external NMOS FET of the X bridge top left side Analog Output GXBR 4 Gate of external NMOS FET of the X bridge bottom right side Analog Output MOTXN 5 Negative end of phase X−coil GXTR 6 Gate of external NMOS FET of the X bridge top right side Equivalent Schematic Analog I/O Analog I/O Analog Output RSENSXP 7 Resistor sense of the X bridge positive pin Analog Input RSENSXN 8 Resistor sense of the X bridge negative pin Analog Input REF 9 Maximum Coil Current Setting Analog Input Type 7 Type 8 VDD 11 Low voltage supply output (needs external decoupling capacitor) Supply GND 12 Ground, heat sink Supply VREGH 13 High voltage supply output Analog output SLA 14 Speed and Load Angle output Analog output Type 6 ERRb 15 Error output Digital Output Type 2 or 4 CLR 16 Clear input WDb 17 Watchdog and Power On Reset output HOLDCUR 18 Hold Current Input Digital Input CLK 21 SPI Clock input Digital Input Type 1 CSb 22 SPI Chip Select input Digital Input Type 3 DI 23 SPI Data input DO 24 SPI Data output TEST 25 NXT DIR Digital Input Type 5 Digital Output Type 2 or 4 Digital Input Type 1 Digital Output Type 4 Test input. To be tied to ground. Digital Input Type 1 26 Next Microstep input Digital Input Type 1 27 Direction input Digital Input Type 1 RSENSYN 29 Resistor sense of the Y bridge negative pin Analog Input RSENSYP 30 Resistor sense of the Y bridge positive pin GYTR 31 Gate of external NMOS FET of the Y bridge top right side MOTYN 32 Negative end of phase Y−coil GYBR 33 Gate of external NMOS FET of the Y bridge bottom right side Analog Output Analog Output Analog Input Analog Output Analog I/O GYTL 34 Gate of external NMOS FET of the Y bridge top left side MOTYP 35 Positive end of phase Y−coil GYBL 36 Gate of external NMOS FET of the Y bridge bottom left side GND 40 Ground, heat sink Supply VBB 41 High voltage supply input Supply CPN 42 Negative connection of charge pump capacitor Analog I/O CPP 43 Positive connection of charge pump capacitor Analog I/O VCP 44 Charge Pump filter capacitor Analog I/O Analog I/O GND 45 Ground, heat sink GXBL 48 Gate of external NMOS FET of the X bridge bottom left side NC 1, 10, 19, 20, 28, 37, 38, 39, 46, 47 NOTE: Analog Output Supply Not connected or connect with ground Output type of WDb− and ERRb−pin is selectable through SPI. http://onsemi.com 3 Analog Output Type 9 AMIS−30422 EQUIVALENT SCHEMATICS Following figure gives the equivalent schematics of the user relevant inputs and outputs. The diagrams are simplified representations of the circuits used. VDD VDD IN OUT Rpd TYPE 1: CLK, DI, NXT, DIR, TEST Input TYPE 2: WDb, ERRb Open Drain Output VDD VDD Rpu IN OUT TYPE 3: CSb Input TYPE 4: DO, WDb, ERRb Push Pull Output VDD VDD Rout IN SLA TYPE 6: SLA Analog Output TYPE 5: VDD VBB1 VDD 2V IN RREF VBB TYPE 7: NOTE: VDD TYPE 8: VDD Power Supply TYPE 9: VBB Power Supply Output type of WDb− and ERRb−pin is selectable through SPI, DO−pin is push−pull output with tristate Figure 3. In− and Output Equivalent Diagrams http://onsemi.com 4 AMIS−30422 ELECTRICAL SPECIFICATION Table 2. ABSOLUTE MAXIMUM RATINGS (Notes 1 and 2) Symbol Parameter Min Max Unit VBB Analog DC supply voltage (Note 3) −0.3 +40 V Iload Logic supply external load current, Normal Mode 0 −10 mA Logic supply external load current, Sleep Mode 0 −1 mA Voltage on pins RSENSXP, RSENSXN, RSENSYP and RSENYN −2.0 +2.0 V Voltage on digital I/O pins, REF−pin and SLA−pin −0.3 3.6 V VRSENS VLVIO VDD + 0.3 ISLA Load current on SLA−pin 0 −40 mA TST Storage temperature −55 +160 °C Junction Temperature under bias (Note 4) −50 +175 °C VHBM Human Body Model electrostatic discharge immunity (Note 5) −2 +2 kV VHBM Human Body Model electrostatic discharge immunity, high voltage pins (Note 6) −4 +4 kV VMM Machine Model electrostatic discharge immunity (Note 7) −150 +150 V VCDM Charge Device Model electrostatic discharge immunity (Note 8) −500 +500 V TJ Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. If more than one value is mentioned, the most stringent applies. 2. Convention: currents flowing in the circuit are defined as positive. 3. +36 V < VBB < +40 V limited to 1 day over lifetime 4. Circuit functionality not guaranteed. 5. According to JESD−A114 6. High Voltage Pins MOTxx, VBB, GND; According to JESD−A114 7. According to JESD−A114 8. According to STM5.3.1−1999 RECOMMEND OPERATION CONDITIONS Operating ranges define the limits for functional operation and parametric characteristics of the device. Note that the functionality of the chip outside these operating ranges is not guaranteed. Operating outside the recommended operating ranges for extended periods of time may affect device reliability. Table 3. OPERATING RANGES Symbol Parameter Min Max Unit +6 +30 V VBB Analog DC supply VDD Logic Supply Output Voltage (Normal Mode) +3.0 +3.6 V Junction temperature (Note 9) −40 +125 °C TJ 9. High junction temperature can result in reduced lifetime. http://onsemi.com 5 AMIS−30422 Table 4. DC PARAMETERS The DC parameters are given for VBB and temperature in their operating ranges unless otherwise specified. Convention: currents flowing in the circuit are defined as positive. Pin(s) Symbol Parameter Remark/Test Conditions Min Typ Max Unit 30 V SUPPLY & VOLTAGE REGULATOR VBB VBB Nominal operating supply range 6 IBB Total internal current consumption Unloaded outputs, internal consumption included, H−bridge disabled 20 mA ISLEEP Sleep mode current consumption Unloaded outputs, CSb = VDD 150 mA V VDD VDD VDD_SLEEP Regulated Output Voltage −10 mA ≤ Iload ≤ 0 mA 3.1 3.3 3.5 Regulated Output Voltage in Sleep −1 mA ≤ Iload ≤ 0 mA 2.1 2.95 3.63 V −10 mA −80 mA −1 mA 12.8 V VBB V ILOAD External load current IDDLIM Current limitation ILOAD_PD Pin shorted to ground −20 Output current in sleep VREGH VREGH High voltage regulator VBBLV v VBB v 30 V Based on Figure 9 H−bridge disabled 13.25 V v VBBLV v 15.75 V 11.2 12.0 6 V v VBB < VBBLV Based on Figure 9 H−bridge disabled 13.25 V v VBBLV v 15.75 V POWER ON RESET (POR) VDDH VDDL VDD Internal POR comparator threshold VDD rising, see Figure 4 1.44 1.8 2.53 Internal POR comparator threshold VDD falling, see Figure 4 1.16 1.5 1.93 Internal POR comparator hysteresis VDDhys V 0.3 UNDERVOLTAGE VBBUH VBB undervoltage release level VBB rising, see Figure 5 5.5 6.5 VBBUL VBB undervoltage trigger level VBB falling, see Figure 5 5.3 6.3 V VBB VBBUhys VBB undervoltage hysteresis 0.25 ION IOFF RSW GXTR, GXTL, GXBR, GXBL, GYTR, GYTL, GYBR, GYBL PRE−DRIVER Gate charge current Selectable through SPI −3 −33 mA Gate discharge current Selectable through SPI 3 33 mA Switch On−resistance See also Figure 10 25 W http://onsemi.com 6 10 AMIS−30422 Table 4. DC PARAMETERS The DC parameters are given for VBB and temperature in their operating ranges unless otherwise specified. Convention: currents flowing in the circuit are defined as positive. Symbol Pin(s) Parameter Remark/Test Conditions Min Selectable through SPI Typ Max Unit 1/40 1/5 VREF −22 +22 % 0 VDD V REF input voltage range 0.25 2 V Tolerance on maximum VREF_Range −10 +10 % VREF ≤ 1.8 V −1 1 mA See also Figure 3 10 30 kW PRE−DRIVER PWM comparator toggle level VSENS VSENS_Tol RSENSxx PWM comparator toggle level tolerance REF INPUT REF input voltage VREF VREF_Range VREF_TOL REF IREF_LEAK REF input leakage RREF REF input impedance 20 DIGITAL INPUTS VIL VIH Rpd Rpu Logic Low Threshold CLK, DI, CSb, NXT, Logic High Threshold DIR, CLR, HOLDCUR Internal Pull Down Resistor CSb 0 0.3 x VDD V 0.7 x VDD VDD V Csb and CLR excluded, See also Figure 3 250 1100 kW See also Figure 3 250 1100 kW Internal Pull Up Resistor DIGITAL OUTPUTS Logic low output level VOL VOH VOL_OPEN DO, ERRb, WDb Output set to type 4 (see Figure 3) Logic high output level 0.5 VDD − 0.5 V IOL = 8 mA, Output set to type 2 (see Figure 3), DO excluded Logic Low level open drain 0.5 SPEED AND LOAD ANGLE OUTPUT Vout Output Voltage Range Voff Output Offset SLA−pin Voff_tol GSLA Selectable through SPI Tolerance on SLA output offset SLA GSLA_tol Gain of SLA−pin = VBEMF / VSLA Selectable through SPI Tolerance on SLA gain Rout Output Resistance SLA−pin ISLA_load 0.5 VDD − 0.5 V 0.6 1.2 V −17 +17 % 0.0625 1 −10 +10 % 1 kW −40 mA 35 °C See also Figure 3 Load current SLA−pin 0 THERMAL WARNING & SHUTDOWN T1 Trigger level thermal range 1 See Figure 21 −5 15 T2 Trigger level thermal range 2 See Figure 21 55 70 85 °C T3 Trigger level thermal range 3 See Figure 21 138 150 162 °C TTW Thermal Warning See Figure 21 138 150 162 °C TTSD Thermal shutdown See Figure 21 TTW + 20 °C CHARGE PUMP VCP − VBB VCPP – VCPN Chargepump overdrive voltage VCP Based on Figure 9 Chargepump pumping voltage 3.5 VBB – 2.5 15.75 V 3.5 VBB – 2.5 15.75 V Cpump External pump capacitor See also C2 Figure 9 220 nF Cbuffer CPP CPN External buffer capacitor See also C3 Figure 9 220 nF http://onsemi.com 7 AMIS−30422 Table 4. DC PARAMETERS The DC parameters are given for VBB and temperature in their operating ranges unless otherwise specified. Convention: currents flowing in the circuit are defined as positive. Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit PACKAGE THERMAL RESISTANCE VALUE Thermal Resistance Junction−to−Ambient Rthja Simulated Conform JEDEC JESD−51, (2S2P) 30 K/W Simulated Conform JEDEC JESD−51, (1S0P) 60 K/W 0.95 K/W Thermal Resistance Junction−to−Exposed Pad Rthjp Table 5. AC PARAMETER The AC parameters are given for VBB and temperature in their operating ranges unless otherwise specified. Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit 6.4 8 9.6 MHz 60 ms 120 ms INTERNAL OSCILLATOR Frequency of internal oscillator fosc POWER−UP tPU tPOR tRF tDSPI POR Power−up time CVDD = 200 nF, See Figure 4 Reset duration See Figure 4 80 Reset filter time See Figure 4 1 SPI Delay See Figure 4 100 15 ms 500 ms 30 kHz PREDRIVER fPWM PWM frequency Frequency depends only on internal oscillator 20 25 t1 Bridge MOSFET switch on time t1 Selectable through SPI. See Figure 11. 375 1250 ns t2 Bridge MOSFET switch on time t2 Selectable through SPI. See Figure 11. 1250 4750 ns toff Bridge MOSFET switch off time Selectable through SPI. See Figure 11. 1250 4750 ns −20 +20 % 0.32 163.84 ms −20 +20 % 0 500 ns −20 +20 % tswitch_tol topen topen_acc tnocross tnocross_acc Bridge MOSFET switch on/off tolerance Open circuit time out Selectable through SPI Open circuit time out accuracy Non overlap time Selectable through SPI Non overlap accuracy http://onsemi.com 8 AMIS−30422 Table 5. AC PARAMETER The AC parameters are given for VBB and temperature in their operating ranges unless otherwise specified. Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit DIGITAL INPUTS tNXT_HI NXT Minimum, high pulse width 625 ns tNXT_LO NXT Minimum, low pulse width 625 ns tDIR_SET NXT set up time, following change of DIR or <DIRCTRL> 1.28 ms tDIR_HOLD NXT hold time, before change of DIR or <DIRCTRL> 1.28 ms tSLP_SET <SLP> set up time 300 ms <SLP> hold time 1 ms tMOTEN_SET <MOTEN> set up time 1 ms tMOTEN_HO <MOTEN> hold time 1.28 ms tSLP_HOLD LD tMSP See Figure 6 <MSP[7:0]> update delay 1.28 ms CLEAR FUNCTION tCLR_SET tCLR CLR Clear set up time See Figure 7 40 Clear duration time See Figure 7 20 ms 90 ms 50 ns 2.5 ms ms DIGITAL OUTPUTS tH2L DO, WDb, Output fall−time from VOH to VOL ERRb Output type 2, capacitive load 400 pF and pull−up resistor of 1.5 kW WATCHDOG tWDPR Prohibited watchdog acknowledge time tWDTO Watchdog time out interval 32 512 Watchdog time out accuracy −20 +20 % 500 ns tWDTO_acc tWDRD Watchdog Reset Delay SERIAL PERIPHERAL INTERFACE (SPI) SPI Clock period tCLK tCLK_HIGH CLK tCLK_LOW tDI_SET DI tDI_HOLD tCS_HIGH tCS_SET CSb tCS_HOLD 1 ms SPI Clock high time 100 ns SPI Clock low time 100 ns 50 ns 50 ns SPI Chip Select high time 2.5 ms SPI Chip Select set up time 100 ns SPI Chip Select hold time 100 ns SPI Data Input set up time See Figure 8 SPI Data Input hold time SPEED AND LOAD ANGLE OUTPUT tSLA_DELAY SLA tMinSLA tMinSLA_Acc SLA output update delay Not−transparent Mode See Figure 19 Minimum zero crossing time Selectable through SPI Minimum zero crossing accuracy 60 ms 40 360 ms −20 +20 % 240 kHz CHARGE PUMP fCP tCPU CPN CPP Charge pump frequency MOTxx Start−up time of charge pump 160 Spec external components in Table 4 http://onsemi.com 9 200 250 ms AMIS−30422 VBB t tPU VDD VDDH VDDL ≤tRF t POR Internal signal t tPOR VWDb <WDEN> tDSPI Enable Watchdog WD Timer > tWDPR and tWDTO t WDTO Internal signal t WDPR Remarks: −WDb−pin pulled up to VDD −tWDTO = <WDT[3:0]> −<WDEN> and <WDT[3:0]> are SPI bits É Ï Ï É Ï É Ï É Ï É tPOR t Write ‘1’ to <WDEN> ≤ tWDPR or ≥ tWDTO t tWDRD t Figure 4. Power−On−Reset Timing Diagram VBB V BBUH V BBUL Figure 5. Under− and Overvoltage http://onsemi.com 10 t AMIS−30422 NXT (<NXTP> = 1) NXT (<NXTP> = 0) DIR or <DRCTRL> <SM[2:0]> <MSP[7:0]> ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ <SLP> <MOTEN> tMOTEN_SET tMOTEN_HOLD t DIR_HOLD tDIR_SET t SLP_SET tSLP_HOLD t MSP tNXT_HI tNXT_LOW Remarks: −<DIRCTRL>, <SM[2:0]>, <MSP[7:0]>, <SLP>, <MOTEN> and <NXTP> are SPI bits −Timing for SPI bits starts after CS is high −TSLP_SET only relates to the digital inputs pins DIR and NXT Figure 6. Digital Input Timing Diagram <SPI> CLR tCLR_SET tCLR Remarks: <SPI> is any SPI data Figure 7. CLR−pin Timing Diagram CS CLK ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ DI t DI_SET tCS_SET tDI_HOLD ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ t CS_HIGH tCLK_HIGH t CLK_LOW t CLK tCS_HOLD Figure 8. SPI Bus Timing Diagram http://onsemi.com 11 AMIS−30422 TYPICAL APPLICATION SCHEMATIC VBAT C3 C2 C1 D1 VDD 41 VDD 44 CPP CPN VCP VBB C4 42 43 11 6 C5 3 R3 5 REF VREGH C7 4 WD Reset CLK SPI Interface DI DO NXT DIR HOLDCUR CLR Diagnostics SLA C6 8 21 AMIS−30422 22 34 32 24 35 26 36 27 33 18 30 16 29 15 T1 T2 T3 T4 MOTXN MOTXP GXBL GXBR RSENSXP M R1 RSENSXN GYTR GYTL T5 T6 T7 T8 MOTYN MOTYP GYBL GYBR RSENSYP R2 RSENSYN 14 12 R6 31 23 GND Position Feedback ERR 7 17 25 GND Microcontroller CS Motor Positioner 48 13 GXTL 40 45 GND R4 2 9 GND C8 GXTR Figure 9. Typical Application Schematic AMIS−30422 Table 6. EXTERNAL COMPONENTS LIST AND DESCRIPTION Component Typ Value Tolerance Unit C1 VBB buffer capacitor (Note 10) Function 100 ±20% mF C2 Charge−pump pumping capacitor 220 ± 20% nF C3 Charge−pump buffer capacitor 220 ±20% nF C4 VBB decoupling capacitor (Note 11) 100 ±20% nF C5, C8 VDD buffer capacitor 100 ±20 % nF C6 Low pass filter SLA 1 ±20% nF C7 VREGH buffer capacitor 4.7 ±20% uF R1, R2 Sense Resistors >25 ±1% mW R3, R4 Coil Current Peak Setting ±1% kW R6 Low pass filter SLA D1 Optional reverse protection diode T1 … T8 Depending on desired voltage on REF−pin 5.6 MBRD1045 H−Bridge N−MOSFET NTD4815N or NTD4813N or NTD40N03R or NTD5807N 10. ESR < 1 W. 11. ESR < 50 mW. http://onsemi.com 12 AMIS−30422 FUNCTIONAL DESCRIPTION H−Bridge Pre−Drivers The H−bridge pre−drivers for external N−type MOSFETs are controlled by means of current sources for slope regulation (Figure 10). The current source value can be set through SPI (see p41 and further). During the MOSFET switch−on and switch−off phase this current source will be applied for a certain time (respectively ton and toff where ton is divided in t1 and t2). After this time (ton or toff) the gate of the MOSFET is pulled high or low by means of a switch (SWon or SWoff). The timings can also be set through SPI (see p41 and further). To prevent short circuits, an additional time tnocross can be added between switching off one MOSFET and switching on the other MOSFET of a half H−bridge (SPI bits <NO_CROSS[1:0]>). More information on the current sources and timings can be found in Table 5. A detailed description of the SPI settings for the H−bridge pre−drivers can be found at p35 and further. Figure 11 gives a detailed view on the different stages during switching of the MOSFET. Ion SWon External MOSFET Ioff SWoff AMIS−30422 Figure 10. Pre−driver Topology Vgate 5 1 2 ION1 ION2 t1 3 4 5 IOFF t2 ton toff Figure 11. Detailed View on MOSFET Switching http://onsemi.com 13 tnocross t AMIS−30422 PWM Current Control bit <MOTEN>, the direction SPI bit <DIRCTRL> and input pins DIR and NXT. It is translating consecutive steps in corresponding currents in both motor coils for a given step mode. One out of 9 possible stepping modes can be selected through SPI bits <SM[3:0]>. After power−up or clear (CLR−pin) the coil current translator is set to position 0. For all stepping modes except full step this means that the coil current is maximum in the Y−coil and zero in the X−coil (see Table 7). If NXT pulses are applied when the DIR−pin is pulled low, SPI bit <DIRCTRL> is zero and SPI bit <MOTEN> is one, the coil current translator will step through Table 7 from top till bottom. If DIR−pin is pulled high or SPI bit <DIRCTRL> is set to ‘1’, the coil current translator will step in opposite direction through the table. Figures 12 up to 15 gives another view on the different stepping modes. The Y−coil current is plotted on the Y−axes, the X−coil current on the X−axes. A PWM comparator compares continuously the actual winding current (measured over the external sense resistor) with the requested current and feeds back the information to a digital regulation loop. This loop then generates a PWM signal, which turns on/off the current sources (Ion, Ioff) and switches (SWon, SWoff). The switching points of the PWM duty−cycle are synchronized to the on−chip PWM clock. The frequency of the PWM controller is fixed and will not vary with changes in the supply voltage. Also variations in motor−speed or load−conditions of the motor have no effect. There are no external components required to adjust the PWM frequency. For EMC reasons it’s possible to add jitter to the PWM by means of the <PWMJ> bit. Step Translator and Step Mode The step translator provides the control of the motor by means of the stepmode SPI bits <SM[3:0]>, the enable SPI IY DIR−pin = high IY Start = 0 DIR−pin = high DIR−pin = low DIR−pin = low Start = 0 Step 1 Step 15 Step 7 Step 1 Step 2 Step 14 Step13 Step2 Step 6 Step 3 Step 4 Step12 IX IX Step 11 Step 3 Step5 Step5 Step 6 Step 10 Step 9 Step7 Step 4 Step 8 Figure 12. Half−step Figure 13. 1/4 Microstepping IY IY DIR−pin = high DIR−pin = high DIR−pin = low DIR−pin = low Start = 0 Start = 0 Step 1 Step 1 Step 3 IX IX Step 3 Step 2 Step 2 Figure 14. Full−Step 1/2 Rotated Figure 15. Full−step Remark: ♦ ♦ Positive coil current flows from MOTXP to MOTXN and MOTYP to MOTYN. In above figures SPI bit <DIRCTRL> is set to ‘0’. When set to ‘1’, rotation will be reversed. http://onsemi.com 14 AMIS−30422 Table 7. CIRCULAR TRANSLATOR TABLE Stepmode(< SM[3:0]>) 0000 0001 0010 0011 0100 0101 % of Imax 0110 0111 1111 Full Step + 1/2 rotation 1/128 1/64 1/32 1/16 1/8 1/4 1/2 Full Step Coil X Coil Y 0 0 0 0 0 0 0 − 0 0 100 1 − − − − − − − − 1 100 2 1 − − − − − − − 2 100 3 − − − − − − − − 4 100 4 2 1 − − − − − − 5 100 5 − − − − − − − − 6 100 6 3 − − − − − − − 7 100 7 − − − − − − − − 9 100 8 4 2 1 − − − − − 10 100 9 − − − − − − − − 11 99 10 5 − − − − − − − 12 99 11 − − − − − − − − 13 99 12 6 3 − − − − − − 15 99 13 − − − − − − − − 16 99 14 7 − − − − − − − 17 99 15 − − − − − − − − 18 98 16 8 4 2 1 − − − − 20 98 17 − − − − − − − − 21 98 18 9 − − − − − − − 22 98 19 − − − − − − − − 23 97 20 10 5 − − − − − − 24 97 21 − − − − − − − − 25 97 22 11 − − − − − − − 27 96 23 − − − − − − − − 28 96 24 12 6 3 − − − − − 29 96 25 − − − − − − − − 30 95 26 13 − − − − − − − 31 95 27 − − − − − − − − 33 95 28 14 7 − − − − − − 34 94 29 − − − − − − − − 35 94 30 15 − − − − − − − 36 93 31 − − − − − − − − 37 93 32 16 8 4 2 1 − − − 38 92 33 − − − − − − − − 39 92 34 17 − − − − − − − 41 91 35 − − − − − − − − 42 91 36 18 9 − − − − − − 43 90 37 − − − − − − − − 44 90 38 19 − − − − − − − 45 89 39 − − − − − − − − 46 89 40 20 10 5 − − − − − 47 88 41 − − − − − − − − 48 88 42 21 − − − − − − − 49 87 43 − − − − − − − − 50 86 44 22 11 − − − − − − 51 86 45 − − − − − − − − 52 85 46 23 − − − − − − − 53 84 47 − − − − − − − − 55 84 48 24 12 6 3 − − − − 56 83 49 − − − − − − − − 57 82 50 25 − − − − − − − 58 82 51 − − − − − − − − 59 81 52 26 13 − − − − − − 60 80 53 − − − − − − − − 61 80 54 27 − − − − − − − 62 79 55 − − − − − − − − 62 78 56 28 14 7 − − − − − 63 77 57 − − − − − − − − 64 77 58 29 − − − − − − − 65 76 59 − − − − − − − − 66 75 60 30 15 − − − − − − 67 74 61 − − − − − − − − 68 73 62 31 − − − − − − − 69 72 63 − − − − − − − − 70 72 64 32 16 8 4 2 1 1 − 71 71 http://onsemi.com 15 AMIS−30422 Table 7. CIRCULAR TRANSLATOR TABLE Stepmode(< SM[3:0]>) 0000 0001 0010 0011 0100 0101 % of Imax 0110 0111 1111 Full Step + 1/2 rotation 1/128 1/64 1/32 1/16 1/8 1/4 1/2 Full Step Coil X Coil Y 65 − − − − − − − − 72 70 66 33 − − − − − − − 72 69 67 − − − − − − − − 73 68 68 34 17 − − − − − − 74 67 69 − − − − − − − − 75 66 70 35 − − − − − − − 76 65 71 − − − − − − − − 77 64 72 36 18 9 − − − − − 77 63 73 − − − − − − − − 78 62 74 37 − − − − − − − 79 62 75 − − − − − − − − 80 61 76 38 19 − − − − − − 80 60 77 − − − − − − − − 81 59 78 39 − − − − − − − 82 58 79 − − − − − − − − 82 57 80 40 20 10 5 − − − − 83 56 81 − − − − − − − − 84 55 82 41 − − − − − − − 84 53 83 − − − − − − − − 85 52 84 42 21 − − − − − − 86 51 85 − − − − − − − − 86 50 86 43 − − − − − − − 87 49 87 − − − − − − − − 88 48 88 44 22 11 − − − − − 88 47 89 − − − − − − − − 89 46 90 45 − − − − − − − 89 45 91 − − − − − − − − 90 44 92 46 23 − − − − − − 90 43 93 − − − − − − − − 91 42 94 47 − − − − − − − 91 41 95 − − − − − − − − 92 39 96 48 24 12 6 3 − − − 92 38 97 − − − − − − − − 93 37 98 49 − − − − − − − 93 36 99 − − − − − − − − 94 35 100 50 25 − − − − − − 94 34 101 − − − − − − − − 95 33 102 51 − − − − − − − 95 31 103 − − − − − − − − 95 30 104 52 26 13 − − − − − 96 29 105 − − − − − − − − 96 28 106 53 − − − − − − − 96 27 107 − − − − − − − − 97 25 108 54 27 − − − − − − 97 24 109 − − − − − − − − 97 23 110 55 − − − − − − − 98 22 111 − − − − − − − − 98 21 112 56 28 14 7 − − − − 98 20 113 − − − − − − − − 98 18 114 57 − − − − − − − 99 17 115 − − − − − − − − 99 16 116 58 29 − − − − − − 99 15 117 − − − − − − − − 99 13 118 59 − − − − − − − 99 12 119 − − − − − − − − 99 11 120 60 30 15 − − − − − 100 10 121 − − − − − − − − 100 9 122 61 − − − − − − − 100 7 123 − − − − − − − − 100 6 124 62 31 − − − − − − 100 5 125 − − − − − − − − 100 4 126 63 − − − − − − − 100 2 127 − − − − − − − − 100 1 128 64 32 16 8 4 2 − 1 100 0 129 − − − − − − − − 100 −1 http://onsemi.com 16 AMIS−30422 Table 7. CIRCULAR TRANSLATOR TABLE Stepmode(< SM[3:0]>) 0000 0001 0010 0011 0100 0101 % of Imax 0110 0111 1111 Full Step + 1/2 rotation 1/128 1/64 1/32 1/16 1/8 1/4 1/2 Full Step Coil X Coil Y 130 65 − − − − − − − 100 −2 131 − − − − − − − − 100 −4 132 66 33 − − − − − − 100 −5 133 − − − − − − − − 100 −6 134 67 − − − − − − − 100 −7 135 − − − − − − − − 100 −9 136 68 34 17 − − − − − 100 −10 137 − − − − − − − − 99 −11 138 69 − − − − − − − 99 −12 139 − − − − − − − − 99 −13 140 70 35 − − − − − − 99 −15 141 − − − − − − − − 99 −16 142 71 − − − − − − − 99 −17 143 − − − − − − − − 98 −18 144 72 36 18 9 − − − − 98 −20 145 − − − − − − − − 98 −21 146 73 − − − − − − − 98 −22 147 − − − − − − − − 97 −23 148 74 37 − − − − − − 97 −24 149 − − − − − − − − 97 −25 150 75 − − − − − − − 96 −27 151 − − − − − − − − 96 −28 152 76 38 19 − − − − − 96 −29 153 − − − − − − − − 95 −30 154 77 − − − − − − − 95 −31 155 − − − − − − − − 95 −33 156 78 39 − − − − − − 94 −34 157 − − − − − − − − 94 −35 158 79 − − − − − − − 93 −36 159 − − − − − − − − 93 −37 160 80 40 20 10 5 − − − 92 −38 161 − − − − − − − − 92 −39 162 81 − − − − − − − 91 −41 163 − − − − − − − − 91 −42 164 82 41 − − − − − − 90 −43 165 − − − − − − − − 90 −44 166 83 − − − − − − − 89 −45 167 − − − − − − − − 89 −46 168 84 42 21 − − − − − 88 −47 169 − − − − − − − − 88 −48 170 85 − − − − − − − 87 −49 171 − − − − − − − − 86 −50 172 86 43 − − − − − − 86 −51 173 − − − − − − − − 85 −52 174 87 − − − − − − − 84 −53 175 − − − − − − − − 84 −55 176 88 44 22 11 − − − − 83 −56 177 − − − − − − − − 82 −57 178 89 − − − − − − − 82 −58 179 − − − − − − − − 81 −59 180 90 45 − − − − − − 80 −60 181 − − − − − − − − 80 −61 182 91 − − − − − − − 79 −62 183 − − − − − − − − 78 −62 184 92 46 23 − − − − − 77 −63 185 − − − − − − − − 77 −64 186 93 − − − − − − − 76 −65 187 − − − − − − − − 75 −66 188 94 47 − − − − − − 74 −67 189 − − − − − − − − 73 −68 190 95 − − − − − − − 72 −69 191 − − − − − − − − 72 −70 192 96 48 24 12 6 3 2 − 71 −71 193 − − − − − − − − 70 −72 194 97 − − − − − − − 69 −72 http://onsemi.com 17 AMIS−30422 Table 7. CIRCULAR TRANSLATOR TABLE Stepmode(< SM[3:0]>) 0000 0001 0010 0011 0100 0101 % of Imax 0110 0111 1111 Full Step + 1/2 rotation 1/128 1/64 1/32 1/16 1/8 1/4 1/2 Full Step Coil X Coil Y 195 − − − − − − − − 68 −73 196 98 49 − − − − − − 67 −74 197 − − − − − − − − 66 −75 198 99 − − − − − − − 65 −76 199 − − − − − − − − 64 −77 200 100 50 25 − − − − − 63 −77 201 − − − − − − − − 62 −78 202 101 − − − − − − − 62 −79 203 − − − − − − − − 61 −80 204 102 51 − − − − − − 60 −80 205 − − − − − − − − 59 −81 206 103 − − − − − − − 58 −82 207 − − − − − − − − 57 −82 208 104 52 26 13 − − − − 56 −83 209 − − − − − − − − 55 −84 210 105 − − − − − − − 53 −84 211 − − − − − − − − 52 −85 212 106 53 − − − − − − 51 −86 213 − − − − − − − − 50 −86 214 107 − − − − − − − 49 −87 215 − − − − − − − − 48 −88 216 108 54 27 − − − − − 47 −88 217 − − − − − − − − 46 −89 218 109 − − − − − − − 45 −89 219 − − − − − − − − 44 −90 220 110 55 − − − − − − 43 −90 221 − − − − − − − − 42 −91 222 111 − − − − − − − 41 −91 223 − − − − − − − − 39 −92 224 112 56 28 14 7 − − − 38 −92 225 − − − − − − − − 37 −93 226 113 − − − − − − − 36 −93 227 − − − − − − − − 35 −94 228 114 57 − − − − − − 34 −94 229 − − − − − − − − 33 −95 230 115 − − − − − − − 31 −95 231 − − − − − − − − 30 −95 232 116 58 29 − − − − − 29 −96 233 − − − − − − − − 28 −96 234 117 − − − − − − − 27 −96 235 − − − − − − − − 25 −97 236 118 59 − − − − − − 24 −97 237 − − − − − − − − 23 −97 238 119 − − − − − − − 22 −98 239 − − − − − − − − 21 −98 240 120 60 30 15 − − − − 20 −98 241 − − − − − − − − 18 −98 242 121 − − − − − − − 17 −99 243 − − − − − − − − 16 −99 244 122 61 − − − − − − 15 −99 245 − − − − − − − − 13 −99 246 123 − − − − − − − 12 −99 247 − − − − − − − − 11 −99 248 124 62 31 − − − − − 10 −100 249 − − − − − − − − 9 −100 250 125 − − − − − − − 7 −100 251 − − − − − − − − 6 −100 252 126 63 − − − − − − 5 −100 253 − − − − − − − − 4 −100 254 127 − − − − − − − 2 −100 255 − − − − − − − − 1 −100 256 128 64 32 16 8 4 − 2 0 −100 257 − − − − − − − − −1 −100 258 129 − − − − − − − −2 −100 259 − − − − − − − − −4 −100 http://onsemi.com 18 AMIS−30422 Table 7. CIRCULAR TRANSLATOR TABLE Stepmode(< SM[3:0]>) 0000 0001 0010 0011 0100 0101 % of Imax 0110 0111 1111 Full Step + 1/2 rotation 1/128 1/64 1/32 1/16 1/8 1/4 1/2 Full Step Coil X Coil Y 260 130 65 − − − − − − −5 −100 261 − − − − − − − − −6 −100 262 131 − − − − − − − −7 −100 263 − − − − − − − − −9 −100 264 132 66 33 − − − − − −10 −100 265 − − − − − − − − −11 −99 266 133 − − − − − − − −12 −99 267 − − − − − − − − −13 −99 268 134 67 − − − − − − −15 −99 269 − − − − − − − − −16 −99 270 135 − − − − − − − −17 −99 271 − − − − − − − − −18 −98 272 136 68 34 17 − − − − −20 −98 273 − − − − − − − − −21 −98 274 137 − − − − − − − −22 −98 275 − − − − − − − − −23 −97 276 138 69 − − − − − − −24 −97 277 − − − − − − − − −25 −97 278 139 − − − − − − − −27 −96 279 − − − − − − − − −28 −96 280 140 70 35 − − − − − −29 −96 281 − − − − − − − − −30 −95 282 141 − − − − − − − −31 −95 283 − − − − − − − − −33 −95 284 142 71 − − − − − − −34 −94 285 − − − − − − − − −35 −94 286 143 − − − − − − − −36 −93 287 − − − − − − − − −37 −93 288 144 72 36 18 9 − − − −38 −92 289 − − − − − − − − −39 −92 290 145 − − − − − − − −41 −91 291 − − − − − − − − −42 −91 292 146 73 − − − − − − −43 −90 293 − − − − − − − − −44 −90 294 147 − − − − − − − −45 −89 295 − − − − − − − − −46 −89 296 148 74 37 − − − − − −47 −88 297 − − − − − − − − −48 −88 298 149 − − − − − − − −49 −87 299 − − − − − − − − −50 −86 300 150 75 − − − − − − −51 −86 301 − − − − − − − − −52 −85 302 151 − − − − − − − −53 −84 303 − − − − − − − − −55 −84 304 152 76 38 19 − − − − −56 −83 305 − − − − − − − − −57 −82 306 153 − − − − − − − −58 −82 307 − − − − − − − − −59 −81 308 154 77 − − − − − − −60 −80 309 − − − − − − − − −61 −80 310 155 − − − − − − − −62 −79 311 − − − − − − − − −62 −78 312 156 78 39 − − − − − −63 −77 313 − − − − − − − − −64 −77 314 157 − − − − − − − −65 −76 315 − − − − − − − − −66 −75 316 158 79 − − − − − − −67 −74 317 − − − − − − − − −68 −73 318 159 − − − − − − − −69 −72 319 − − − − − − − − −70 −72 320 160 80 40 20 10 5 3 − −71 −71 321 − − − − − − − − −72 −70 322 161 − − − − − − − −72 −69 323 − − − − − − − − −73 −68 324 162 81 − − − − − − −74 −67 http://onsemi.com 19 AMIS−30422 Table 7. CIRCULAR TRANSLATOR TABLE Stepmode(< SM[3:0]>) 0000 0001 0010 0011 0100 0101 % of Imax 0110 0111 1111 Full Step + 1/2 rotation 1/128 1/64 1/32 1/16 1/8 1/4 1/2 Full Step Coil X Coil Y 325 − − − − − − − − −75 −66 326 163 − − − − − − − −76 −65 327 − − − − − − − − −77 −64 328 164 82 41 − − − − − −77 −63 329 − − − − − − − − −78 −62 330 165 − − − − − − − −79 −62 331 − − − − − − − − −80 −61 332 166 83 − − − − − − −80 −60 333 − − − − − − − − −81 −59 334 167 − − − − − − − −82 −58 335 − − − − − − − − −82 −57 336 168 84 42 21 − − − − −83 −56 337 − − − − − − − − −84 −55 338 169 − − − − − − − −84 −53 339 − − − − − − − − −85 −52 340 170 85 − − − − − − −86 −51 341 − − − − − − − − −86 −50 342 171 − − − − − − − −87 −49 343 − − − − − − − − −88 −48 344 172 86 43 − − − − − −88 −47 345 − − − − − − − − −89 −46 346 173 − − − − − − − −89 −45 347 − − − − − − − − −90 −44 348 174 87 − − − − − − −90 −43 349 − − − − − − − − −91 −42 350 175 − − − − − − − −91 −41 351 − − − − − − − − −92 −39 352 176 88 44 22 11 − − − −92 −38 353 − − − − − − − − −93 −37 354 177 − − − − − − − −93 −36 355 − − − − − − − − −94 −35 356 178 89 − − − − − − −94 −34 357 − − − − − − − − −95 −33 358 179 − − − − − − − −95 −31 359 − − − − − − − − −95 −30 360 180 90 45 − − − − − −96 −29 361 − − − − − − − − −96 −28 362 181 − − − − − − − −96 −27 363 − − − − − − − − −97 −25 364 182 91 − − − − − − −97 −24 365 − − − − − − − − −97 −23 366 183 − − − − − − − −98 −22 367 − − − − − − − − −98 −21 368 184 92 46 23 − − − − −98 −20 369 − − − − − − − − −98 −18 370 185 − − − − − − − −99 −17 371 − − − − − − − − −99 −16 372 186 93 − − − − − − −99 −15 373 − − − − − − − − −99 −13 374 187 − − − − − − − −99 −12 375 − − − − − − − − −99 −11 376 188 94 47 − − − − − −100 −10 377 − − − − − − − − −100 −9 378 189 − − − − − − − −100 −7 379 − − − − − − − − −100 −6 380 190 95 − − − − − − −100 −5 381 − − − − − − − − −100 −4 382 191 − − − − − − − −100 −2 383 − − − − − − − − −100 −1 384 192 96 48 24 12 6 − 3 −100 0 385 − − − − − − − − −100 1 386 193 − − − − − − − −100 2 387 − − − − − − − − −100 4 388 194 97 − − − − − − −100 5 389 − − − − − − − − −100 6 http://onsemi.com 20 AMIS−30422 Table 7. CIRCULAR TRANSLATOR TABLE Stepmode(< SM[3:0]>) 0000 0001 0010 0011 0100 0101 % of Imax 0110 0111 1111 Full Step + 1/2 rotation 1/128 1/64 1/32 1/16 1/8 1/4 1/2 Full Step Coil X Coil Y 390 195 − − − − − − − −100 7 391 − − − − − − − − −100 9 392 196 98 49 − − − − − −100 10 393 − − − − − − − − −99 11 394 197 − − − − − − − −99 12 395 − − − − − − − − −99 13 396 198 99 − − − − − − −99 15 397 − − − − − − − − −99 16 398 199 − − − − − − − −99 17 399 − − − − − − − − −98 18 400 200 100 50 25 − − − − −98 20 401 − − − − − − − − −98 21 402 201 − − − − − − − −98 22 403 − − − − − − − − −97 23 404 202 101 − − − − − − −97 24 405 − − − − − − − − −97 25 406 203 − − − − − − − −96 27 407 − − − − − − − − −96 28 408 204 102 51 − − − − − −96 29 409 − − − − − − − − −95 30 410 205 − − − − − − − −95 31 411 − − − − − − − − −95 33 412 206 103 − − − − − − −94 34 413 − − − − − − − − −94 35 414 207 − − − − − − − −93 36 415 − − − − − − − − −93 37 416 208 104 52 26 13 − − − −92 38 417 − − − − − − − − −92 39 418 209 − − − − − − − −91 41 419 − − − − − − − − −91 42 420 210 105 − − − − − − −90 43 421 − − − − − − − − −90 44 422 211 − − − − − − − −89 45 423 − − − − − − − − −89 46 424 212 106 53 − − − − − −88 47 425 − − − − − − − − −88 48 426 213 − − − − − − − −87 49 427 − − − − − − − − −86 50 428 214 107 − − − − − − −86 51 429 − − − − − − − − −85 52 430 215 − − − − − − − −84 53 431 − − − − − − − − −84 55 432 216 108 54 27 − − − − −83 56 433 − − − − − − − − −82 57 434 217 − − − − − − − −82 58 435 − − − − − − − − −81 59 436 218 109 − − − − − − −80 60 437 − − − − − − − − −80 61 438 219 − − − − − − − −79 62 439 − − − − − − − − −78 62 440 220 110 55 − − − − − −77 63 441 − − − − − − − − −77 64 442 221 − − − − − − − −76 65 443 − − − − − − − − −75 66 444 222 111 − − − − − − −74 67 445 − − − − − − − − −73 68 446 223 − − − − − − − −72 69 447 − − − − − − − − −72 70 448 224 112 56 28 14 7 0 − −71 71 449 − − − − − − − − −70 72 450 225 − − − − − − − −69 72 451 − − − − − − − − −68 73 452 226 113 − − − − − − −67 74 453 − − − − − − − − −66 75 454 227 − − − − − − − −65 76 http://onsemi.com 21 AMIS−30422 Table 7. CIRCULAR TRANSLATOR TABLE Stepmode(< SM[3:0]>) 0000 0001 0010 0011 0100 0101 % of Imax 0110 0111 1111 Full Step + 1/2 rotation 1/128 1/64 1/32 1/16 1/8 1/4 1/2 Full Step Coil X Coil Y 455 − − − − − − − − −64 77 456 228 114 57 − − − − − −63 77 457 − − − − − − − − −62 78 458 229 − − − − − − − −62 79 459 − − − − − − − − −61 80 460 230 115 − − − − − − −60 80 461 − − − − − − − − −59 81 462 231 − − − − − − − −58 82 463 − − − − − − − − −57 82 464 232 116 58 29 − − − − −56 83 465 − − − − − − − − −55 84 466 233 − − − − − − − −53 84 467 − − − − − − − − −52 85 468 234 117 − − − − − − −51 86 469 − − − − − − − − −50 86 470 235 − − − − − − − −49 87 471 − − − − − − − − −48 88 472 236 118 59 − − − − − −47 88 473 − − − − − − − − −46 89 474 237 − − − − − − − −45 89 475 − − − − − − − − −44 90 476 238 119 − − − − − − −43 90 477 − − − − − − − − −42 91 478 239 − − − − − − − −41 91 479 − − − − − − − − −39 92 480 240 120 60 30 15 − − − −38 92 481 − − − − − − − − −37 93 482 241 − − − − − − − −36 93 483 − − − − − − − − −35 94 484 242 121 − − − − − − −34 94 485 − − − − − − − − −33 95 486 243 − − − − − − − −31 95 487 − − − − − − − − −30 95 488 244 122 61 − − − − − −29 96 489 − − − − − − − − −28 96 490 245 − − − − − − − −27 96 491 − − − − − − − − −25 97 492 246 123 − − − − − − −24 97 493 − − − − − − − − −23 97 494 247 − − − − − − − −22 98 495 − − − − − − − − −21 98 496 248 124 62 31 − − − − −20 98 497 − − − − − − − − −18 98 498 249 − − − − − − − −17 99 499 − − − − − − − − −16 99 500 250 125 − − − − − − −15 99 501 − − − − − − − − −13 99 502 251 − − − − − − − −12 99 503 − − − − − − − − −11 99 504 252 126 63 − − − − − −10 100 505 − − − − − − − − −9 100 506 253 − − − − − − − −7 100 507 − − − − − − − − −6 100 508 254 127 − − − − − − −5 100 509 − − − − − − − − −4 100 510 255 − − − − − − − −2 100 511 − − − − − − − − −1 100 Remarks: ♦ Positive coil current conducts from MOTXP to MOTXN or MOTYP to MOTYN. http://onsemi.com 22 AMIS−30422 Direction movement of the stepper motor. It’s not allowed to apply pulses on the NXT−pin when the motor driver is disabled. Certain errors (see Error Output p28) will automatically disable the motor driver (<MOTEN> = 0). The errors first need to be cleared before one is able to enable the motor driver again. Setup and hold times need to be respected (see Figure 6). The direction of rotation can be changed by means of the DIR−pin and the SPI bit <DIRCTRL>. See also Figure 12 up to Figure 15. Setup and hold times need to be respected when changing direction (see Figure 6). NXT Input Every rising or falling edge on the NXT−pin (selectable through SPI bit <NXTP>) will move the coil current one step up or down (dependant on the DIR−pin and <DIRCTRL> bit) in the translator table (see Table 7). The motor current will be updated at the next PWM cycle. Microstep Position To be able to track the position in the current translator table (Table 7), the microstep position SPI byte can be used (<MSP[8:0]>). This byte gives the position within the current translator table in units of 1/128 microsteps. This means that when working in 1/4th microstepping the read out microstep positions will be 0, 32, 64, ... The microstep position can be used to track/verify the real position of the stepper motor. Keep in mind that <MSP[8:0]> will only be update 1 ms after the NXT pulse was applied. Enable The enable SPI bit <MOTEN> is used to enable the PWM regulator and drive coil current through the stepper motor coils. When ‘1’ the motor driver is enabled and coil current will be conducted. If ‘0’ (zero), the H−bridge drivers are disabled. When the motor driver is enabled, the NXT− and DIR−pin as also the <DIRCTRL> SPI bit can be used to control the VDIR t VNXT Step up in translator table Step up in translator table Step down in translator table t Step down in translator table Figure 16. Translator Table Update Microstep stepping mode this could lead to a change in coil current (= movement of rotor) even if no NXT pulses are applied. This will only be the case if the microstep position is not shared between the old and new stepping mode (see also Table 7 and Figure 17). This is done to avoid unwanted phase shifts in the coil current. <SM[3:0]> is used to set the microstep stepping mode. Changing to another microstep stepping mode can be done but the setup and hold timings need to be respected (see Figure 6). Changing to another stepping mode can be done in any (microstep) position. When changing to a lower IY IY IY DIR−pin = low DIR−pin = low Step 1 Step 1 Step 2 IY Step 1 Step 2 IX IX IX IX Step 3 1/4th Stepping Mode Half Step 1/4th Stepping Mode Step 2 of 1/4th stepping mode is equal to Step 1 of half step stepping mode (see Table 7). No change of coil current during change of stepping mode. Half Step Step 1 of 1/4th stepping mode is NOT shared with a step in half step stepping mode (see Table 7). Change of coil current will occur during change of stepping mode (to avoid a coil current phase shift). Figure 17. NXT−Step Mode Synchronization http://onsemi.com 23 AMIS−30422 Programmable Peak−Current The Hold Current (<HOLD_CUR[2:0]>) is calculated in the same way as the Run Current (<CUR[2:0]>). The amplitude of the current waveform in the motor coils (Imax) can be programmed through SPI bits <CUR[2:0]>. The coil current can be calculated as next: Clear RSENSE is resistor R1 and R2 as given in Figure 9, <CUR[2:0]> is dependant on the REF−pin voltage. This makes it possible to set the coil current by means of SPI commands or by adjusting the REF−pin voltage. See also page 35. A change in the coil current (<CUR[2:0]>) will be updated at the next PWM cycle. Logic 0 on the CLR−pin allows normal operation of the chip. To clear the complete digital inside AMIS−30422, the CLR−pin needs to be pulled to logic 1 for a minimum time of tCLR (Table 5). Clearing the motor driver can not be done during Sleep Mode. During a clear the charge pump remains active. The voltage regulator remains functional during and after the clear action and the WDb−pin is not activated. After a clear, NXT pulses can be applied after tCLR_SET (see Figure 7). Hold Current Setting Speed and Load Angle Output I max + <CUR[2:0]> ń R SENSE The SLA−pin provides an output voltage that indicates the level of the BEMF (Back Electro Magnetic Force) voltage of the motor. This BEMF voltage is sampled during every so−called ”coil current zero crossing”. Per coil, two zero−current positions exist per electrical period, yielding in a total of four zero−current observation points per electrical period. Because of the relatively high recirculation currents in the coil during current decay, the coil voltage VCOIL shows a transient behavior. This transient behavior (which is not the BEMF) can be made visible or invisible on the SLA−pin by means of SPI bit <SLAT>. When set to transparent (<SLAT> = ‘1’), the coil voltage is sampled every PWM cycle and updated on the SLA−pin (see Figure 18). When set to not−transparent (<SLAT> = ‘0’), only the last sample (taken right before leaving the “coil current zero crossing”) will be copied to the SLA−pin (see Figure 19). When working in not−transparent mode (<SLAT> = ‘0’) keep in mind that there is a delay between applying the NXT pulse (to leave the “coil current zero crossing”) and the updated voltage on the SLA−pin (see tSLA_DELAY in Figure 19 and Table 5). A second coil current value can be programmed which is called the Hold Current (<HOLD_CUR[2:0]>). By enabling this functionality (<EN_HOLD> = 1), AMIS−30422 will automatically change the coil current to the programmed Hold Current value when no NXT pulse is detected for a time longer than the specified <HOLD_TIME[1:0]>. From the moment a NXT pulse is detected, AMIS−30422 will automatically set the coil current back to <CUR[2:0]>. This functionality makes it easy to add Run and Hold Current capability to your application. The HOLDCUR−pin can be used if one wants to select Run or Hold Current manually. To use this pin, <EN_HOLD> must be set to 0 (zero). When pulling the HOLDCUR−pin high, the coil current will be defined by the <HOLD_CUR[2:0]> value. When pulled low, the coil current will be defined by the <CUR[2:0]> value. When <EN_HOLD> is set to 0 (zero) <HOLD_TIME[1:0]> will have no meaning. Switching between the two coil current values can be done at any time (= independent of the NXT frequency). By this the HOLDCUR−pin can also be used to switch between two coil current values in an easy way (even when the motor is rotating). http://onsemi.com 24 AMIS−30422 I coil I coil t Coil Current Zero Crossing V NXT Next Microstep Next step Previous Microstep Next step V NXT Next Microstep Next step Coil Current Zero Crossing Next step Previous Microstep t t t I coil I coil Current Decay Current Decay t V coil t V coil VBB + 0.6V V BB + 0.6V VBEMF V BEMF t t V SLA Transparent V SLA Not−transparent Bemf of previous zero crossing Last sample before leaving zero crossing is retained. Bemf of previous zero crossing t tSLA _DELAY Remark: Vcoil is only drawn during the coil current zero crossing t Remark: Vcoil is only drawn during the coil current zero crossing Figure 18. Principle of BEMF Measurement in Transparent Mode Figure 19. Principle of BEMF Measurement in Not−Transparent Mode Figure 20). By using SPI bits <MIN_SLA_TIME[1:0]> one can stretch the “coil current zero crossing” without changing the speed of the motor (see Figure 20). AMIS−30422 will ignore but keep track of the NXT pulses applied during the “stretched coil current zero crossing” and compensate the ignored pulses when leaving the “coil current zero crossing”. More information on using the SLA−pin can be found in application note AND8399. Although this application note refers to AMIS−305xx, it is also valid for AMIS−30422. The relationship between the voltage measured on the SLA−pin and the coil voltage is: VSLA = 0.6 + (0.6 x <SLA_OFFS>) + (Vcoil x <SLAG>) SPI bit <SLA_OFFS> can be used to add an additional offset of 0.6 V. Five different SLA gain values can be set by means of SPI bits <SLAG[2:0]>. AMIS−30422 has the ability to stretch the “coil current zero crossing”. If NXT pulses are applied too fast it’s possible that the “coil current zero crossing” is too short making it impossible to measure the real BEMF (see http://onsemi.com 25 AMIS−30422 Figure 20. BEMF sampling without (left) and with (right) zero crossing stretching Sleep Mode The voltage regulator remains active but with reduced current−output capability (ILOAD_PD). When Sleep Mode is left a start−up time is needed for the charge pump to stabilize. After this time (tSLP_SET) NXT commands can be issued (see also Figure 6). Enabling the motor when the charge pump is not stable can result in overcurrent errors (see section Over−Current Detection). Because of this it’s advised to keep the motor disabled during the stabilization time (tSLP_SET). The IO−pins of AMIS−30422 have internal pull−down or pull−up resistors (see Figure 3). Keep this in mind when entering Sleep Mode. In Sleep Mode VDD can drop to 2.1 V minimum (see VDD_SLEEP in Table 4). Keep in mind that in this case it’s not allowed to pull the input pins above 2.1 V! AMIS−30422 can be placed in Sleep Mode by means of SPI bit <SLP>. This mode allows reduction of current−consumption when the motor is not in operation. The effect of sleep mode is as follows: • The drivers are put in HiZ • All analog circuits are disabled and in low−power mode • All SPI registers maintain their logic content • SPI communication is still possible (slightly current increase during SPI communication). • Status Registers can not be cleared by reading out • NXT and DIR inputs are forbidden • Oscillator and digital clocks are silent • Motor driver can not be cleared by means of the CLR−pin http://onsemi.com 26 AMIS−30422 WARNING, ERROR DETECTION AND DIAGNOSTICS FEEDBACK Thermal Warning and Shutdown Note: Successive resetting the motor driver in case of a short circuit condition may damage the drivers. AMIS−30422 has 4 thermal ranges which can be read out through SPI bits <TR[1:0]> and <TSD>. Thermal Range 1 goes from −40°C up to T1. Thermal Range 2 goes from T1 to T2 and Thermal Range 3 goes from T2 up to T3 (T1, T2 and T3 can be found in Table 4). Once above T3 the 4th thermal level is reached which is the thermal warning range. When junction temperature rises above TTW (= T3), the ERRb−pin will be activated. If junction temperature increases above thermal shutdown level (TTSD), then the circuit goes in Thermal Shutdown Mode and all driver transistors are disabled (high impedance). The condition to get out of the Thermal Shutdown Mode is to be at a temperature lower than TTW and by clearing the <TSD> SPI bit. ÂÂ ÏÏ ÏÏ ÂÂ ÈÈ ÈÈ ÈÈ ÇÇ ÇÇ ÇÇ ÀÀ ÀÀ ÀÀ TTSD T 3= TTW Open Coil/Current Not Reached Detection Open coil detection is based on the observation of 100% duty cycle of the PWM regulator. If in a coil 100% duty cycle is detected for a certain time, an open coil will be latched (see Status Register 1 and 2) and the ERRb−pin will be activated (drivers are disabled). The time this 100% duty cycle needs to be present is adjustable with SPI bits <OPEN_COIL[1:0]>. A short time will result in fast detection of an open−coil but could also trigger unwanted open−coil errors. Increase the timing if this is the case. When the resistance of a motor coil is very large and the supply voltage is low, it can happen that the motor driver is not able to deliver the requested current to the motor. Under these conditions the PWM controller duty cycle will be 100% and the ERRb−pin will flag this situation. This feature can be used to test if the operating conditions (supply voltage, motor coil resistance) still allow reaching the requested coil−current or else the coil current should be reduced. Note: A short circuit could trigger an open coil. Thermal Range 4 = Thermal Warning (ERRb−pin active) Thermal Range 3 T2 Thermal Range 2 T1 Thermal Range 1 Charge Pump Failure −40°C The charge pump is an important circuit that guarantees low RDS(on) for all external MOSFET’s, especially for low supply voltages. If supply voltage is too low or external components are not properly connected to guarantee a low RDS(on) of the drivers, a charge pump failure is latched (<CPFAIL>), the ERRb−pin is activated and the driver is disabled (<MOTEN> = ‘0’). One needs to read Status Register 1 to clear the charge pump failure. After power on reset (POR) the charge pump voltage will need some time to exceed the required threshold. During that time the ERRb−pin will be active but not latched for 250 ms. If the slope of the power supply VBB is slow during power up (charge pump not started after 250 ms), a charge pump failure will be latched and the ERRb−pin is activated (see also Figure 22). Figure 21. Thermal Ranges Over−Current Detection The over−current detection circuit monitors the load current in each activated output stage. If the load current exceeds the over−current detection threshold, the ERRb−pin will be activated and the drivers are switched off (motor driver disabled) to reduce the power dissipation and to protect the H−bridge. Each driver has an individual detection bit (see Status Register 1 and 2). The error condition is latched and the microcontroller needs to read out the error to reset the error and to be able to re−enable the motor driver again. http://onsemi.com 27 AMIS−30422 VBB t VERRb t Charge Pump Failure during start up Charge Pump Failure longer than 250 us due to slow voltage slope Error is latched. Figure 22. Charge Pump Failure Watchdog During and after power up the WDb−pin is an open drain output. One can change this to a push−pull output by using SPI bit <IO_OT>. When VBB is applied, the WDb−pin is kept low for tpor (Table 5). This can for instance be used to reset an external microcontroller at power up. The WDb−pin also has a second function, a Watchdog function. When the watchdog is enabled (<WDEN> = ‘1’), a timer will start counting up. When the counter reaches a certain value (<WDT[3:0]>), the <WD> SPI bit will be set and the WDb−pin will be pulled low for a time equal to tPOR to reset the external microcontroller. To avoid that the microcontroller gets reset, the microcontroller needs to re−enable the watchdog before the count value is reached (= write ‘1’ to <WDEN> before <WDT[3:0]> is reached). This functionality can be used to reset a “stuck” microcontroller. The SPI bit <WD> can be used to detect a cold or warm boot. When powering the application (cold boot), <WD> will be zero. If the microcontroller has been reset by the WDb−pin (warm boot), <WD> bit will be ‘1’. The microcontroller can use this information to detect a cold or warm boot. It’s forbidden to re−enable the watchdog too fast (minimum time between re−enabling must be above tWDPR (see Figure 4)). One may also not enable the watchdog too fast after power up (see tDSPI, Figure 4). A small analogue filter avoids resetting due to spikes or noise on the VDD supply (trf). Error Output The error output (ERRb−pin) will be activated if an error is reported. Next errors will be reported: • Thermal Warning • Thermal Shutdown • Overcurrent • Open Coil • Charge Pump Failure • All errors except a Thermal Warning will disable the H−bridge drivers to protect the motor driver (<MOTEN> = ‘0’). To reset the error one needs to read out the error. Only when all errors are reset it will be possible to re−enable the motor driver (<MOTEN> = ‘1’). Keep in mind that during power up a charge pump failure will be reported during the first 250us but will not be latched (see also Charge Pump Failure). During and after power up the ERRb−pin is an open drain output. One can change this to a push−pull output with SPI bit <IO_OT>. http://onsemi.com 28 AMIS−30422 POWER SUPPLY AND THERMAL CALCULATION • In Sleep Mode (<SLP> = ‘1’) the VBAT consumption is Logic Supply Regulator AMIS−30422 has an on−chip 3.3 V low−drop regulator to supply the digital part of the chip itself, some low−voltage analog blocks and external circuitry. See Table 4 for the limitations. maximum 150 mA making Tj = Tamb. • In Normal Mode when the driver is disabled (<MOTEN> = ‘0’), the VBAT consumption is maximum 20 mA (no external load on VDD−pin). The junction temperature can be calculated as next: Undervoltage T J + T A ) ǒV BAT AMIS−30422 has undervoltage detection. If VBB drops below VBBUL, the drivers are disabled. To be able to enable the drivers again the VBB voltage needs to rise above VBBUH. See also Figure 5. I BAT Rth JAǓ For an 18 V application operating at an ambient temperature of 125°C this would give: T J + 125° C ) ǒ18 V 20 mA 30° CńWǓ Start−Up Behavior T J + 135.8° C Figure 4 gives the start−up of AMIS−30422. After VBB is applied and after a certain power up time (tPU), the internal voltage regulator VDD will start−up. When VDD gets above VDDH, the internal POR will be released and the digital will start−up. The WDb−pin will be kept low for an additional 100ms (tPOR). After the WDb−pin is deactivated and after a time tDSPI, SPI communication can be initiated. • In Normal Mode with the driver enabled (<MOTEN> = ‘1’) the gate charge current needs to be included in the calculations. I BAT + 20 mA ) ǒ6 V REGH C ISS f PWMǓ For an 18 V application driving external MOSFET’s with an input capacitance of 1 nF this would result in: I BAT + 20 mA ) ǒ6 12.8 V 1 nF 30 kHzǓ Junction Temperature Calculation To calculate the junction temperature of AMIS−30422 the thermal resistance junction−to−ambient must be known. When only a PCB heat sink is used, a typical value is 30°C/W (see Table 4). There are three modes the junction temperature can be calculated for. I BAT + 22.3 mA Operating at 125°C ambient temperature this result in a junction temperature of: T J + 125° C ) ǒ18 V 22.3 mA 30° CńWǓ T J + 137° C http://onsemi.com 29 AMIS−30422 SPI INTERFACE DO signal is the output from the Slave (AMIS−30422), and DI signal is the output from the Master. A chip select line (CSb) allows individual selection of a Slave SPI device in a multiple−slave system. The CSb line is active low. If AMIS−30422 is not selected, DO is in HiZ and does not interfere with SPI bus activity. The output type of DO can be set in SPI (<IO_OT>). Since AMIS−30422 operates as a Slave in MODE 0 (CPOL = 0; CPHA = 0) it always clocks data out on the falling edge and samples data in on rising edge of clock. The Master SPI port must be configured in MODE 0 too, to match this operation. The diagram below is both a Master and a Slave timing diagram since CLK, DO and DI pins are directly connected between the Master and the Slave. The serial peripheral interface (SPI) allows an external microcontroller (Master) to communicate with AMIS−30422. The implemented SPI block is designed to interface directly with numerous microcontrollers from several manufacturers. AMIS−30422 acts always as a Slave and can’t initiate any transmission. The operation of the device is configured and controlled by means of SPI registers which are observable for read and/or write from the Master. SPI Transfer Format and Pin Signals During a SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (CLK) synchronizes shifting and sampling of the information on the two serial data lines (DO and DI). 8 7 6 5 4 3 2 1 MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB CS ÏÏÏÏ ÏÏÏÏ CLK DI DO MSB Figure 23. Timing Diagram of a SPI Transfer Transfer Packet Two command types can be distinguished in the communication between master and AMIS−30422: • CMD2 = ‘0’: READ from SPI Register with address ADDR[4:0] • CMD2 = ‘1’: WRITE to SPI Register with address ADDR[4:0] Serial data transfer is assumed to follow MSB first rule. The transfer packet contains one or more bytes. Byte 1 contains the Command and the SPI Register Address and indicates to AMIS−30422 the chosen type of operation and addressed register. Byte 2 contains data, or sent from the Master in a WRITE operation, or received from AMIS−30422 in a READ operation. BYTE1 BYTE2 Command and SPI Register Address Data MSB CMD2 LSB CMD1 Command CMD0 ADDR4 ÏÏÏ ÏÏÏ ÏÏ ÏÏ ADDR3 ADDR2 ADDR1 MSB ADDR0 D7 LSB D6 D5 D4 D3 D2 D1 D0 SPI Register Address Figure 24. SPI Transfer Packet READ Operation the same time the data shifted in from DI (Master) should be interpreted as the following successive command or dummy data. Status Register 0, 1 and 2 (see SPI Registers) contain 7 data bits and a parity check bit. The most significant bit (D7) represents a parity of D[6:0]. If the number of logical ones in D[6:0] is odd, the parity bit D7 equals ‘1’. If the number of logical ones in D[6:0] is even then the parity bit D7 equals If the Master wants to read data from a Status or Control Register, it initiates the communication by sending a READ command. This READ command contains the address of the SPI register to be read out. At the falling edge of the eight clock pulse the data−out shift register is updated with the content of the corresponding internal SPI register. In the next 8−bit clock pulse train this data is shifted out via DO pin. At http://onsemi.com 30 AMIS−30422 root cause of the problem can be determined by reading out the Status Registers. However, if the error occurs at the moment CSb is low, one first needs to pull CSb high to update the Status Registers properly. Only then the Status Registers can be read out to determine the error. For this reason it is also recommended to keep CSb high when the SPI bus is idle. ‘0’. This simple mechanism protects against noise and increases the consistency of the transmitted data. If a parity check error occurs it is recommended to initiate an additional READ command to obtain the status again. The CSb−pin is active low and may remain low between successive READ commands as illustrated in Figure 27. There is one exception. In case an error condition occurs the CS ÏÏÏ ÏÏ ÏÏ ÏÏ CLK DI DO 0 Old Data or Not Valid 0 0 Addr[4] Addr[3] Addr[2] Addr[1] Addr[0] Command or Dummy Command or Dummy Command or Dummy Command or Dummy Command or Dummy Command or Dummy Command or Dummy Command or Dummy D[4 ] from Addr D[3] from Addr D[2 ] from Addr D[1] from Addr D[0 ] from Addr Next command or dummy data Old Data or Not Valid Old Data or Not Valid Old Data or Not Valid Old Data or Not Valid Old Data or Not Valid Old Data or Not Valid Old Data or Not Valid D[7] from Addr D[6 ] from Addr D[5] from Addr Data from previous command or not valid after POR . Figure 25. Single READ Operation Where Data from SPI Register is Read by the Master WRITE Operation less bits are transmitted the complete transfer packet is ignored. A WRITE command executed for a read−only register (e.g. Status Registers) will not affect the addressed register and the device operation. AMIS−30422 responds on every incoming byte by shifting out via DO the data stored in the last received address. Because after a power−on−reset the initial address is unknown the data shifted out via DO is not valid. If the Master wants to write data to a Control Register it initiates the communication by sending a WRITE command. This contains the address of the SPI register to write to. The command is followed with a data byte. This incoming data will be stored in the corresponding Control Register after CSb goes from low to high. It is important that the writing action to the Control Register is exactly 16 bits long and that CSb goes high after these 16 bits. If more or The new data is written into the corresponding internal register at the rising edge of CS. CS ÏÏÏ ÏÏÏ CLK DI DO 1 Old Data or Not Valid ÏÏ ÏÏ ÏÏ 0 0 Addr[4] Addr[3] Addr[2] Addr[1] Addr[0] D[7] from Addr D[6 ] from Addr D[5] from Addr D[4 ] from Addr D[3] from Addr D[2 ] from Addr D[1] from Addr D[0 ] from Addr Old Data or Not Valid Old Data or Not Valid Old Data or Not Valid Old Data or Not Valid Old Data or Not Valid Old Data or Not Valid Old Data or Not Valid Old Data From Addr Old Data From Addr Old Data From Addr Old Data From Addr Old Data From Addr Old Data From Addr Old Data From Addr Old Data From Addr Data from previous command or not valid after POR . Old data from Addr Figure 26. Single WRITE Operation Where Data from the Master is Written in SPI Register Examples of READ and WRITE Operations followed by writing a control byte in Control Register at Addr3. Note that during the WRITE command the old data of the pointed register is returned at the moment the new data is shifted in. In the following examples successive READ and/or WRITE operations are combined. In Figure 27 the Master first reads the status from Register at Addr1 and at Addr2 New data is written into Register with Addr3 at rising edge of CSb CS DI Read Data from Addr1 Read Data from Addr2 Write Data to Addr3 New Data to Addr 3 DO Old Data or Not Valid Data from Addr1 Data from Addr2 Old Data from Addr3 Data from previous command or not valid after POR Figure 27. 2 Successive READ Commands Followed by a WRITE Command http://onsemi.com 31 AMIS−30422 transmitted. This rule also applies when the master device wants to initiate an SPI transfer to read the Status Registers. Because the internal system clock updates the Status Registers only when CSb line is high, the first read out byte might represent old status information (Figure 29). After a WRITE operation the Master could initiate a READ command in order to verify the data correctly written as illustrated in Figure 28. During reception of the READ command the old data is returned for a second time. Only after receiving the READ command the new data is New data is written into Register with Addr4 at rising edge of CSb CS DI Write Data to Addr4 New Data for Addr4 Read Data from Addr4 Command or Dummy DO Old Data or Not Valid Old Data from Addr4 Old Data From Addr4 New Data From Addr4 Data from previous command or not valid after POR Figure 28. WRITE Operation Followed by a READ operation to verify CS DI Read from 0x04 Read from 0x05 Read from 0x06 Command or Dummy DO Old Data or Not Valid Data from 0x04 Data from 0x05 Data from 0x06 Data from previous command or not valid after POR Figure 29. 3 READ Operations in a Row Bad Examples of READ and WRITE Operations be determined. A second problem with Figure 32 is that the data written to Addr9 will not be stored because CSb was not toggled after the write operation. Figure 34 gives the correct way of reading out errors. When the error is detected (toggling of ERRb−pin), CSb is made high to make sure the Status Registers are updated. Then the Status Registers are read out. Notice that ERRb toggles after Status Register 1 is read out (Addr 0x05). This indicates that the error was an overcurrent in the X−coil, a charge pump failure or an open X−coil. Also notice that because CSb is made high after the write operation, the write operation will now be done correctly. The following example demonstrates a bad WRITE operation. After a WRITE operation a read operation is done before CSb is made high. The data will not be written in the Register. Figure 31 demonstrates how it should be done (see also Figure 28). The second example (Figure 32) demonstrates an incorrect way of reading errors. After a WRITE operation the ERRb−pin toggles indication an error. Without toggling CSb the 3 Status Registers are read out to determine the error. Because CSb was not high after the error was detected, the Status Registers will not be updated and the error can not New data is NOT written into Register because WRITE operation did not ended with CSb going high! CS DI Write Data to Addr8 New Data for Addr8 Read Data from Addr8 Command or Dummy Read Data from Addr8 Command or Dummy DO Old Data or Not Valid Old Data from Addr8 Old Data From Addr8 Old Data from Addr8 Old Data From Addr8 Old Data from Addr8 Data from previous command or not valid after POR Data was not written in Addr8 because WRITE operation did not ended with CSb going high! Figure 30. Bad Example of Write Operation http://onsemi.com 32 AMIS−30422 CS DI Write Data to Addr8 New Data for Addr8 Read Data from Addr8 Command or Dummy DO Old Data or Not Valid Old Data from Addr8 Old Data From Addr8 New Data from Addr8 Data from previous command or not valid after POR Figure 31. Good Write Operation ERR CS DI Write Data to Addr9 New Data for Addr9 Read Data from 0x04 Read Data from 0x05 Read Data from 0x06 New Command or Dummy DO Old Data or Not Valid Old Data from Addr9 Old Data From Addr9 Old Data from 0x04 Old Data from 0x05 Old Data from 0x06 Data from previous command or not valid after POR Figure 32. Bad Example of Error Read Out ERR CS Making CSb high will update the Status Registers DI Write Data to Addr9 New Data for Addr9 Read Data from 0x04 Read Data from 0x05 Read Data from 0x06 New Command or Dummy DO Old Data or Not Valid Old Data from Addr9 Old Data From Addr9 New Data from 0x04 New Data from 0x05 New Data from 0x06 Data from previous command or not valid after POR Figure 33. Correct Read Out of Error SPI Register Description Below table gives an overview of all SPI Registers that can be used. Table 8. SPI REGISTER OVERVIEW Address Access Abbreviation Watchdog Register SPI Register 0x00 R/W WR Control Register 0 0x01 R/W CR0 Control Register 1 0x02 R/W CR1 Control Register 2 0x03 R/W CR2 Control Register 3 0x04 R/W CR3 Status Register 0 0x05 R SR0 Status Register 1 0x06 R SR1 Status Register 2 0x07 R SR2 Status Register 3 0x08 R SR3 http://onsemi.com 33 AMIS−30422 Table 8. SPI REGISTER OVERVIEW Address Access Abbreviation Status Register 4 SPI Register 0x09 R SR4 Predriver Register 0 0x0A R/W PDRV0 Predriver Register 1 0x0B R/W PDRV1 Predriver Register 2 0x0C R/W PDRV2 Predriver Register 3 0x0D R/W PDRV3 Where: R/W = read and write access, R = read access only Watchdog Register (WR) The Watchdog Register is located at address 0x00 and can be used to enable the watchdog and set the watchdog time−out. It can also be used to set the short circuit and open coil detection time−out. Table 9. WATCHDOG REGISTER Watchdog Register (WR) Address 0x00 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 1 0 0 Data WDEN WDT[3:0] OPEN_COIL[1:0] − Table 10. WATCHDOG REGISTER PARAMETERS Parameter WDEN WDT[3:0] OPEN_COIL[1:0] Value Value 0 Disable 1 Enable 0000 32 ms 0001 64 ms 0010 96 ms 0011 128 ms 0100 160 ms 0101 192 ms 0110 224 ms 0111 256 ms 1000 288 ms 1001 320 ms 1010 352 ms 1011 384 ms 1100 416 ms 1101 448 ms 1110 480 ms 1111 512 ms 00 2.56 ms 01 0.32 ms 10 20.48 ms 11 163.84 ms Description Info Enables the watchdog p28 Defines the watchdog time−out period. The watchdog needs to be re−enabled (WDEN) within this time or WDb−pin is activated for tPOR. p28 Defines the open coil detection time−out. If an open coil is detected for a time longer than OpenTimeOut[1:0], an open coil (OPEN_X and/or OPEN_Y) will be reported. Note: Short circuit could trigger open coil detection. p27 Remark: Bit 0 of Watchdog Register should always be ‘0’ (zero)! http://onsemi.com 34 AMIS−30422 Control Register 0 (CR0) Control Register 0 is located at address 0x01 and is used to set the maximum coil current and stepping mode. Table 11. CONTROL REGISTER 0 Control Register 0 (CR0) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 1 1 1 0x01 SM[3:0] Data − CUR[2:0] Table 12. CONTROL REGISTER 0 PARAMETERS Parameter SM[3:0] CUR[2:0] Value Value 0000 128th Description 0001 64th 0010 32nd 0011 16th 0100 8th 0101 4th 0110 Half step 0111 Full Step 1111 Full Step + 1/2 rotation Other Reserved 000 VREF / 40 001 VREF / 20 010 3 x VREF / 40 011 VREF / 10 100 VREF / 8 101 3 x VREF / 20 110 7 x VREF / 40 111 VREF / 5 Info Defines the 8 stepping modes for the PWM regulator. p23 Defines the maximum voltage over the coil current sense resistor which defines the maximum coil current. The maximum coil current is calculated as next: Icoil = CUR[2:0] / Rsense VREF = voltage on REF−pin (with a maximum of 2 V) p24 Control Register 1 (CR1) Control Register 1 is located at address 0x02 and can used to set the direction, NXT−pin polarity, output configuration of WDb− and ERRb− pin and to enable PWM jitter. It can also be used to set the coil current zero−crossing. Table 13. CONTROL REGISTER 1 Control Register 1 (CR1) Address Access 0x02 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 Reset 0 0 0 1 1 0 Data DIRCTRL NXTP − WDb_OD ERRb_OD PWMJ http://onsemi.com 35 MINSLATIME[1:0] AMIS−30422 Table 14. CONTROL REGISTER 1 PARAMETERS Parameter Value Value 0 CW 1 CCW 0 Positive Edge 1 Negative Edge Description DIRCTRL NXTP WDb_OD ERRb_OD PWMJ MINSLATIME[1:0] 0 Push Pull 1 Open Drain 0 Push Pull 1 Open Drain 0 Disabled 1 Enabled 00 40 ms 01 120 ms 10 200 ms 11 360 ms Info Defines the direction of rotation. Remark: CW and CCW is relative. Direction of rotation will be defined by the status of the DIR−pin and connection of the stepper motor! p23 Defines the active edge on the NXT−pin. p23 Defines the output type of WDb−pin p28 Defines the output type of ERRb−pin p28 Enables or disables PWM jitter p14 Defines the time coil current zero−crossing extension time. p21 Remark: Bit 5 of Control Register 1 should always be ‘0’ (zero)! Control Register 2 (CR2) Control Register 2 is located at address 0x03 and can be used to enable the motor driver and to put the motor driver in sleep mode. It also has some parameters that can be used to set the SLA. Table 15. CONTROL REGISTER 2 Control Register 2 (CR2) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Data MOTEN SLP − SLAT 0x03 SLAG[2:0] SLA_OFFS Table 16. CONTROL REGISTER 2 PARAMETERS Parameter MOTEN SLP SLAT Value Value Description Info 0 Disabled 1 Enabled Enables the PWM regulator. Remark: the regulator is automatically disabled if one of the bits in Status Register 1 or 2 is set. p23 0 Normal Mode 1 Sleep Mode Enables the sleep mode (power down mode) p26 0 Not Transparent 1 Transparent Defines the type of SLA sampling. p24 http://onsemi.com 36 AMIS−30422 Table 16. CONTROL REGISTER 2 PARAMETERS Parameter SLAG[2:0] SLA_OFFS Value Value 000 1 Description 001 0.5 010 0.25 011 0.125 100 0.0625 101 0.0625 110 0.0625 111 0.0625 0 No additional offset 1 Additional offset of 0.6 V Info Defines the motor terminal voltage division factor for the SLA−pin. p24 To enable an additional offset on the SLA−pin of 0.6V. p24 Remark: Bit 5 of Control Register 2 should always be ‘0’ (zero)! Control Register 3 (CR3) Control Register 3 is located at address 0x04 and is used to set the hold coil current functionality. Table 17. CONTROL REGISTER 3 Control Register 3 (CR3) Address 0x04 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 0 1 0 0 1 1 1 Data EN_HOLD - HOLD_TIME[1:0] - HOLD_CUR[2:0] Table 18. CONTROL REGISTER 3 PARAMETERS Parameter EN_HOLD HOLD_TIME[1:0] HOLD_CUR[2:0] Value Value 0 Disable 1 Enable 00 128 ms 01 256 ms 10 512 ms 11 1024 ms 000 VREF / 40 001 VREF / 20 010 3 x VREF / 40 011 VREF / 10 100 VREF / 8 101 3 x VREF / 20 110 7 x VREF / 40 111 VREF / 5 Description Info Enable or disable the automatic switching from CUR[2:0] to HOLD_CUR[2:0] p24 If EN_HOLD is set to 1 and no NXT pulses are detected for a time minimum to the HOLD_TIME[1:0], coil current will be set to HOLD_CUR[2:0] p24 Defines the maximum voltage over the coil current sense resistor which defines the maximum coil current. The maximum coil current is calculated as next: Icoil = HOLD_CUR[2:0] / Rsense VREF = voltage on REF−pin (with a maximum of 2 V) p24 Remark: Bit 3 and 6 should always be ‘0’+ (zero)! http://onsemi.com 37 AMIS−30422 Status Register 0 (SR0) Status Register 0 is located at address 0x05 and can only be read. Status Register 0 is a non−latched register meaning that the value of the register can change without the need of reading out the register. The register can be used to retrieve the temperature range or to verify a watchdog event. Notice that bit 7 is the parity bit (see READ operation p30). Table 19. STATUS REGISTER 0 Status Register 0 (SR0) Address 0x05 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R R R R R R R R Reset 0 0 0 0 0 1 0 0 Data PAR WD − − − − TR[1:0] Table 20. STATUS REGISTER 0 PARAMETERS Parameter TR[1:0] Value Value Description 00 −40°C to 15°C 01 15°C to 72°C 10 73°C to 150°C 11 TSD = 0: 150°C to 170°C TSD = 1: >170°C 0 No watchdog event Motor driver thermal range. Remark: TR[1:0] = 11 and TSD = 0 => Thermal Warning TR[1:0] = 11 and TSD = 1 => Thermal Shutdown TSD is located in Status Register 2 p27 If WDEN = 1 and watchdog not acknowledged before the Watchdog Time−out (WDT[3:0]), WDb−pin will be pulled low for 100ms to reset an external microcontroller and WD bit will be set to ‘1’ to indicate this event. The external microcontroller can use this bit to verify a cold (WD = 0) or warm boot (WD = 1). WD 1 Info Watchdog event occurred p28 Status Register 1 (SR1) Status Register 1 is located at address 0x06 and can only be read. Status Register 1 is a latched register. If an error occurs the bit will be set and can only be cleared by reading out this bit1. The register is used to report an overcurrent or open coil in the X−coil, or to report a charge pump failure. Notice that bit 7 is the parity bit (see READ operation p30). Table 21. STATUS REGISTER 1 Status Register 1 (SR1) Address 0x06 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Data PAR OVCXPT OVCXPB OVCXNT OVCXNB CPFAIL OPEN_X − 1. In Sleep mode the register can be read out but will not be cleared! http://onsemi.com 38 AMIS−30422 Table 22. STATUS REGISTER 1 PARAMETERS Parameter Value Value 0 No overcurrent 1 Overcurrent 0 No overcurrent 1 Overcurrent 0 No overcurrent 1 Overcurrent 0 No overcurrent 1 Overcurrent 0 No charge pump failure 1 Charge pump failure 0 No open coil detected 1 Open coil detected OVCXPT OVCXPB OVCXNT OVCXNB CPFAIL OPEN_X Description Info Overcurrent detection in top transistor XP−terminal p27 Overcurrent detection in bottom transistor XP−terminal p27 Overcurrent detection in top transistor XN−terminal p27 Overcurrent detection in bottom transistor XN−terminal p27 Charge pump failure detection p27 Open coil detection for X−coil Note: a short circuit could trigger an open coil p27 Status Register 2 (SR2) Status Register 2 is located at address 0x07 and can only be read. Status Register 2 is a latched register. If an error occurs the bit will be set and can only be cleared by reading out this bit2. The register is used to report an overcurrent or open coil in the Y−coil, or to report a thermal shutdown. Notice that bit 7 is the parity bit (see READ operation p30). Table 23. STATUS REGISTER 2 Status Register 2 (SR2) Address 0x07 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Data PAR OVCYPT OVCYPB OVCYNT OVCYNB TSD OPEN_Y − Table 24. STATUS REGISTER 2 PARAMETERS Parameter OVCYPT OVCYPB OVCYNT OVCYNB TSD OPEN_Y Value Value Description 0 No overcurrent 1 Overcurrent 0 No overcurrent 1 Overcurrent 0 No overcurrent 1 Overcurrent 0 No overcurrent 1 Overcurrent 0 No thermal shutdown 1 Thermal shutdown 0 No open coil detected 1 Open coil detected Info Overcurrent detection in top transistor YP−terminal p27 Overcurrent detection in bottom transistor YP−terminal p27 Overcurrent detection in top transistor YN−terminal p27 Overcurrent detection in bottom transistor YN−terminal p27 Thermal Shutdown detection p27 Open coil detection for X−coil Note: a short circuit could trigger an open coil p27 2. In Sleep mode the register can be read out but will not be cleared! http://onsemi.com 39 AMIS−30422 Status Register 3 (SR3) Status Register 3 is located at address 0x08 and can only be read. Status Register 3 contains the highest 8 bits of the microstepping position and can be used to retrieve the position in the translator table (see Table 7). It is a non−latched register meaning that the microstepping position can be updated by the motor driver at any moment. Status Register 3 does not contain a parity bit. Table 25. STATUS REGISTER 3 Status Register 3 (SR3) Address 0x08 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 MSP[8:1] Data Table 26. STATUS REGISTER 3 PARAMETERS Parameter Value Value Description MSP[8:1] xxxx xxxx Microstepping position Info Indicates the position within the translator table p23 Status Register 4 (SR4) Status Register 4 is located at address 0x09 and can only be read. Status Register 4 contains the lowest 8 bits of the microstepping position and can be used to retrieve the position in the translator table (see Table 7). It is a non-latched register meaning that the microstepping position can be updated by the motor driver at any moment. Status Register 4 does not contain a parity bit. Table 27. STATUS REGISTER 4 Status Register 4 (SR4) Address 0x09 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 MSP[7:0] Data Table 28. STATUS REGISTER 4 PARAMETERS Parameter Value Value MSP[7:0] xxxx xxxx Microstepping position Description Indicates the position within the translator table http://onsemi.com 40 Info p23 AMIS−30422 Predriver Register 0 (PDRV0) Predriver Register 0 is located at address 0x0A and can be used to set the current source for the gate charge and discharge (see Figure 11). Table 29. PREDRIVER REGISTER 0 Predriver Register 0 (PDRV0) Address 0x0A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Data ION[3:0] IOFF[3:0] Table 30. PREDRIVER REGISTER 0 PARAMETERS Parameter Value ION[3:0] xxxx IOFF[3:0] xxxx Value Description Info Current source value Defines the current source for charging and discharging of the external MOSFET’s. Current source can be calculated as next: 3 mA + (ION[3:0] x 2 mA) and 3 mA + (IOFF[3:0] x 2 mA) p13 Predriver Register 1 (PDRV1) Predriver Register 1 is located at address 0x0B and can be used to set the non-overlap time as well as t2 (see Figure 11). Table 31. PREDRIVER REGISTER 1 Predriver Register 1 (PDRV1) Address 0x0B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 0 0 0 0 0 0 Data NO_CROSS[1:0] TOP_t2[2:0] BOT_t2[2:0] Table 32. PREDRIVER REGISTER 1 PARAMETERS Parameter NO_CROSS[2:0] TOP_t2[2:0] Value Value 00 0 01 40 ms 10 80 ms 11 160 ms 000 1.25 ms 001 1.75 ms 010 2.25 ms 011 2.75 ms 100 3.25 ms 101 3.75 ms 110 4.25 ms 111 4.75 ms Description Info Defines time between switching off one transistor and switching on the next. p13 Defines the switch on duration t2 for the external top MOSFET’s. p13 http://onsemi.com 41 AMIS−30422 Table 32. PREDRIVER REGISTER 1 PARAMETERS Parameter BOT_t2[2 :0] Value Value 000 1.25 ms 001 1.75 ms 010 2.25 ms 011 2.75 ms 100 3.25 ms 101 3.75 ms 110 4.25 ms 111 4.75 ms Description Info Defines the switch on duration t2 for the external bottom MOSFET’s. p13 Predriver Register 2 (PDRV2) Predriver Register 2 is located at address 0x0C and can be used to set toff (see Figure 11). Table 33. PREDRIVER REGISTER 2 Predriver Register 2 (PDRV2) Address 0x0C Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 1 0 0 0 1 Data - TOP_toff[2:0] - BOT_toff[2:0] Table 34. PREDRIVER REGISTER 2 PARAMETERS Parameter TOP_toff[2:0] BOT_toff[2 :0] Value Value 000 1.25 ms 001 1.75 ms 010 2.25 ms 011 2.75 ms 100 3.25 ms 101 3.75 ms 110 4.25 ms 111 4.75 ms 000 1.25 ms 001 1.75 ms 010 2.25 ms 011 2.75 ms 100 3.25 ms 101 3.75 ms 110 4.25 ms 111 4.75 ms Description Info Defines the switch off duration toff for the external top MOSFET’s. p13 Defines the switch off duration toff for the external bottom MOSFET’s. p13 http://onsemi.com 42 AMIS−30422 Predriver Register 3 (PDRV3) Predriver Register 3 is located at address 0x0D and can be used to set t1 (see Figure 11). Table 35. PREDRIVER REGISTER 3 Predriver Register 3 (PDRV3) Address 0x0D Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 1 0 0 0 1 Data - TOP_t1[2:0] - BOT_t1[2:0] Table 36. PREDRIVER REGISTER 3 PARAMETERS Parameter TOP_t1[2:0] BOT_t1[2 :0] Value Value 000 375 ns 001 500 ns 010 625 ns 011 750 ns 100 825 ns 101 1000 ns 110 1125 ns 111 1250 ns 000 375 ns 001 500 ns 010 625 ns 011 750 ns 100 825 ns 101 1000 ns 110 1125 ns 111 1250 ns Description Info Defines the switch on duration t1 for the external top MOSFET’s. p13 Defines the switch on duration t1 for the external bottom MOSFET’s. p13 http://onsemi.com 43 AMIS−30422 PACKAGE THERMAL CHARACTERISTICS 37 39 38 41 40 42 43 44 46 45 47 48 The major thermal resistances of the device are the Rth from the junction to the ambient (Rthja) and the overall Rth from the junction to exposed pad (Rthjp). In Table 4 one can find the values for the Rthja and Rthjp, simulated according to JESD−51. The Rthja for 2S2P is simulated conform JEDEC JESD−51 as follows: • A 4−layer printed circuit board with inner power planes and outer (top and bottom) signal layers is used • Board thickness is 1,46mm (FR4 PCB material) • The 2 signal layers: 70 um thick copper with an area of 5500 mm2 copper and 20% conductivity • The 2 power internal planes: 36 mm thick copper with an area of 5500 mm2 copper and 90% conductivity The Rthja for 1S0P is simulated conform to JEDEC JESD−51 as follows: • A 1−layer printed circuit board with only 1 layer • Board thickness is 1.46 mm (FR4 PCB material) • The layer has a thickness of 70 mm copper with an area of 5500 mm2 copper and 20% conductivity 37 39 38 41 40 42 43 44 46 45 47 48 The AMIS−30422 is available in a NQFP48 package. For cooling optimizations, the NQFP has an exposed thermal pad which has to be soldered to the PCB ground plane. The ground plane needs thermal vias to conduct the heat to the bottom layer. Figure 34 gives an example of good heat transfer. The exposed thermal pad is soldered directly on the top ground layer (left picture of Figure 34). It’s advised to make the top ground layer as large as possible (see arrows Figure 34). To improve the heat transfer even more, the exposed thermal pad is connected to a bottom ground layer by using thermal vias (see right picture of Figure 34). It’s advised to make this bottom ground layer as large as possible and with as less as possible interruptions. For precise thermal cooling calculations the major thermal resistances of the device are given (Table 4). The thermal media to which the power of the devices has to be given are: • Static environmental air (via the case) • PCB board copper area (via the exposed pad) 29 9 28 10 27 10 27 11 26 11 26 12 25 12 25 13 24 8 28 22 29 9 23 8 21 30 20 7 19 30 18 31 7 17 6 16 31 15 32 6 14 5 24 32 22 33 5 23 4 21 33 20 34 4 19 3 18 34 17 35 3 16 36 2 15 1 35 13 36 14 1 2 Figure 34. PCB Ground Plane Layout Condition (left picture displays the top ground layer, right picture displays the bottom ground layer) ORDERING INFORMATION Part No. AMIS30422C422G Peak Current Temperature Range Package Shipping† NA −40°C to +170°C NQFP−48 (7 x 7 mm) (Pb−Free) Units / Tube AMIS30422C422MNTWG Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 44 AMIS−30422 PACKAGE DIMENSIONS QFN48 7x7, 0.5P CASE 485AJ ISSUE O ÈÈÈ ÈÈÈ PIN 1 LOCATION D NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO THE PLATED TERMINAL AND IS MEASURED ABETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A B E L 2X 0.15 C DETAIL A OPTIONAL CONSTRUCTION 2X SCALE 2X 0.15 C TOP VIEW (A3) 0.05 C DIM A A1 A3 b D D2 E E2 e K L MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 7.00 BSC 5.00 5.20 7.00 BSC 5.00 5.20 0.50 BSC 0.20 −−− 0.30 0.50 A 0.08 C A1 NOTE 4 C SIDE VIEW SOLDERING FOOTPRINT* 2X D2 DETAIL A SEATING PLANE 5.20 K 13 25 12 1 E2 2X 7.30 48X 0.63 1 36 48 48X L 37 e e/2 48X BOTTOM VIEW b 0.10 C A B 0.05 C 48X 0.30 0.50 PITCH DIMENSIONS: MILLIMETERS NOTE 3 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 45 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative AMIS−30422/D