MAXIM MXL1543CAI

19-1929; Rev 1; 9/01
+5V Multiprotocol, 3Tx/3Rx, SoftwareSelectable Clock/Data Transceivers
Features
♦ MXL1543, MXL1544/MAX3175, and MXL1344A
Chipset Is Pin Compatible with LTC1543,
LTC1544, and LTC1344A
♦ Supports RS-232, RS-449, EIA-530, EIA-530A,
V.35, V.36, and X.21
♦ Software-Selectable Cable Termination Using the
MXL1344A
♦ Complete DTE or DCE Port with MXL1544/
MAX3175, and MXL1344A
♦ +5V Single-Supply Operation
♦ 0.5µA No-Cable Mode
♦ TUV-Certified NET1/NET2 and TBR1/TBR2Compliant
Ordering Information
Applications
Data Networking
PCI Cards
CSU and DSU
Telecommunications
Equipment
Data Routers
PART
TEMP. RANGE
MXL1543CAI
0° to +70°C
PIN-PACKAGE
28 SSOP
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
D4
LL
CTS
DSR
R4
R3
R2
R1
MXL1544
MAX3175
DCD
DTR
RTS
D3
D2
D1
RXD
RXC
R3
R2
TXC
R1
MXL1543
D3
SCTE TXD
D2
D1
MXL1344A
18
13 5 10 8
22 6
23 20 19 4
1
7
16 3
9 17
12 15 11 24 14 2
TXD A (103)
TXD B
SCTE A (113)
SCTE B
TXC A (114)
TXC B
RXC A (115)
RXC B
RXD A (104)
RXD B
SG (102)
SHIELD (101)
RTS A (105)
RTS B
DTR A (108)
DTR B
DCD A (107)
DCD B
DSR A (109)
DSR B
CTS A (106)
CTS B
LL A (141)
DB-25 CONNECTOR
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MXL1543
General Description
The MXL1543 is a three-driver/three-receiver multiprotocol transceiver that operates from a +5V single supply. The MXL1543, along with the MXL1544/MAX3175
and the MXL1344A, form a complete software-selectable data terminal equipment (DTE) or data communication equipment (DCE) interface port that supports the
V.28 (RS-232), V.10/V.11 (RS-449/V.36, EIA-530, EIA530A, X.21), and V.35 protocols. The MXL1543 transceivers carry the high-speed clock and data signals
while the MXL1544/MAX3175 carry the control signals.
The MXL1543 can be terminated by the MXL1344A
software-selectable resistor termination network or by
discrete termination networks.
An internal charge pump and a proprietary low-dropout
transmitter output stage allow V.11- , V.28- , and V.35compliant operation from a +5V single supply. A nocable mode is entered when all mode pins (M0, M1,
and M2) are pulled high or left unconnected. In nocable mode, supply current decreases to 0.5µA and all
transmitter and receiver outputs are disabled (high
impedance). Short-circuit current limiting and thermal
shutdown circuitry protect the drivers against excessive
power dissipation.
MXL1543
+5V Multiprotocol, 3Tx/3Rx, SoftwareSelectable Clock/Data Transceivers
ABSOLUTE MAXIMUM RATINGS
All Voltages Referenced to GND Unless Otherwise Noted.
Supply Voltages
VCC .......................................................................-0.3V to +6V
VDD ....................................................................-0.3V to +7.3V
VEE.....................................................................+0.3V to -6.5V
VDD to VEE (Note 1) ................................................................13V
Logic Input Voltages
M0, M1, M2, DCE/DTE, T_IN ................................-0.3V to +6V
Logic Output Voltages
R_OUT ....................................................-0.3V to (VCC + 0.3V)
Transmitter Outputs
T_OUT_, T3OUT_/R1IN_.....................................-15V to +15V
Short-Circuit Duration............................................Continuous
Note 1: VDD and VEE absolute difference cannot exceed 13V.
Receiver Input
R_IN_T3OUT_/R1IN_ ..........................................-15V to +15V
Continuous Power Dissipation (TA = +70°C)
28-Pin SSOP (derate 11.1mW/°C above +70°C) .........889mW
Operating Temperature Range
MXL1543CAI .......................................................0°C to 70°C
Junction Temperature .......................................................150°C
Storage Temperature Range ...........................-65°C to +150°C
Lead Temperature (soldering, 10s) ...............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +5.0V, C1 = C2 = C4 = 1µF, C3 = C5 = 4.7µF, (Figure 10), TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5.25
V
DC CHARACTERISTICS
VCC Operating Range
Supply Current
(DCE Mode)
(Digital Inputs = GND or
VCC)
(Transmitter Outputs Static)
Internal Power Dissipation
(DCE Mode)
Positive Charge-Pump
Output Voltage
Negative Charge-Pump
Output Voltage
Supply Rise Time
VCC
ICC
PD
VDD
VEE
tr
4.75
RS-530, RS-530A, X.21, no load
13
RS-530, RS-530A, X.21, full load
100
V.35 mode, no load
20
V.35 mode, full load
126
V.28 mode, no load
20
V.28 mode, full load
40
75
No-cable mode
0.5
10
RS-530, RS-530A, X.21, full load
230
V.35 mode, full load
600
V.28 mode, full load
140
Any mode (except no-cable mode), no load
6.4
6.8
V.28 mode, with load
6.4
6.8
V.28, V.35 modes, with load, IDD = 10mA
6.4
6.8
130
170
mA
µA
mW
V
V.28, V.35, no load
-5.6
V.28 mode, full load
-5.6
-5.4
V.35 mode, full load
-5.6
-5.4
RS-530, RS-530A, X.21, full load
-5.6
-5.4
No-cable mode or power-up to turn on
500
V
µs
LOGIC INPUTS (M0, M1, M2, DCE/DTE, T1IN, T2IN, T3IN)
Input High Voltage
VIH
Input Low Voltage
VIL
2.0
0.8
T1IN, T2IN, T3IN
Logic Input Current
IIN
M0, M1, M2, DCE/DTE = GND
±10
-100
-50
M0, M1, M2, DCE/DTE = VCC
2
V
_______________________________________________________________________________________
-30
±10
µA
+5V Multiprotocol, 3Tx/3Rx, SoftwareSelectable Clock/Data Transceivers
(VCC = +5.0V, C1 = C2 = C4 = 1µF, C3 = C5 = 4.7µF, (Figure 10), TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
3
4.5
MAX
UNITS
LOGIC OUTPUTS (R1OUT, R2OUT, R3OUT)
Output High Voltage
VOH
ISOURCE = 4mA
Output Low Voltage
VOL
ISINK = 4mA
Output Short-Circuit Current
ISC
0 ≤ VOUT ≤ VCC
Output Pullup Current
IL
0.3
0.8
±50
VOUT = 0, no-cable mode
V
mA
µA
70
V.11 TRANSMITTER
Open-Circuit Differential Output
Voltage
VODO
Loaded Differential Output
Voltage
VODL
Open circuit, R = 1.95kΩ (Figure 1)
R = 50Ω (Figure 1), TA = +25oC
R = 50Ω (Figure 1)
0.5 ✕
VODO
±5
V
0.67 ✕
VODO
V
±2
Change in Magnitude of Output
Differential Voltage
∆VOD
R = 50Ω (Figure 1)
0.2
V
Common-Mode Output Voltage
VOC
R = 50Ω (Figure 1)
3.0
V
Change in Magnitude of Output
Common-Mode Voltage
∆VOC
R = 50Ω (Figure 1)
0.2
V
VOUT = GND
150
mA
±1
±100
µA
10
25
ns
Short-Circuit Current
Output Leakage Current
Rise or Fall Time
ISC
IZ
-0.25V ≤ VOUT ≤ +0.25V, power-off or
no-cable mode
tr, tf
(Figures 2, 6)
Transmitter Input to Output
Delay
tPHL , tPLH
(Figures 2, 6)
40
80
ns
Data Skew
ItPHL- tPLHI
(Figures 2, 6)
3
12
ns
tSKEW
(Figures 2, 6)
3
Output to Output Skew
2
ns
V.11 RECEIVER
Differential Threshold Voltage
Input Hysteresis
VTH
-7V ≤ VCM ≤ 7V
∆VTH
-7V ≤ VCM ≤ 7V
-200
15
200
mV
40
mV
±0.66
mA
IIN
-10V ≤ VA, B ≤10V
Receiver Input Resistance
RIN
-10V ≤ VA, B ≤ 10V
Rise or Fall Time
tr, tf
(Figures 2, 7)
15
tPHL,tPLH
(Figures 2, 7)
50
80
ns
|tPHL- tPLH|
(Figures 2, 7)
4
16
ns
±0.44
±0.55
±0.66
Receiver Input Current
Receiver Input to Output Delay
Data Skew
15
30
kΩ
ns
V.35 TRANSMITTER
±7
Open circuit (Figure 3)
V
Differential Output Voltage
VOD
Output High Current
IOH
VA,B = 0
-13
-11
-9
mA
Output Low Current
IOL
VA,B = 0
9
11
13
mA
With load, -4V ≤ VCM ≤ 4V (Figure 3)
_______________________________________________________________________________________
3
MXL1543
ELECTRICAL CHARACTERISTICS (continued)
MXL1543
+5V Multiprotocol, 3Tx/3Rx, SoftwareSelectable Clock/Data Transceivers
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5.0V, C1 = C2 = C4 = 1µF, C3 = C5 = 4.7µF, (Figure 10), TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER
TYP
MAX
UNITS
-0.25V ≤ VOUT ≤ +0.25V, power-off or nocable mode
±1
±100
µA
tr, tf
(Figures 3, 6)
5
Transmitter Input to Output
Delay
tPHL, tPLH
(Figures 3, 6)
35
80
ns
Data Skew
|tPHL–tPLH|
(Figures 3, 6)
4
16
ns
tSKEW
(Figures 3, 6)
4
Output Leakage Current
Rise or Fall Time
Output-to-Output Skew
SYMBOL
IZ
CONDITIONS
MIN
ns
ns
V.35 RECEIVER
Differential Input Voltage
Input Hysteresis
VTH
-2V ≤ VCM ≤ 2V (Figure 3)
∆VTH
-2V ≤ VCM ≤ 2V (Figure 3)
-200
15
200
mV
40
mV
±0.66
mA
Receiver Input Current
IIN
-10V ≤ VA,B ≤ 10V
Receiver Input Resistance
RIN
-10V ≤ VA,B ≤ 10V
Rise or Fall Time
tr, tf
(Figures 3, 7)
15
Receiver Input to Output Delay
tPHL, tPLH
(Figures 3, 7)
50
80
ns
Data Skew
|tPHL–tPLH|
(Figures 3, 7)
4
16
ns
15
30
kΩ
ns
V.28 TRANSMITTER
Output Voltage Swing (Figure 4)
VO
Short-Circuit Current
ISC
±7
Open circuit
RL = 3kΩ
±5
±6
V
±150
mA
±100
µA
30
V/µs
Output Leakage Current
IZ
-0.25V ≤ VOUT ≤ +0.25V, power-off or nocable mode
Output Slew Rate
SR
RL = 3kΩ, CL = 2500pF (Figures 4, 8)
Transmitter Input to Output
Delay
tPHL
RL = 3kΩ, CL = 2500pF (Figures 4, 8)
1.5
2.5
µs
Transmitter Input to Output
Delay
tPLH
RL = 3kΩ, CL = 2500pF (Figures 4, 8)
1.5
3
µs
±1
4
V.28 RECEIVER
Input Threshold Low
VIL
Input Threshold High
VIH
0.8
1.2
V
1.2
2.0
V
0.05
0.3
V
5
7
kΩ
Input Hysteresis
VHYST
Input Resistance
RIN
-15V ≤ VIN ≤ +15V
Rise or Fall Time
tr, tf
(Figures 5, 9)
Receiver Input to Output Delay
tPHL
(Figures 5, 9)
60
100
ns
Receiver Input to Output Delay
tPLH
(Figures 5, 9)
160
250
ns
4
3
15
_______________________________________________________________________________________
ns
+5V Multiprotocol, 3Tx/3Rx, SoftwareSelectable Clock/Data Transceivers
V.28 SUPPLY CURRENT
vs. DATA RATE
80
60
40
100
1000
50
DATA RATE (kbps)
V.11 DRIVER DIFFERENTIAL OUTPUT
VOLTAGE vs. TEMPERATURE
VOUT+
250
2
1
0
-1
VOUT-
2
0
-2
-4
-6
-4
-8
-5
VOUT+
4
20
30
40
50
60
70
100
1000
10,000
0.66
VOH
DCE MODE, VCM = 0
FULL LOAD
0.44
0.22
0
-0.22
-0.44
VOUT-
VOL
-0.66
-10
10
10
V.35 OUTPUT VOLTAGE
vs. TEMPERATURE
6
-3
0
0.1
0.1
DATA RATE (kbps)
DCE MODE, RL = 3kΩ
8
OUTPUT VOLTAGE (V)
3
-2
200
10
MXL1543 toc04
DCE MODE, R = 50Ω
100
150
DATA RATE (kbps)
V.28 OUTPUT VOLTAGE
vs. TEMPERATURE
5
4
DCE MODE, FULL LOAD, ALL TRANSMITTERS
OPERATING AT THE SPECIFIED DATA RATE
0
0
10,000
OUTPUT VOLTAGE (V)
100
10
MXL1543 toc05
1
60
20
0
0.1
80
40
DCE MODE, R = 50Ω, ALL TRANSMITTERS
OPERATING AT THE SPECIFIED DATA RATE
0
0
10
20
30
40
50
60
70
TEMPERATURE (°C)
TEMPERATURE (°C)
20
30
40
50
TEMPERATURE (°C)
V.35 DIFFERENTIAL OUTPUT VOLTAGE
vs. COMMON-MODE VOLTAGE
V.11/V.35 RECEIVER INPUT CURRENT
vs. INPUT VOLTAGE
V.28 RECEIVER INPUT CURRENT
vs. INPUT VOLTAGE
580
|VOD|
570
560
550
540
530
520
DCE MODE
200
100
0
-100
-200
-3
-2
-1
0
1
2
COMMON-MODE VOLTAGE (V)
3
4
60
70
2.5
2.0
DCE MODE
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-2.5
-300
-4
10
MXL1543 toc09
300
0
RECEIVER INPUT CURRENT (mA)
590
RECEIVER INPUT CURRENT (µA)
MXL1543 toc07
600
MXL1543 toc08
DRIVER DIFFERENTIAL OUTPUT VOLTAGE (V)
120
20
20
DIFFERENTIAL OUTPUT VOLTAGE (mV)
MXL1543 toc02
60
40
160
140
MXL1543 toc06
100
200
180
SUPPLY CURRENT (mA)
120
DCE MODE ALL TRANSMITTERS
OPERATING AT THE SPECIFIED DATA RATE
RL = 3kΩ, CL = 2500pF
80
SUPPLY CURRENT (mA)
140
SUPPLY CURRENT (mA)
100
MXL1543 toc01
160
V.35 SUPPLY CURRENT
vs. DATA RATE
MXL1543 toc03
V.11 SUPPLY CURRENT
vs. DATA RATE
-10 -8
-6
-4
-2
0
2
4
INPUT VOLTAGE (V)
6
8
10
-10 -8
-6
-4
-2
0
2
4
6
8
10
INPUT VOLTAGE (V)
_______________________________________________________________________________________
5
MXL1543
Typical Operating Characteristics
(VCC = +5.0V, C1 = C2 = C4 =1µF, C3 = C5 = 4.7µF, (Figure 10), TA = TMIN to TMAX, TA = +25°C, unless otherwise noted.)
+5V Multiprotocol, 3Tx/3Rx, SoftwareSelectable Clock/Data Transceivers
MXL1543
Typical Operating Characteristics (continued)
(VCC = +5.0V, C1= C2 = C4 =1µF, C3 = C5 = 4.7µF (Figure 10), TA = +25°C, unless otherwise noted.)
V.11 LOOPBACK OPERATION
V.28 LOOPBACK OPERATION
MXL1543 toc10
R = 50Ω
5V/div
TIN
TOUT/RIN
5V/div
ROUT
5V/div
5V/div
TIN
TOUT/RIN
5V/div
TOUT/RIN
ROUT
5V/div
5V/div
ROUT
V.28 SLEW RATE vs. CLOAD
V.11 TRANSMITTER PROPAGATION DELAY
vs. TEMPERATURE
V.11 RECEIVER PROPAGATION DELAY
vs. TEMPERATURE
RL = 3kΩ
1 TRANSMITTER SWITCHING AT 250kbps.
OTHER TRANSMITTERS SWITCHING AT 15kbps
1000
2000
3000
4000
PROPAGATION DELAY (ns)
tPLH
40
30
tPHL
20
10
10
20
30
50
40
TEMPERATURE (°C)
60
60
tPLH
40
30
tPHL
20
tPLH
30
20
70
0
10
20
30
50
40
TEMPERATURE (°C)
MXL1543 toc17
100
90
80
PROPAGATION DELAY (ns)
70
40
V.35 RECEIVER PROPAGATION DELAY
vs. TEMPERATURE
MXL1543 toc16
80
50
0
0
5000
tPHL
60
10
0
V.35 TRANSMITTER PROPAGATION DELAY
vs. TEMPERATURE
50
70
60
50
MXL1543 toc15
70
PROPAGATION DELAY (ns)
-SLEW
80
MXL1543 toc14
80
CLOAD (pF)
70
tPHL
60
50
40
tPLH
30
20
10
10
0
0
0
6
1V/div
200ns/div
+SLEW
0
5V/div
1µs/div
MXL1543 toc13
24
22
20
18
16
14
12
10
8
6
4
2
0
MXL1543 toc12
FULL LOAD
CL = 2500pF
RL = 3kΩ
200ns/div
PROPAGATION DELAY (ns)
SLEW RATE (V/µs)
TIN
V.35 LOOPBACK OPERATION
MXL1543 toc11
10
20
30
50
40
TEMPERATURE (°C)
60
70
0
10
20
30
50
40
TEMPERATURE (°C)
60
_______________________________________________________________________________________
70
60
70
+5V Multiprotocol, 3Tx/3Rx, SoftwareSelectable Clock/Data Transceivers
100pF
D
R
B
B
R
100Ω
A
A
VOD
15pF
VOC
R
100pF
Figure 1. V.11 DC Test Circuit
Figure 2. V.11 AC Test Circuit
50Ω
D
B
125Ω
50Ω
VCM
125Ω
B
VOD
R
A
50Ω
A
50Ω
15pF
Figure 3. V.35 Transmitter/Receiver Test Circuit
D
A
D
VO C L
Figure 4. V.28 Driver Test Circuit
A
R
RL
15pF
Figure 5. V.28 Receiver Test Circuit
_______________________________________________________________________________________
7
MXL1543
Test Circuits
+5V Multiprotocol, 3Tx/3Rx, SoftwareSelectable Clock/Data Transceivers
MXL1543
Timing Diagrams
5V
D
f = 1MHz: tr ≤10ns: tf ≤ 10ns
1.5V
0
1.5V
tPLH
tPHL
V0
90%
10%
50%
B—A
-V0
tr
90%
VDIFF = V(A) - V(B)
50%
1/2 V0
10%
tf
A
V0
B
tSKEW
tSKEW
Figure 6. V.11, V.35 Driver Propagation Delays
V0
B—A
-V0
f = 1MHz: tr ≤10ns: tf ≤ 10ns
0
INPUT
0
tPHL
tPLH
V0H
1.5V
R
OUTPUT
1.5V
V0L
Figure 7. V.11, V.35 Receiver Propagation Delays
3V
1.5V
D
0
1.5V
tPHL
tPLH
V0
3V
3V
0
0
A
-3V
-V0
-3V
tr
tr
Figure 8. V.28 Driver Propagation Delays
VIH
A
VIL
1.7V
1.3V
tPLH
tPHL
V0H
R
V0L
2.4V
0.8V
Figure 9. V.28 Receiver Propagation Delays
8
_______________________________________________________________________________________
+5V Multiprotocol, 3Tx/3Rx, SoftwareSelectable Clock/Data Transceivers
PIN
NAME
1
C1-
Capacitor C1 Negative Terminal. Connect a 1µF ceramic capacitor between C1+ and C1-.
FUNCTION
2
C1+
Capacitor C1 Positive Terminal. Connect a 1µF ceramic capacitor between C1+ and C1-.
3
VDD
Generated Positive Supply. Connect a 4.7µF ceramic capacitor to ground.
4
VCC
+5V Supply Voltage (±5%). Decouple with a 1µF capacitor to ground.
5
T1IN
Transmitter 1 TTL-Compatible Input
6
T2IN
Transmitter 2 TTL-Compatible Input
7
T3IN
Transmitter 3 TTL-Compatible Input
8
R1OUT
Receiver 1 CMOS Output
9
R2OUT
Receiver 2 CMOS Output
10
R3OUT
Receiver 3 CMOS Output
11
M0
Mode-Select Pin with Internal Pullup to VCC
12
M1
Mode-Select Pin with Internal Pullup to VCC
13
M2
Mode-Select Pin with Internal Pullup to VCC
14
DCE/DTE
15
R3INB
Noninverting Receiver Input
16
R3INA
Inverting Receiver Input
17
R2INB
Noninverting Receiver Input
18
R2INA
Inverting Receiver Input
19
T3OUTB/R1INB
Noninverting Transmitter Output/Noninverting Receiver Input
20
T3OUTA/R1INA
Inverting Transmitter Output/Inverting Receiver Input
21
T2OUTB
Noninverting Transmitter Output
22
T2OUTA
Inverting Transmitter Output
23
T1OUTB
Noninverting Transmitter Output
24
T1OUTA
Inverting Transmitter Output
25
GND
Ground
26
VEE
Generated Negative Supply. Connect a 4.7µF ceramic capacitor to ground.
27
C2-
Capacitor C2 Negative Terminal. Connect a 1µF ceramic capacitor between C2+ and C2-.
28
C2+
Capacitor C2 Positive Terminal. Connect a 1µF ceramic capacitor between C2+ and C2-.
DCE/DTE Mode-Select Pin with Internal Pullup to VCC
Detailed Description
The MXL1543 is a three-driver/three-receiver, multiprotocol transceiver that operates from a single +5V supply. The MXL1543, along with the MXL1544/MAX3175
and MXL1344A, form a complete software-selectable
DTE or DCE interface port that supports the V.28 (RS232), V.10/V.11 (RS-449/V.36, EIA-530, EIA-530A,
X.21), and V.35 protocols. The MXL1543 transceivers
carry the high-speed clock and data signals, while the
MXL1544/MAX3175 transceivers carry serial interface
control signaling. The MXL1543 can be terminated by
the MXL1344A software-selectable resistor termination
network or by a discrete termination network. The
MXL1543 features a 0.5µA no-cable mode, true fail-
safe operation, and thermal shutdown circuitry. Thermal
shutdown protects the drivers against excessive power
dissipation. When activated, the thermal shutdown circuitry places the driver outputs into a high-impedance
state.
Mode Selection
The state of the mode-select pins M0, M1, and M2
determines which serial interface protocol is selected
(Table 1). The state of the DCE/DTE input determines
whether the transceiver will be configured as a DTE or
DCE serial port. When the DCE/DTE input is logic
HIGH, driver T3 is activated and receiver R1 is disabled. When the DCE/DTE input is logic LOW, driver T3
_______________________________________________________________________________________
9
MXL1543
Pin Description
MXL1543
+5V Multiprotocol, 3Tx/3Rx, SoftwareSelectable Clock/Data Transceivers
Table 1. Mode Selection
MXL1543
MODE NAME
M2
M1
M0
DCE/
DTE
T1
T2
T3
R1
R2
R3
Not Used (Default V.11)
0
0
0
0
V.11
V.11
Z
V.11
V.11
V.11
RS-530A
0
0
1
0
V.11
V.11
Z
V.11
V.11
V.11
RS-530
0
1
0
0
V.11
V.11
Z
V.11
V.11
V.11
X.21
0
1
1
0
V.11
V.11
Z
V.11
V.11
V.11
V.35
1
0
0
0
V.35
V.35
Z
V.35
V.35
V.35
RS-449/V.36
1
0
1
0
V.11
V.11
Z
V.11
V.11
V.11
V.28
V.28/RS-232
1
1
0
0
V.28
V.28
Z
V.28
V.28
No Cable
1
1
1
0
Z
Z
Z
Z
Z
Z
Not Used (Default V.11)
0
0
0
1
V.11
V.11
V.11
Z
V.11
V.11
RS-530A
0
0
1
1
V.11
V.11
V.11
Z
V.11
V.11
RS-530
0
1
0
1
V.11
V.11
V.11
Z
V.11
V.11
X.21
0
1
1
1
V.11
V.11
V.11
Z
V.11
V.11
V.35
1
0
0
1
V.35
V.35
V.35
Z
V.35
V.35
RS-449/V.36
1
0
1
1
V.11
V.11
V.11
Z
V.11
V.11
V.28/RS-232
1
1
0
1
V.28
V.28
V.28
Z
V.28
V.28
No Cable
1
1
1
1
Z
Z
Z
Z
Z
Z
is disabled and receiver R1 is activated. M0, M1, M2,
and DCE/DTE are internally pulled up to VCC to ensure
a logic HIGH if left unconnected.
No-Cable Mode
The MXL1543 will enter no-cable mode when the
mode-select pins are left unconnected or connected
high (M0 = M1 = M2 = 1). In this mode, the multiprotocol drivers and receivers are disabled and the supply
current drops to 0.5µA. The receivers’ outputs enter a
high-impedance state in no-cable mode, which allow
these output lines to be shared with other receivers’
outputs (the receivers’ outputs have internal pullup
resistors to pull the outputs HIGH if not driven). Also, in
no-cable mode, the transmitter outputs enter a highimpedance state so that these output lines can be
shared with other devices.
Dual Charge-Pump Voltage Converter
The MXL1543’s internal power supply consists of a regulated dual charge pump that provides positive and
negative output voltages from a +5V supply. The
charge pump operates in discontinuous mode. If the
output voltage is less than the regulated voltage, the
charge pump is enabled. If the output voltage exceeds
the regulated voltage, the charge pump is disabled.
10
Each charge pump requires a flying capacitor (C1, C2)
and a reservoir capacitor (C3, C5) to generate the VDD
and VEE supplies. Figure 10 shows charge-pump connections.
Fail-Safe Receivers
The MXL1543 guarantees a logic-high receiver output
when the receiver inputs are shorted or open, or when
they are connected to a terminated transmission line
with all the drivers disabled. This is done by setting the
receivers’ threshold between -25mV and -200mV in the
MXL1543
C3
4.7µF
C1
1µF
5V
C4
1µF
VDD
C2+
C1+
C2-
C1-
VEE
VCC
GND
Figure 10. Charge Pump
______________________________________________________________________________________
C2
1µF
C5
4.7µF
+5V Multiprotocol, 3Tx/3Rx, SoftwareSelectable Clock/Data Transceivers
MXL1543
C6
C7 C8
100pF 100pF 100pF
3
8
VCC
5V
11
12 13
MXL1344A
14
25
C4
1µF
DTE_TXD/DCE_RXD
5
DTE_SCTE/DCE_RXC
6
D2
7
5 4
6 7
9 10 16 15 18 17 19 20 22 23 24 1
VCC
DTE
2
TXD A
14
TXD B
24
SCTE A
11
SCTE B
15
12
17
9
18
17
16
15
R2
10
DTE_RXD/DCE_TXD
C12
1µF
20
19
R1
9
DTE_RXC/DCE_SCTE
VEE
DCE
RXD A
RXD B
RXC A
RXC B
D3
8
DTE_TXC/DCE_TXC
2
C5
4.7µF
24
23
22
21
D1
21
M0
27
26
CHARGE
PUMP
2
4
LATCH
C2
1µF
M1
1
C1
1µF
VCC
DCE/DTE
M2
C3
4.7µF
C13
1µF
28
3
R3
3
16
7
TXC A
TXC B
TXC A
TXC B
RXC A SCTE A
RXC B SCTE B
RXD A TXD A
RXD B TXD B
SG
11
NC
M0 MXL1543
12
M1
13
M2
14
DCE/DTE
1
SHIELD
DB-25
CONNECTOR
C9
1µF
VCC
1
C10
1µF
2
3
DTE_RTS/DCE_CTS
4
DTE_DTR/DCE_DSR
5
6
DTE_DCD/DCE_DCD
7
DTE_DSR/DCE_DTR
8
DTE_CTS/DCE_RTS
10
9
28
VCC
VEE
VDD
GND
D1
D2
27
26
25
24
23
C11
1µF
25
DCE/DTE
21
M1
18
M0
4
RTS A CTS A
19 RTS B CTS B
20
DTR A DSR A
23
DTR B DSR B
D3
R1
R2
R3
R4
22
21
20
19
18
17
8
DCD A
10
DCD B
6
DSR A
22
DSR B
5
CTS A
13 CTS B
DCD A
DCD B
DTR A
DTR B
RTS A
RTS B
16
D4
11
NC
M0 MXL1544
MAX3175
12
M1
13
M2
14
15
DCE/DTE INVERT
Figure 11. Cable-Selectable Multiprotocol DTE/DCE Port
______________________________________________________________________________________
11
MXL1543
+5V Multiprotocol, 3Tx/3Rx, SoftwareSelectable Clock/Data Transceivers
BALANCED
INTERCONNECTING
CABLE
GENERATOR
IZ
CABLE
TERMINATION
A
3.25mA
LOAD
RECEIVER
-10V
-3V
VZ
+10V
A′
+3V
100Ω
MIN
B
B′
C
C′
GND
GND
Figure 13. Receiver Input Impedance
Cable-Selectable Mode
Figure 12. Typical V.11 Interface
V.11 and V.35 modes. If the differential receiver input
voltage (B - A) is ≥ -25mV, R_OUT is logic HIGH. If (B A) is ≤ -200mV, R_OUT is logic LOW. In the case of a
terminated bus with all transmitters disabled, the
receiver’s differential input voltage is pulled to zero by
the termination. With the receiver thresholds of the
MXL1543, this results in a logic HIGH with a 25mV minimum noise margin.
Applications Information
Capacitor Selection
The capacitors used for the charge pumps, as well as
for supply bypassing, should have a low equivalent
series resistance (ESR) and low temperature coefficient. Multilayer ceramic capacitors with an X7R dielectric offer the best combination of performance, size,
and cost. The flying capacitors (C1, C2) and the
bypass capacitor (C4) should have a value of 1µF,
while the reservoir capacitors (C3, C5) should have a
minimum value of 4.7µF (Figure 10). To reduce the ripple present on the transmitter outputs, capacitors C3,
C4, and C5 can be increased. The values of C1 and C2
should not be increased.
Cable Termination
The MXL1344A software-selectable resistor network is
designed to be used with the MXL1543. The MXL1344A
multiprotocol termination network provides V.11- and
V.35-compliant termination, while V.28 receiver termination is internal to the MXL1543. These cable termination
networks provide compatibility with V.11, V.28, and
V.35 protocols. Using the MXL1344A termination networks provide the advantage of not having to build
expensive termination networks out of resistors and
relays, manually changing termination modules, or
building custom termination networks
12
-3.25mA
A cable-selectable multiprotocol interface is shown in
Figure 11. The mode control lines M0, M1, and
DCE/DTE are wired to the DB-25 connector. To select
the serial interface mode, the appropriate combination
of M0, M1, and DCE/DTE are grounded within the cable
wiring. The control lines that are not grounded are
pulled high by the internal pullups on the MXL1543.
The serial interface protocol of the MXL1543,
MXL1544/MAX3175, and MXL1344A is selected based
on the cable that is connected to the DB-25 interface.
V.11 Interface
As shown in Figure 12, the V.11 protocol is a fully balanced differential interface. The V.11 driver generates a
minimum of ±2V between nodes A and B when a 100Ω
(min) resistance is presented at the load. The V.11
receiver is sensitive to ±200mV differential signals at
receiver inputs A’ and B’. The V.11 receiver rejects
common-mode signals developed across the cable
(referenced from C to C’) of up to ±7V, allowing for
error-free reception in noisy environments. The receiver
inputs must comply with the impedance curve shown in
Figure 13.
For high-speed data transmission, the V.11 specification recommends terminating the cable at the receiver
with a 100Ω resistor. This resistor, although not
required, prevents reflections from corrupting transmitted data. In Figure 14, the MXL1344A is used to terminate the V.11 receiver. Internal to the MXL1344A, S1 is
closed and S2 is open to present a 100Ω minimum differential resistance. The MXL1543’s internal V.28 termination is disabled by opening S3.
V.35 Interface
Figure 15 shows a fully-balanced, differential standard
V.35 interface. The generator and the load must both
present a 100Ω ±10Ω differential impedance and a
150Ω ±15Ω common-mode impedance as shown by
the resistive T networks in Figure 15. The V.35 driver
generates a current output (±11mA, typ) that develops
an output voltage of ±550mV across the generator and
______________________________________________________________________________________
+5V Multiprotocol, 3Tx/3Rx, SoftwareSelectable Clock/Data Transceivers
MXL1543
A′
A
MXL1543
R5
30kΩ
R1
52Ω
R8
5kΩ
MXL1344A
RECEIVER
S3
S1
S2
R6
10kΩ
R3
124Ω
R7
10kΩ
R2
52Ω
B′
R4
30kΩ
B
C′
GND
Figure 14. V.11 Termination and Internal Resistance Networks
BALANCED
INTERCONNECTING
CABLE
GENERATOR
LOAD
50Ω
CABLE
TERMINATION
A′
A
125Ω
125Ω
50Ω
RECEIVER
50Ω
50Ω
B
B′
C
C′
GND
GND
Figure 15. Typical V.35 Interface
A′
A
MXL1543
R5
30kΩ
R1
52Ω
R8
5kΩ
MXL1344A
S1
S2
R6
10kΩ
S3
R3
124Ω
R7
10kΩ
R2
52Ω
B′
RECEIVER
R4
30kΩ
B
C′
GND
Figure 16. V.35 Termination and Internal Resistance Networks
______________________________________________________________________________________
13
MXL1543
+5V Multiprotocol, 3Tx/3Rx, SoftwareSelectable Clock/Data Transceivers
UNBALANCED
INTERCONNECTING
CABLE
GENERATOR
LOAD
CABLE
TERMINATION
A
A′
C
C′
GND
RECEIVER
GND
Figure 17. Typical V.28 Interface
A′
A
MXL1543
R5
30kΩ
R1
52Ω
R8
5kΩ
MXL1344A
S1
S2
R6
10kΩ
S3
R3
124Ω
R7
10kΩ
R2
52Ω
B′
RECEIVER
R4
30kΩ
B
C′
GND
Figure 18. V.28 Termination and Internal Resistance Networks
load termination networks. The V.35 receiver is sensitive to ±200mV differential signals at receiver inputs A’
and B’. The V.35 receiver rejects common-mode signals developed across the cable (referenced from C to
C’) of up to ±4V, allowing for error-free reception in
noisy environments.
In Figure 16, the MXL1344A is used to implement the
resistive T network that is needed to properly terminate
the V.35 driver and receiver. Internal to the MXL1344A,
S1 and S2 are closed to connect the T-network resistors to the circuit. The V.28 termination resistor (internal
to the MXL1543) is disabled by opening S3 to avoid
interference with the T-network impedance.
in rejecting system noise, the MXL1543’s V.28 receiver
has a typical hysteresis of 0.05V.
Figure 18 shows the MXL1344A’s termination network
disabled by opening S1 and S2. The MXL1543’s internal 5kΩ V.28 termination is enabled by closing S3.
DTE vs. DCE Operation
V.28 Interface
Figure 19 shows a DCE or DTE controller-selectable
interface. DCE/DTE (pin 14) switches the port’s mode
of operation. See Table 1.
This application requires only one DB-25 connector,
but separate cables for DCE or DTE signal routing. See
Figure 19 for complete signal routing in DCE and DTE
modes.
The V.28 interface is an unbalanced single-ended interface (Figure 17). The V.28 driver generates a minimum
of ±5V across a 3kΩ load impedance between A’ and
C’. The V.28 receiver has a single-ended input. To aid
A complete DTE-to-DCE interface operating in X.21
mode is shown in Figure 20. The MXL1543 is used to
generate the clock and data signals, and the
14
Complete Multiprotocol X.21 Interface
______________________________________________________________________________________
+5V Multiprotocol, 3Tx/3Rx, SoftwareSelectable Clock/Data Transceivers
MXL1543
C6
C7 C8
100pF 100pF 100pF
3
8
VCC
5V
11
12 13
MXL1344A
14
27
26
CHARGE
PUMP
2
4
25
C4
1µF
DTE_TXD/DCE_RXD
5
DTE_SCTE/DCE_RXC
6
D2
7
5 4
6 7
9 10 16 15 18 17 19 20 22 23 24 1
DTE
2
TXD A
14
TXD B
24
SCTE A
11
SCTE B
15
12
17
9
18
17
16
15
R2
10
DTE_RXD/DCE_TXD
VEE
C12
1µF
20
19
R1
9
DTE_RXC/DCE_SCTE
21
DCE
RXD A
RXD B
RXC A
RXC B
D3
8
DTE_TXC/DCE_TXC
2
C5
4.7µF
24
23
22
21
D1
LATCH
C2
1µF
M0
1
C1
1µF
VCC
DCE/DTE
M2
M1
C3
4.7µF
C13
1µF
28
3
R3
3
16
7
TXC A
TXC B
TXC A
TXC B
RXC A SCTE A
RXC B SCTE B
RXD A TXD A
RXD B TXD B
SG
11
M0 MXL1543
12
M1
13
M2
14
DCE/DTE
1
SHIELD
DB-25
CONNECTOR
C9
1µF
VCC
C10
1µF
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
1
2
3
4
5
DTE_DCD/DCE_DCD
DTE_DSR/DCE_DTR
DTE_CTS/DCE_RTS
DTE_LL/DCE_LL
6
7
8
10
9
28
VCC
VEE
VDD
GND
D1
D2
27
C11
1µF
26
25
24
23
4
RTS A
19 RTS B
20
DTR A
23
DTR B
22
21
20
19
18
17
8
DCD A
10
DCD B
6
DSR A
22
DSR B
5
CTS A
13 CTS B
16
18
CTS A
CTS B
DSR A
DSR B
D3
R1
R2
R3
R4
LLA
DCD A
DCD B
DTR A
DTR B
RTS A
RTS B
LLA
D4
MXL1544
M0 MAX3175
12
15
M1
INVERT
13
M2
14
DCE/DTE
11
DCE/DTE
M2
M1
M0
Figure 19. Multiprotocol DCE/DTE Port
______________________________________________________________________________________
15
MXL1543
+5V Multiprotocol, 3Tx/3Rx, SoftwareSelectable Clock/Data Transceivers
DTE
SERIAL
CONTROLLER
MXL1543
DCE
MXL1344A
MXL1344A
TXD
D1
TXD
SCTE
D2
SCTE
D3
TXC
R3
RXC
R2
RXD
R1
104Ω
104Ω
MXL1543
SERIAL
CONTROLLER
R3
TXD
R2
SCTE
R1
104Ω
104Ω
104Ω
TXC
D1
TXC
RXC
D2
RXC
RXD
D3
RXD
MXL1544
MAX3175
MXL1544
MAX3175
RTS
D1
RTS
R3
RTS
DTR
D2
DTR
R2
DTR
D3
R1
DCD
R1
DCD
D3
DCD
DSR
R2
DSR
D2
DSR
CTS
R3
CTS
D1
CTS
LL
D4
R4
LL
R4
LL
D4
Figure 20. DCE-to-DTE X.21 Interface
MXL1544/MAX3175 generate the control signals and
local loopback (LL). The MXL1344A is used to terminate the clock and data signals to support the V.11 protocol for cable termination. The control signals do not
need external termination.
16
Compliance Testing
A European Standard EN 45001 test report is pending
for the MXL1543/MXL1544/MXL1344A chipset. A copy
of the test report will be available from Maxim upon
completion.
______________________________________________________________________________________
+5V Multiprotocol, 3Tx/3Rx, SoftwareSelectable Clock/Data Transceivers
Pin Configuration
TOP VIEW
C1- 1
28 C2+
C1+ 2
27 C2-
VDD 3
26 VEE
VCC 4
25 GND
T1IN 5
T2IN 6
24 T1OUTA
MXL1543
23 T1OUTB
T3IN 7
22 T2OUTA
R1OUT 8
21 T2OUTB
R2OUT 9
20 T3OUTA/R1INA
R3OUT 10
19 T3OUTB/R1INB
M0 11
18 R2INA
M1 12
17 R2INB
M2 13
16 R3INA
DCE/DTE 14
15 R3INB
SSOP
______________________________________________________________________________________
17
MXL1543
Chip Information
TRANSISTOR COUNT: 2619
PROCESS: BiCMOS
+5V Multiprotocol, 3Tx/3Rx, SoftwareSelectable Clock/Data Transceivers
SSOP.EPS
MXL1543
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.