SCES613A – OCTOBER 2004 − REVISED DECEMBER 2004 D Available in the Texas Instruments D D D D D D Very Low Static and Dynamic Power NanoStar and NanoFree Packages Single-Supply Voltage Translator − 1.8 V to 3.3 V (at VCC = 3.3 V) − 2.5 V to 3.3 V (at VCC = 3.3 V) − 1.8 V to 2.5 V (at VCC = 2.5 V) − 3.3 V to 2.5 V (at VCC = 2.5 V) Nine Configurable Gate Logic Functions Schmitt-Trigger Inputs Reject Input Noise and Provide Better Output Signal Integrity Ioff Supports Partial-Power-Down Mode With Low Leakage Current (0.5 mA) 200-ns/V Input Rise/Fall Time Allows Slow Transition of Input Signal DBV OR DCK PACKAGE (TOP VIEW) B GND A 1 6 2 5 3 4 C VCC Y D D D D Consumption Pb-Free Packages Available: SOT-23 (DBV), SC-70 (DCK), WCSP (NanoFree) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) Related Devices: AUP1T98/57/58 YEP OR YZP PACKAGE (BOTTOM VIEW) A GND B 3 4 2 5 1 6 Y VCC C description /ordering information AUP technology is the industry’s lowest-power logic technology designed for use in battery-operated or battery backed-up equipment. The SN74AUP1T97 is designed for logic level translation applications with input switching levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply. The wide VCC range of 2.3 V to 3.6 V allows the possibility of battery voltage drop during system operation and ensures normal operation between this range. Schmitt-trigger inputs ( nVT = 210 mV between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog-mixed mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and also allow for slow input signal transition. The AUP1T97 can be easily configured to perform a required gate function by connecting A, B, and C inputs to VCC or ground (see Function Selection Table). Up to nine commonly used logic gate functions can be performed. Ioff is a feature that allows for powered-down conditions (VCC = 0 V) and is important in portable and mobile applications. When VCC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of the device. No damage will occur to the device under these conditions. AUP1T97 is designed with optimized current drive capability of 4 mA to reduce line reflections, overshoot, and undershoot caused by high drive outputs. Nanostar and Nanofree package technology is a major breakthrough in IC packaging concepts, using the die as the package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments. Copyright 2004, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCES613A – OCTOBER 2004 − REVISED DECEMBER 2004 description/ordering information (continued) ORDERING INFORMATION −40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA TOP-SIDE MARKING‡ NanoStar − WCSP (DSBGA) 0.23-mm Large Bump − YEP Tape and reel SN74AUP1T97YEPR NanoFree − WCSP (DSBGA) 0.23-mm Large Bump − YZP (Pb-free) Tape and reel SN74AUP1T97YZPR SOT (SOT-23) − DBV Tape and reel SN74AUP1T97DBVR HT4_ SOT (SC-70) − DCK Tape and reel SN74AUP1T97DCKR TH_ _ _ _TH_ † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION SELECTION TABLE LOGIC FUNCTION 2 FIGURE NO. 2-to-1 data selector 5 2-input AND gate 6 2-input OR gate with one inverted input 7 2-input NAND gate with one inverted input 7 2-input AND gate with one inverted input 8 2-input NOR gate with one inverted input 8 2-input OR gate 9 Inverter 10 Noninverted buffer 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCES613A – OCTOBER 2004 − REVISED DECEMBER 2004 Dynamic-Power Consumption (pF) 100% 100% 80% 80% 60% 60% 3.3-V Logic† 40% 40% 3 2.5 3.3-V LVC Logic† AUP 0% 0% 2 Input Output 1.5 1 0.5 0 20% 20% Switching Characteristics at 25 MHz† 3.5 Voltage − V Static-Power Consumption (µA) −0.5 AUP † Single, dual, and triple gates 0 5 10 15 20 25 30 Time − ns 35 40 45 † AUP1G08 data at CL = 15 pF Figure 1. AUP - The Lowest-Power Family Figure 2. Excellent Signal Integrity 3.3 V 3.3 V VIH = 1.19 V VIL = 0.5 V VIH = 1.19 V VIL = 0.5 V 1.8-V System 2.5-V System 3.3-V System 3.3-V System AUP1T97 AUP1T97 2.5 V 2.5 V VIH = 1.10 V VIL = 0.35 V VIH = 1.10 V VIL = 0.35 V 1.8-V System 3.3-V System 2.5-V System AUP1T97 2.5-V System AUP1T97 Figure 3. Possible Voltage Translation Combinations 3.3 V 1.8-V System 3.3-V System AUP1T97 VOH min VT+(max) = VIH(min) = 1.19 V VT−(min) = VIL(max) = 0.5 V VOL max Input Switching Waveform Output Switching Waveform Figure 4. Switching Thresholds for 1.8-V to 3.3-V Translation POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCES613A – OCTOBER 2004 − REVISED DECEMBER 2004 FUNCTION TABLE INPUTS A OUTPUT Y L L L L H L C B L L L H L H L H H H H L L L H L H H H H L L H H H H logic diagram (positive logic) A 3 4 B C 4 1 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Y SCES613A – OCTOBER 2004 − REVISED DECEMBER 2004 logic configurations VCC VCC C B B Y A A 1 6 2 5 3 4 C C Y A A Y GND 1 6 2 5 3 4 C Y GND Figure 5. 157: 2-to-1 Data Selector/MUX When C is L, Y = B When C is H, Y = A Figure 6. 08: 2-Input AND Gate VCC C VCC C Y C Y B A Y A A 1 6 2 5 3 4 C B C Y Y B 1 6 2 5 3 4 C Y GND GND Figure 7. 14+32/14+00: 2-Input OR/NAND Gate With One Inverted Input Figure 8. 14+08/14+02: 2-Input AND/NOR Gate With One Inverted Input VCC VCC C Y B B 1 6 2 5 3 4 C C Y Y 1 6 2 5 3 4 C Y GND GND Figure 9. 32: 2-Input OR Gate Figure 10. 04/14: Inverter VCC B B Y 1 6 2 5 3 4 Y GND Figure 11. 17/34: Noninverted Buffer POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCES613A – OCTOBER 2004 − REVISED DECEMBER 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Output voltage range in the high or low state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259°C/W YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) MIN VCC VI Supply voltage VO Output voltage Input voltage IOH High-level output current VCC = 2.3 V VCC = 3 V IOL Low-level output current VCC = 2.3 V VCC = 3 V ∆t/∆v MAX UNIT 2.3 3.6 V 0 3.6 V 0 VCC −3.1 V −4 mA 3.1 4 mA Input transition rise or fall rate VCC = 2.3 V to 3.6 V 200 ns/V TA Operating free-air temperature −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCES613A – OCTOBER 2004 − REVISED DECEMBER 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = −40°C TO 85°C TA = 25°C VCC MIN TYP UNIT MAX MIN MAX VT+ Positive-going input threshold voltage 2.3 V to 2.7 V 0.6 1.1 0.6 1.1 3 V to 3.6 V 0.75 1.16 0.75 1.19 VT− Negative-going input threshold voltage 2.3 V to 2.7 V 0.35 0.6 0.35 0.6 3 V to 3.6 V 0.5 0.85 0.5 0.85 ∆VT Hysteresis (VT+ − VT−) 2.3 V to 2.7 V 0.23 0.6 0.17 0.6 3 V to 3.6 V 0.25 0.56 0.21 0.56 2.3 V to 3.6 V VCC − 0.1 2.05 V V V IOH = −20 µA IOH = −2.3 mA 2.3 V IOH = −3.1 mA IOH = −2.7 mA VOH 3V IOH = −4 mA IOL = 20 µA All inputs ∆Ioff ICC ∆ICC 1.85 2.67 2.6 2.55 2.3 V IOL = 2.7 mA IOL = 4 mA II Ioff 1.9 2.72 2.3 V to 3.6 V IOL = 2.3 mA IOL = 3.1 mA VOL VCC − 0.1 1.97 3V V 0.1 0.1 0.31 0.33 0.44 0.45 0.31 0.33 0.44 0.45 V VI = 3.6 V or GND VI or VO = 0 V to 3.6 V 0 V to 3.6 V 0.1 0.5 µA 0V 0.1 0.5 µA VI or VO = 5.5 V VI = 3.6 V or GND, IO = 0 0 V to 0.2 V 0.2 0.5 µA 2.3 V to 3.6 V 0.5 0.9 µA One input at 0.3 V or 1.1 V, Other inputs at 0 or VCC, IO = 0 2.3 V to 2.7 V 4 One input at 0.45 V or 1.2 V, Other inputs at 0 or VCC, IO = 0 3 V to 3.6 V 12 µA Ci VI = VCC or GND 3.3 V 1.5 pF Co VO = VCC or GND 3.3 V 3 pF switching characteristics over recommended operating free-air temperature VCC = 2.5 V + 0.2 V, VI = 1.8 V + 0.15 V (unless otherwise noted) (see Figure 12) PARAMETER tpd FROM (INPUT) A, B, or C TO (OUTPUT) Y POST OFFICE BOX 655303 TA = −40°C TO 85°C TA = 25°C CL MIN TYP MAX MIN MAX 5 pF 1.8 2.3 2.9 0.5 6.8 10 pF 2.3 2.8 3.4 1 7.9 15 pF 2.6 3.1 3.8 1 8.7 30 pF 3.8 4.4 5.1 1.5 10.8 • DALLAS, TEXAS 75265 range, UNIT ns 7 SCES613A – OCTOBER 2004 − REVISED DECEMBER 2004 switching characteristics over recommended operating free-air temperature VCC = 2.5 V + 0.2 V, VI = 2.5 V + 0.2 V (unless otherwise noted) (see Figure 12) PARAMETER tpd FROM (INPUT) A, B, or C TO (OUTPUT) Y TA = −40°C TO 85°C TA = 25°C CL range, UNIT MIN TYP MAX MIN MAX 5 pF 1.8 2.3 3.1 0.5 6 10 pF 2.2 2.8 3.5 1 7.1 15 pF 2.6 3.2 5.2 1 7.9 30 pF 3.7 4.4 5.2 1.5 10 switching characteristics over recommended operating free-air temperature VCC = 2.5 V + 0.2 V, VI = 3.3 V + 0.3 V (unless otherwise noted) (see Figure 12) PARAMETER tpd FROM (INPUT) A, B, or C TO (OUTPUT) Y range, TA = −40°C TO 85°C TA = 25°C CL UNIT MIN TYP MAX MIN MAX 5 pF 2 2.7 3.5 0.5 5.5 10 pF 2.4 3.1 3.9 1 6.5 15 pF 2.8 3.5 4.3 1 7.4 30 pF 4 4.7 5.5 1.5 9.5 switching characteristics over recommended operating free-air temperature VCC = 3.3 V + 0.3 V, VI = 1.8 V + 0.15 V (unless otherwise noted) (see Figure 12) PARAMETER tpd FROM (INPUT) A, B, or C TO (OUTPUT) Y MIN TYP MAX MIN UNIT MAX 5 pF 1.6 2 2.5 0.5 8 10 pF 2 2.4 2.9 1 8.5 15 pF 2.3 2.8 3.3 1 9.1 30 pF 3.4 3.9 4.4 1.5 9.8 switching characteristics over recommended operating free-air temperature VCC = 3.3 V + 0.3 V, VI = 2.5 V + 0.2 V (unless otherwise noted) (see Figure 12) PARAMETER tpd 8 FROM (INPUT) A, B, or C TO (OUTPUT) Y POST OFFICE BOX 655303 TA = −40°C TO 85°C TA = 25°C CL MIN TYP MAX MIN MAX 5 pF 1.6 1.9 2.4 0.5 5.3 10 pF 2 2.3 2.7 1 6.1 15 pF 2.3 2.7 3.1 1 6.8 30 pF 3.4 3.8 4.2 1.5 8.5 • DALLAS, TEXAS 75265 ns range, TA = −40°C TO 85°C TA = 25°C CL ns ns range, UNIT ns SCES613A – OCTOBER 2004 − REVISED DECEMBER 2004 switching characteristics over recommended operating free-air temperature VCC = 3.3 V + 0.3 V, VI = 3.3 V + 0.3 V (unless otherwise noted) (see Figure 12) PARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP MAX MIN MAX 1.6 2.1 2.7 0.5 4.7 10 pF 2 2.4 3 1 5.7 15 pF 2.3 2.7 3.3 1 6.2 30 pF 3.4 3.8 4.4 1.5 7.8 5 pF tpd A, B, or C Y TA = −40°C TO 85°C TA = 25°C CL range, UNIT ns operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance f = 10 MHz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCC = 2.5 V TYP 4 VCC = 3.3 V TYP 5 UNIT pF 9 SCES613A – OCTOBER 2004 − REVISED DECEMBER 2004 PARAMETER MEASUREMENT INFORMATION From Output Under Test CL (see Note A) VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V 5, 10, 15, 30 pF VI/2 VCC/2 5, 10, 15, 30 pF VI/2 VCC/2 1 MΩ CL VMI VMO LOAD CIRCUIT VI VMI Input VMI 0V tPHL tPLH VOH VMO Output VMo VOL tPHL tPLH VOH Output VMo VMo VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS NOTES: A. B. C. D. CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. The outputs are measured one at a time, with one transition per measurement. tPLH and tPHL are the same as tpd. Figure 12. Load Circuit and Voltage Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDS114 – FEBRUARY 2002 DCK (R-PDSO-G6) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 6 0,10 M 4 1,40 1,10 1 0,13 NOM 2,40 1,80 3 Gage Plane 2,15 1,85 0,15 0°–8° 0,46 0,26 Seating Plane 1,10 0,80 0,10 0,00 0,10 4093553-3/D 01/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. 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