TI SN74AVC2T45DCTR

SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F – DECEMBER 2003 – REVISED MAY 2005
FEATURES
•
•
•
•
•
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
Control Inputs VIH/VIL Levels Are Referenced
to VCCA Voltage
Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.2-V to
3.6-V Power-Supply Range
I/Os Are 4.6-V Tolerant
Ioff Supports Partial-Power-Down Mode
Operation
BBBB
BBBB
•
–
–
–
–
–
•
Max Data Rates
500 Mbps (1.8-V to 3.3-V Translation)
320 Mbps (<1.8-V to 3.3-V Translation)
320 Mbps (Translate to 2.5 V or 1.8 V)
180 Mbps (Translate to 1.5 V)
240 Mbps (Translate to 1.2 V)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
BBBB
DCT OR DCU PACKAGE
(TOP VIEW)
VCCA
A1
A2
GND
1
8
2
7
3
6
4
5
YEP OR YZP PACKAGE
(BOTTOM VIEW)
VCCB
B1
B2
DIR
GND
A2
A1
VCCA
4 5
3 6
2 7
1 8
DIR
B2
B1
VCCB
DESCRIPTION/ORDERING INFORMATION
This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is
designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track
VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional
translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVC2T45 is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input.
The SN74AVC2T45 is designed so that the DIR input is powered by VCCA.
ORDERING INFORMATION
PACKAGE (1)
TA
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
–40°C to 85°C
(1)
(2)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
ORDERABLE PART NUMBER
TOP-SIDE MARKING (2)
SN74AVC2T45YEPR
Tape and reel
_ _ _TD_
SN74AVC2T45YZPR
SSOP – DCT
Tape and reel
SN74AVC2T45DCTR
DT2_ _ _
VSSOP – DCU
Tape and reel
SN74AVC2T45DCUR
DT2_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, ⋅ = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F – DECEMBER 2003 – REVISED MAY 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
FUNCTION TABLE
(EACH TRANSCEIVER)
INPUT
OPERATION
DIR
L
B data to A bus
H
A data to B bus
LOGIC DIAGRAM (POSITIVE LOGIC)
DIR
A1
5
2
7
A2
3
6
VCCA
2
B1
VCCB
B2
www.ti.com
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES531F – DECEMBER 2003 – REVISED MAY 2005
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
VCCA
VCCB
Supply voltage range
VI
Input voltage range (2)
MIN
MAX
–0.5
4.6
I/O ports (A port)
–0.5
4.6
I/O ports (B port)
–0.5
4.6
Control inputs
–0.5
4.6
A port
–0.5
4.6
B port
–0.5
4.6
A port
–0.5
VCCA + 0.5
B port
–0.5
VCCB + 0.5
UNIT
V
V
VO
Voltage range applied to any output in the high-impedance or
power-off state (2)
VO
Voltage range applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCCA, VCCB, or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
DCT package
220
DCU package
227
YEP/YZP package
(1)
(2)
(3)
(4)
V
V
°C/W
102
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
3
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F – DECEMBER 2003 – REVISED MAY 2005
Recommended Operating Conditions (1) (2) (3) (4) (5)
VCCI
VCCO
MIN
MAX
UNIT
VCCA
Supply voltage
1.2
3.6
V
VCCB
Supply voltage
1.2
3.6
V
High-level
input voltage
VIH
Low-level
input voltage
VIL
High-level
input voltage
VIH
VIL
Low-level
input voltage
VI
Input voltage
VO
Output voltage
IOH
Data inputs (4)
Data
inputs (4)
DIR
(referenced to VCCA) (5)
DIR
(referenced to VCCA) (5)
2
V
1.2 V to 1.95 V
VCCI × 0.35
1.95 V to 2.7 V
0.7
2.7 V to 3.6 V
0.8
1.2 V to 1.95 V
VCCA × 0.65
1.95 V to 2.7 V
1.6
2.7 V to 3.6 V
2
1.2 V to 1.95 V
VCCA × 0.35
1.95 V to 2.7 V
0.7
2.7 V to 3.6 V
3-state
0
3.6
Operating free-air temperature
V
0.8
3.6
Low-level output current
V
V
VCCO
TA
4
1.6
2.7 V to 3.6 V
0
Input transition rise or fall rate
(4)
(5)
1.95 V to 2.7 V
Active state
∆t/∆v
(1)
(2)
(3)
VCCI × 0.65
0
High-level output current
IOL
1.2 V to 1.95 V
1.2 V
–3
1.4 V to 1.6 V
–6
1.65 V to 1.95 V
–8
2.3 V to 2.7 V
–9
3 V to 3.6 V
–12
1.2 V
3
1.4 V to 1.6 V
6
1.65 V to 1.95 V
8
2.3 V to 2.7 V
9
3 V to 3.6 V
12
–40
V
V
mA
mA
5
ns/V
85
°C
VCCI is the VCC associated with the data input port.
VCCO is the VCC associated with the output port.
All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
For VCCI values not specified in the data sheet, VIH(min) = VCCI x 0.7 V, VIL(max) = VCCI x 0.3 V.
For VCCI values not specified in the data sheet, VIH(min) = VCCA x 0.7 V, VIL(max) = VCCA x 0.3 V.
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F – DECEMBER 2003 – REVISED MAY 2005
Electrical Characteristics
(1) (2)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOL
1.2 V to 3.6 V
1.2 V to 3.6 V
IOH = –3 mA
1.2 V
1.2 V
IOH = –6 mA
1.4 V
1.4 V
1.05
IOH = –8 mA
1.65 V
1.65 V
1.2
IOH = –9 mA
2.3 V
2.3 V
1.75
IOH = –12 mA
3V
3V
2.3
IOL = 100 µA
1.2 V to 3.6 V
1.2 V to 3.6 V
IOL = 3 mA
1.2 V
1.2 V
IOL = 6 mA
1.4 V
1.4 V
0.35
1.65 V
1.65 V
0.45
IOL = 9 mA
2.3 V
2.3 V
0.55
IOL = 12 mA
3V
3V
0.7
II
1.2 V to 3.6 V
1.2 V to 3.6 V
Ioff
IOZ
IOL = 8 mA
DIR
input
A port
B port
A or B
ports
ICCA + ICCB
VI = VIL
VI or VO = 0 to 3.6 V
VO = VCCO or GND
VI = VCCI or
GND,
ICCB
VI = VIH
VI = VCCA or GND
VI = VCCI or
GND,
ICCA
–40°C to 85°C
VCCB
IOH = –100 µA
VOH
TA = 25°C
VCCA
VI = VCCI or
GND,
TYP
MAX
MIN
MAX
0.95
V
0.2
0.25
±0.025
±0.25
±1
0V
0 to 3.6 V
±0.1
±1
±5
0V
±0.1
±1
±5
1.2 V to 3.6 V
1.2 V to 3.6 V
±0.5
±2.5
±5
1.2 V to 3.6 V
1.2 V to 3.6 V
10
0V
3.6 V
–2
3.6 V
0V
10
1.2 V to 3.6 V
1.2 V to 3.6 V
10
0V
3.6 V
10
3.6 V
0V
–2
1.2 V to 3.6 V
1.2 V to 3.6 V
20
IO = 0
UNIT
VCCO
– 0.2 V
0 to 3.6 V
IO = 0
IO = 0
MIN
V
µA
µA
µA
µA
µA
µA
Ci
Control
inputs
VI = 3.3 V or GND
3.3 V
3.3 V
2.5
pF
Cio
A or B
ports
VO = 3.3 V or GND
3.3 V
3.3 V
6
pF
(1)
(2)
VCCO is the VCC associated with the output port.
VCCI is the VCC associated with the input port.
5
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F – DECEMBER 2003 – REVISED MAY 2005
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 1.2 V (see Figure 11)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH (1)
tPZL (1)
tPZH (1)
tPZL
(1)
(1)
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
TYP
TYP
TYP
TYP
TYP
3.1
2.6
2.4
2.2
2.2
3.1
2.6
2.4
2.2
2.2
3.4
3.1
3
2.9
2.9
3.4
3.1
3
2.9
2.9
5.2
5.2
5.1
5
4.8
5.2
5.2
5.1
5
4.8
5
4
3.8
2.8
3.2
5
4
3.8
2.8
3.2
8.4
7.1
6.8
5.7
6.1
8.4
7.1
6.8
5.7
6.1
8.3
7.8
7.5
7.2
7
8.3
7.8
7.5
7.2
7
UNIT
ns
ns
ns
ns
ns
ns
The enable time is a calculated value, derived using the formula shown in the enable times section.
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (see Figure 11)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH (1)
tPZL (1)
tPZH (1)
tPZL
(1)
6
(1)
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.8
0.7
5.4
0.5
4.6
0.4
3.7
0.3
3.5
2.8
0.7
5.4
0.5
4.6
0.4
3.7
0.3
3.5
2.7
0.8
5.4
0.7
5.2
0.6
4.9
0.5
4.7
2.7
0.8
5.4
0.7
5.2
0.6
4.9
0.5
4.7
3.9
1.3
8.5
1.3
7.8
1.1
7.7
1.4
7.6
3.9
1.3
8.5
1.3
7.8
1.1
7.7
1.4
7.6
4.7
1.1
7
1.4
6.9
1.2
6.9
1.7
7.1
4.7
1.1
7
1.4
6.9
1.2
6.9
1.7
7.1
7.4
12.4
12.1
11.8
11.8
7.4
12.4
12.1
11.8
11.8
6.7
13.9
11.6
9.1
7.8
6.7
13.9
11.6
9.1
7.8
The enable time is a calculated value, derived using the formula shown in the enable times section.
UNIT
ns
ns
ns
ns
ns
ns
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F – DECEMBER 2003 – REVISED MAY 2005
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (see Figure 11)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH (1)
tPZL (1)
tPZH (1)
tPZL (1)
(1)
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.7
0.5
5.2
0.4
4.3
0.2
3.4
0.2
3.1
2.7
0.5
5.2
0.4
4.3
0.2
3.4
0.2
3.1
2.4
0.7
4.7
0.5
4.4
0.5
4
0.4
3.8
2.4
0.7
4.7
0.5
4.4
0.5
4
0.4
3.8
3.7
1.3
8.1
0.7
6.9
1.4
5.3
1.1
4.5
3.7
1.3
8.1
0.7
6.9
1.4
5.3
1.1
4.5
4.4
1.3
5.8
1.3
5.9
0.8
5.7
1.5
5.9
4.4
1.3
5.8
1.3
5.9
0.8
5.7
1.5
5.9
6.8
10.4
10.3
9.7
9.7
6.8
10.4
10.3
9.7
9.7
6.4
13.3
11.2
8.6
7.4
6.4
13.3
11.2
8.6
7.4
UNIT
ns
ns
ns
ns
ns
ns
The enable time is a calculated value, derived using the formula shown in the enable times section.
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (see Figure 11)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH (1)
tPZL (1)
tPZH (1)
tPZL
(1)
(1)
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.6
0.4
4.9
0.2
4
0.2
3
0.2
2.6
2.6
0.4
4.9
0.2
4
0.2
3
0.2
2.6
2.1
0.6
3.8
0.5
3.4
0.4
3
0.3
2.8
2.1
0.6
3.8
0.5
3.4
0.4
3
0.3
2.8
2.4
0.7
7.9
0.8
6.4
0.8
5
0.5
4.3
2.4
0.7
7.9
0.8
6.4
0.8
5
0.5
4.3
3.8
1
4.3
0.6
4.3
0.5
4.2
1.1
4.1
3.8
1
4.3
0.6
4.3
0.5
4.2
1.1
4.1
5.9
7.9
7.7
7.2
6.9
5.9
7.9
7.7
7.2
6.9
5
12.8
10.4
7.9
6.8
5
12.8
10.4
7.9
6.8
UNIT
ns
ns
ns
ns
ns
ns
The enable time is a calculated value, derived using the formula shown in the enable times section.
7
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F – DECEMBER 2003 – REVISED MAY 2005
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (see Figure 11)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH (1)
tPZL (1)
tPZH (1)
tPZL (1)
(1)
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.5
0.3
4.7
0.2
3.8
0.2
2.8
0.2
2.4
2.5
0.3
4.7
0.2
3.8
0.2
2.8
0.2
2.4
2.1
0.6
3.6
0.4
3.1
0.3
2.6
0.3
2.4
2.1
0.6
3.6
0.4
3.1
0.3
2.6
0.3
2.4
2.9
1.1
8
1
6.5
1.3
4.7
1.2
4
2.9
1.1
8
1
6.5
1.3
4.7
1.2
4
3.4
0.5
6.6
0.3
5.6
0.3
4.6
1.1
3.5
3.4
0.5
6.6
0.3
5.6
0.3
4.6
1.1
3.5
5.5
6.9
6.6
6.2
5.9
5.5
6.9
6.6
6.2
5.9
5.4
12.7
10.3
7.4
6.3
5.4
12.7
10.3
7.4
6.3
UNIT
ns
ns
ns
ns
ns
ns
The enable time is a calculated value, derived using the formula shown in the enable times section.
Operating Characteristics
TA = 25°C
PARAMETER
CpdA (1)
CpdB (1)
(1)
8
A-port input,
B-port output
B-port input,
A-port output
A-port input,
B-port output
B-port input,
A-port output
TEST
CONDITIONS
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
Power-dissipation capacitance per transceiver
VCCA =
VCCB = 1.2 V
VCCA =
VCCB = 1.5 V
VCCA =
VCCB = 1.8 V
VCCA =
VCCB = 2.5 V
VCCA =
VCCB = 3.3 V
TYP
TYP
TYP
TYP
TYP
3
3
3
3
4
12
13
13
14
15
12
13
13
14
15
3
3
3
3
4
UNIT
pF
pF
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F – DECEMBER 2003 – REVISED MAY 2005
Power-Up Considerations
A proper power-up sequence always should be followed to avoid excessive supply current, bus contention,
oscillations, or other anomalies. To guard against such power-up problems, take the following precautions:
1. Connect ground before any supply voltage is applied.
2. Power up VCCA.
3. VCCB can be ramped up along with or after VCCA.
Table 1. Typical Total Static Power Consumption (ICCA + ICCB)
VCCB
VCCA
0V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0V
0
<0.5
<0.5
<0.5
<0.5
<0.5
1.2 V
<0.5
<1
<1
<1
<1
1
1.5 V
<0.5
<1
<1
<1
<1
1
1.8 V
<0.5
<1
<1
<1
<1
<1
2.5 V
<0.5
1
<1
<1
<1
<1
3.3 V
<0.5
1
<1
<1
<1
<1
UNIT
µA
9
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F – DECEMBER 2003 – REVISED MAY 2005
TYPICAL CHARACTERISTICS
6
6
5
5
4
4
tPHL - ns
tPLH - ns
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE, TA = 25°C, VCCA = 1.2 V
3
2
3
2
VCCB = 1.2 V
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.5 V
VCCB = 1.8 V
1
VCCB = 1.8 V
1
VCCB = 2.5 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 3.3 V
0
0
10
20
30
40
50
60
0
60 0
10
20
CL - pF
Figure 1.
30
CL - pF
40
50
60
Figure 2.
6
6
5
5
4
4
tPHL - ns
tPLH - ns
CL - pF
- 1.5 = 1.5 V
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE, TA = 25°C,
VCCA
3
2
3
2
VCCB = 1.2 V
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.5 V
VCCB = 1.8 V
1
VCCB = 1.8 V
1
VCCB = 2.5 V
VCCB = 2.5 V
VCCB = 3.3 V
0
0
10
20
30
CL - pF
Figure 3.
40
50
VCCB = 3.3 V
60
0
60 0
10
20
30
CL - pF
40
Figure 4.
CL - pF - 1.5
10
50
60
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F – DECEMBER 2003 – REVISED MAY 2005
TYPICAL CHARACTERISTICS
6
6
5
5
4
4
tPHL - ns
tPLH - ns
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE, TA = 25°C, VCCA = 1.8 V
3
2
3
2
VCCB = 1.2 V
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.5 V
VCCB = 1.8 V
1
VCCB = 1.8 V
1
VCCB = 2.5 V
VCCB = 2.5 V
VCCB = 3.3 V
0
0
10
20
30
40
50
VCCB = 3.3 V
60
0
60 0
10
20
CL - pF
Figure 5.
30
CL - pF
40
50
60
Figure 6.
CL - pF
- 1.5 = 2.5 V
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE, TA = 25°C,
VCCA
6
6
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.8 V
5
5
VCCB = 3.3 V
VCCB = 3.3 V
4
4
tPHL - ns
tPLH - ns
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 2.5 V
3
3
2
2
1
1
0
VCCB = 1.2 V
VCCB = 1.5 V
0
10
20
30
CL - pF
Figure 7.
40
50
60
0
60 0
10
20
30
CL - pF
40
50
60
Figure 8.
CL - pF - 1.5
11
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F – DECEMBER 2003 – REVISED MAY 2005
TYPICAL CHARACTERISTICS
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE, TA = 25°C, VCCA = 3.3 V
6
6
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.8 V
5
5
VCCB = 2.5 V
VCCB = 3.3 V
4
4
tPHL - ns
tPLH - ns
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
3
3
2
2
1
1
0
VCCB = 1.2 V
VCCB = 1.5 V
0
10
20
30
CL - pF
Figure 9.
40
50
60
0
60 0
10
20
30
CL - pF
40
Figure 10.
CL - pF - 1.5
12
50
60
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F – DECEMBER 2003 – REVISED MAY 2005
PARAMETER MEASUREMENT INFORMATION
2 × VCCO
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCCO
GND
RL
tw
LOAD CIRCUIT
VCCI
VCCI/2
Input
VCCO
CL
RL
VTP
1.2 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
15 pF
15 pF
15 pF
15 pF
15 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
0.1 V
0.1 V
0.15 V
0.15 V
0.3 V
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VCCA
Output
Control
(low-level
enabling)
VCCA/2
VCCA/2
0V
tPZL
VCCI
Input
VCCI/2
VCCI/2
0V
tPLH
Output
tPHL
VCCO/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOH
VCCO/2
VOL
tPLZ
VCCO
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
VCCO/2
VOL + VTP
VOL
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
tPHZ
VCCO/2
VOH - VTP
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
Figure 11. Load Circuit and Voltage Waveforms
13
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F – DECEMBER 2003 – REVISED MAY 2005
APPLICATION INFORMATION
Figure 12 is an example circuit of the SN74AVC2T45 used in a bidirectional logic level-shifting application.
VCC1
VCC2
VCC1
VCC2
1
8
2
7
3
6
4
5
VCC2
VCC1
SYSTEM-1
SYSTEM-2
PIN
NAME
FUNCTION
1
VCCA
VCC1
SYSTEM-1 supply voltage (1.2 V to 3.6 V)
DESCRIPTION
2
A1
OUT1
Output level depends on VCC1 voltage.
3
A2
OUT2
Output level depends on VCC1 voltage.
4
GND
GND
Device GND
5
DIR
DIR
The GND (low-level) determines B-port to A-port direction.
6
B2
IN2
Input threshold value depends on VCC2 voltage.
7
B1
IN1
Input threshold value depends on VCC2 voltage.
8
VCCB
VCC2
SYSTEM-2 supply voltage (1.2 V to 3.6 V)
Figure 12. Bidirectional Logic Level-Shifting Application
14
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F – DECEMBER 2003 – REVISED MAY 2005
APPLICATION INFORMATION
Figure 13 shows the SN74AVC2T45 used in a bidirectional logic level-shifting application. Since the
SN74AVC2T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid
bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
VCC1
VCC1
I/O-1
VCC2
VCC2
Pullup/Pulldown
or Bus Hold(1)
Pullup/Pulldown
or Bus Hold(1)
1
8
2
7
3
6
4
5
I/O-2
DIR CTRL
SYSTEM-1
SYSTEM-2
Following is a sequence that illustrates data transmission from SYSTEM-1 to SYSTEM-2 and then from
SYSTEM-2 to SYSTEM-1.
(1)
STATE
DIR CTRL
I/O-1
I/O-2
1
H
Out
In
DESCRIPTION
2
H
Hi-Z
Hi-Z
SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are
disabled.
The bus-line state depends on pullup or pulldown. (1)
3
L
Hi-Z
Hi-Z
DIR bit is flipped. I/O-1 and I/O-2 still are disabled.
The bus-line state depends on pullup or pulldown. (1)
4
L
Out
In
SYSTEM-1 data to SYSTEM-2
SYSTEM-2 data to SYSTEM-1
SYSTEM-1 and SYSTEM-2 must use the same conditions, i.e., both pullup or both pulldown.
Figure 13. Bidirectional Logic Level-Shifting Application
Enable Times
Calculate the enable times for the SN74AVC2T45 using the following formulas:
• tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
• tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
• tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
• tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74AVC2T45 initially is transmitting from A to B, then
the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B
port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
15
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74AVC2T45DCTR
ACTIVE
SM8
DCT
8
3000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVC2T45DCTRE4
ACTIVE
SM8
DCT
8
3000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVC2T45DCTT
ACTIVE
SM8
DCT
8
250
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVC2T45DCUR
ACTIVE
US8
DCU
8
3000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVC2T45DCURE4
ACTIVE
US8
DCU
8
3000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVC2T45DCUT
ACTIVE
US8
DCU
8
250
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVC2T45DCUTE4
ACTIVE
US8
DCU
8
250
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVC2T45YEPR
ACTIVE
WCSP
YEP
8
3000
TBD
SNPB
Level-1-260C-UNLIM
SN74AVC2T45YZPR
ACTIVE
WCSP
YZP
8
3000
Pb-Free
(RoHS)
SNAGCU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
8
0,13 M
5
0,15 NOM
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
1
0,25
4
0° – 8°
3,15
2,75
0,60
0,20
1,30 MAX
Seating Plane
0,10
0,10
0,00
NOTES: A.
B.
C.
D.
4188781/C 09/02
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion
Falls within JEDEC MO-187 variation DA.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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